OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [socsim_plugin/] [irqctrl.h] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 sergeykhbr
/**
2
 * @file
3
 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
4
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
5
 * @brief      Interrupt controller functional model.
6
 */
7
 
8
#ifndef __DEBUGGER_SOCSIM_PLUGIN_IRQCTRL_H__
9
#define __DEBUGGER_SOCSIM_PLUGIN_IRQCTRL_H__
10
 
11
#include <iclass.h>
12
#include <iservice.h>
13
#include "coreservices/iclock.h"
14
#include "coreservices/imemop.h"
15
#include "coreservices/iwire.h"
16
#include "coreservices/icpugen.h"
17
 
18
namespace debugger {
19
 
20
class IrqPort : public IWire {
21
 public:
22
    IrqPort(IService *parent, const char *portname, int idx);
23
 
24
    /** IWire interface */
25
    virtual void raiseLine();
26
    virtual void lowerLine() { level_ = false; }
27
    virtual void setLevel(bool level);
28
    virtual bool getLevel() { return level_; }
29
 
30
 protected:
31
    IService *parent_;
32
    int idx_;
33
    bool level_;
34
};
35
 
36
class IrqController : public IService,
37
                      public IMemoryOperation,
38
                      public IClockListener {
39
 public:
40
    IrqController(const char *name);
41
    ~IrqController();
42
 
43
    /** IService interface */
44
    virtual void postinitService();
45
 
46
    /** IMemoryOperation */
47
    virtual ETransStatus b_transport(Axi4TransactionType *payload);
48
 
49
    /** IClockListener interface */
50
    virtual void stepCallback(uint64_t t);
51
 
52
    /** Controller specific methods visible for ports */
53
    void requestInterrupt(int idx);
54
 
55
 private:
56
    AttributeType mipi_;
57
    AttributeType irqTotal_;
58
    AttributeType cpu_;
59
    ICpuGeneric *icpu_;
60
    IClock *iclk_;
61
    static const int IRQ_MAX = 32;
62
    IrqPort *irqlines_[IRQ_MAX];
63
 
64
    struct irqctrl_map {
65
        uint32_t irq_mask;      // 0x00: [RW] 1=disable; 0=enable
66
        uint32_t irq_pending;   // 0x04: [RW]
67
        uint32_t irq_clear;     // 0x08: [WO]
68
        uint32_t irq_rise;      // 0x0c: [WO]
69
        uint64_t isr_table;     // 0x10: [RW]
70
        uint64_t dbg_cause;     // 0x18: [RW]
71
        uint64_t dbg_epc;       // 0x20: [RW]
72
        uint32_t irq_lock;      // 0x28: [RW]
73
        uint32_t irq_cause_idx; // 0x2c: [RW]
74
    } regs_;
75
};
76
 
77
DECLARE_CLASS(IrqController)
78
 
79
}  // namespace debugger
80
 
81
#endif  // __DEBUGGER_SOCSIM_PLUGIN_IRQCTRL_H__

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.