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sergeykhbr |
-----------------------------------------------------------------------------
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--! @file
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--! @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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--! @author Sergey Khabarov - sergeykhbr@gmail.com
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--! @brief Data Cache.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library commonlib;
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use commonlib.types_common.all;
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--! RIVER CPU specific library.
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library riverlib;
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--! RIVER CPU configuration constants.
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use riverlib.river_cfg.all;
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entity DCache is
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port (
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i_clk : in std_logic; -- CPU clock
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i_nrst : in std_logic; -- Reset. Active LOW.
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-- Data path:
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i_req_data_valid : in std_logic;
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i_req_data_write : in std_logic;
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i_req_data_sz : in std_logic_vector(1 downto 0);
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i_req_data_addr : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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i_req_data_data : in std_logic_vector(RISCV_ARCH-1 downto 0);
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o_req_data_ready : out std_logic;
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o_resp_data_valid : out std_logic;
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o_resp_data_addr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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o_resp_data_data : out std_logic_vector(RISCV_ARCH-1 downto 0);
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i_resp_data_ready : in std_logic;
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-- Memory interface:
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i_req_mem_ready : in std_logic;
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o_req_mem_valid : out std_logic;
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o_req_mem_write : out std_logic;
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o_req_mem_addr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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o_req_mem_strob : out std_logic_vector(BUS_DATA_BYTES-1 downto 0);
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o_req_mem_data : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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i_resp_mem_data_valid : in std_logic;
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i_resp_mem_data : in std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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-- Debug Signals:
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o_dstate : out std_logic_vector(1 downto 0)
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);
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end;
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architecture arch_DCache of DCache is
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constant State_Idle : std_logic_vector(1 downto 0) := "00";
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constant State_WaitGrant : std_logic_vector(1 downto 0) := "01";
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constant State_WaitResp : std_logic_vector(1 downto 0) := "10";
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constant State_WaitAccept : std_logic_vector(1 downto 0) := "11";
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type RegistersType is record
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dline_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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dline_addr_req : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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dline_size_req : std_logic_vector(1 downto 0);
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state : std_logic_vector(1 downto 0);
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end record;
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signal r, rin : RegistersType;
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begin
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comb : process(i_nrst, i_req_data_valid, i_req_data_write, i_req_data_sz,
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i_req_data_addr, i_req_data_data, i_resp_mem_data_valid,
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i_resp_mem_data, i_req_mem_ready, i_resp_data_ready, r)
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variable v : RegistersType;
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variable w_wait_response : std_logic;
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variable w_o_req_data_ready : std_logic;
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variable w_o_req_mem_valid : std_logic;
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variable wb_o_req_mem_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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variable wb_o_req_strob : std_logic_vector(BUS_DATA_BYTES-1 downto 0);
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variable wb_o_req_wdata : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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variable w_req_fire : std_logic;
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variable w_o_resp_valid : std_logic;
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variable wb_o_resp_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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variable wb_resp_data_mux : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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variable wb_o_resp_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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variable wb_rtmp : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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begin
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v := r;
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wb_o_req_strob := (others => '0');
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wb_o_req_wdata := (others => '0');
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wb_o_resp_data := (others => '0');
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wb_rtmp := (others => '0');
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w_wait_response := '0';
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if r.state = State_WaitResp and i_resp_mem_data_valid = '0' then
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w_wait_response := '1';
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end if;
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case i_req_data_sz is
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when "00" =>
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wb_o_req_wdata := i_req_data_data(7 downto 0) &
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i_req_data_data(7 downto 0) & i_req_data_data(7 downto 0) &
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i_req_data_data(7 downto 0) & i_req_data_data(7 downto 0) &
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i_req_data_data(7 downto 0) & i_req_data_data(7 downto 0) &
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i_req_data_data(7 downto 0);
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if i_req_data_addr(2 downto 0) = "000" then
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wb_o_req_strob := X"01";
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elsif i_req_data_addr(2 downto 0) = "001" then
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wb_o_req_strob := X"02";
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elsif i_req_data_addr(2 downto 0) = "010" then
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wb_o_req_strob := X"04";
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elsif i_req_data_addr(2 downto 0) = "011" then
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wb_o_req_strob := X"08";
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elsif i_req_data_addr(2 downto 0) = "100" then
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wb_o_req_strob := X"10";
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elsif i_req_data_addr(2 downto 0) = "101" then
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wb_o_req_strob := X"20";
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elsif i_req_data_addr(2 downto 0) = "110" then
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wb_o_req_strob := X"40";
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elsif i_req_data_addr(2 downto 0) = "111" then
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wb_o_req_strob := X"80";
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end if;
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when "01" =>
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wb_o_req_wdata := i_req_data_data(15 downto 0) &
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i_req_data_data(15 downto 0) & i_req_data_data(15 downto 0) &
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i_req_data_data(15 downto 0);
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if i_req_data_addr(2 downto 1) = "00" then
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wb_o_req_strob := X"03";
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elsif i_req_data_addr(2 downto 1) = "01" then
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wb_o_req_strob := X"0C";
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elsif i_req_data_addr(2 downto 1) = "10" then
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wb_o_req_strob := X"30";
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else
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wb_o_req_strob := X"C0";
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end if;
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when "10" =>
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wb_o_req_wdata := i_req_data_data(31 downto 0) &
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i_req_data_data(31 downto 0);
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if i_req_data_addr(2) = '1' then
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wb_o_req_strob := X"F0";
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else
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wb_o_req_strob := X"0F";
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end if;
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when "11" =>
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wb_o_req_wdata := i_req_data_data;
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wb_o_req_strob := X"FF";
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when others =>
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end case;
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w_o_req_mem_valid := i_req_data_valid and not w_wait_response;
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wb_o_req_mem_addr := i_req_data_addr(BUS_ADDR_WIDTH-1 downto 3) & "000";
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w_o_req_data_ready := i_req_mem_ready;
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w_req_fire := w_o_req_mem_valid and w_o_req_data_ready;
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case r.state is
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when State_Idle =>
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if i_req_data_valid = '1' then
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if i_req_mem_ready = '1' then
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v.state := State_WaitResp;
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else
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v.state := State_WaitGrant;
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end if;
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end if;
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when State_WaitGrant =>
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if i_req_mem_ready = '1' then
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v.state := State_WaitResp;
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end if;
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when State_WaitResp =>
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if i_resp_mem_data_valid = '1' then
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if i_resp_data_ready = '0' then
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v.state := State_WaitAccept;
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elsif i_req_data_valid = '0' then
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v.state := State_Idle;
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else
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-- New request
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if i_req_mem_ready = '1' then
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v.state := State_WaitResp;
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else
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v.state := State_WaitGrant;
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end if;
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end if;
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end if;
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when State_WaitAccept =>
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if i_resp_data_ready = '1' then
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if i_req_data_valid = '0' then
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v.state := State_Idle;
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else
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if i_req_mem_ready = '1' then
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v.state := State_WaitResp;
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else
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v.state := State_WaitGrant;
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end if;
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end if;
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end if;
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when others =>
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end case;
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if w_req_fire = '1' then
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v.dline_addr_req := i_req_data_addr;
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v.dline_size_req := i_req_data_sz;
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end if;
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if i_resp_mem_data_valid = '1' then
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v.dline_data := i_resp_mem_data;
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end if;
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wb_o_resp_addr := r.dline_addr_req;
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if r.state = State_WaitAccept then
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w_o_resp_valid := '1';
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wb_resp_data_mux := r.dline_data;
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else
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w_o_resp_valid := i_resp_mem_data_valid;
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wb_resp_data_mux := i_resp_mem_data;
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end if;
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case r.dline_addr_req(2 downto 0) is
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when "001" =>
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wb_rtmp := X"00" & wb_resp_data_mux(63 downto 8);
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when "010" =>
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wb_rtmp := X"0000" & wb_resp_data_mux(63 downto 16);
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when "011" =>
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wb_rtmp := X"000000" & wb_resp_data_mux(63 downto 24);
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when "100" =>
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wb_rtmp := X"00000000" & wb_resp_data_mux(63 downto 32);
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when "101" =>
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wb_rtmp := X"0000000000" & wb_resp_data_mux(63 downto 40);
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when "110" =>
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wb_rtmp := X"000000000000" & wb_resp_data_mux(63 downto 48);
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when "111" =>
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wb_rtmp := X"00000000000000" & wb_resp_data_mux(63 downto 56);
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when others =>
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wb_rtmp := wb_resp_data_mux;
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end case;
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case r.dline_size_req is
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when "00" =>
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wb_o_resp_data(7 downto 0) := wb_rtmp(7 downto 0);
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when "01" =>
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wb_o_resp_data(15 downto 0) := wb_rtmp(15 downto 0);
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when "10" =>
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wb_o_resp_data(31 downto 0) := wb_rtmp(31 downto 0);
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when others =>
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wb_o_resp_data := wb_rtmp;
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end case;
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if i_nrst = '0' then
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v.dline_addr_req := (others => '0');
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v.dline_size_req := (others => '0');
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v.dline_data := (others => '0');
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v.state := State_Idle;
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end if;
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o_req_data_ready <= w_o_req_data_ready;
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o_req_mem_valid <= w_o_req_mem_valid;
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o_req_mem_addr <= wb_o_req_mem_addr;
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o_req_mem_write <= i_req_data_write;
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o_req_mem_strob <= wb_o_req_strob;
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o_req_mem_data <= wb_o_req_wdata;
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o_resp_data_valid <= w_o_resp_valid;
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o_resp_data_data <= wb_o_resp_data;
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o_resp_data_addr <= wb_o_resp_addr;
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o_dstate <= r.state;
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rin <= v;
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end process;
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-- registers:
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regs : process(i_clk)
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begin
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if rising_edge(i_clk) then
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r <= rin;
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end if;
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end process;
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end;
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