1 |
5 |
sergeykhbr |
-----------------------------------------------------------------------------
|
2 |
|
|
--! @file
|
3 |
|
|
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
|
4 |
|
|
--! @author Sergey Khabarov - sergeykhbr@gmail.com
|
5 |
|
|
--! @brief TileLink-to-AXI4 bridge implementation.
|
6 |
|
|
------------------------------------------------------------------------------
|
7 |
|
|
|
8 |
|
|
library ieee;
|
9 |
|
|
use ieee.std_logic_1164.all;
|
10 |
|
|
library commonlib;
|
11 |
|
|
use commonlib.types_common.all;
|
12 |
|
|
--! AMBA system bus specific library.
|
13 |
|
|
library ambalib;
|
14 |
|
|
--! AXI4 configuration constants.
|
15 |
|
|
use ambalib.types_amba4.all;
|
16 |
|
|
library rocketlib;
|
17 |
|
|
use rocketlib.types_rocket.all;
|
18 |
|
|
|
19 |
|
|
entity Tile2Axi is
|
20 |
|
|
port (
|
21 |
|
|
clk : in std_logic;
|
22 |
|
|
nrst : in std_logic;
|
23 |
|
|
|
24 |
|
|
--! Tile-to-AXI direction
|
25 |
|
|
tloi : in tile_out_type;
|
26 |
|
|
msto : out nasti_master_out_type;
|
27 |
|
|
--! AXI-to-Tile direction
|
28 |
|
|
msti : in nasti_master_in_type;
|
29 |
|
|
tlio : out tile_in_type
|
30 |
|
|
);
|
31 |
|
|
end;
|
32 |
|
|
|
33 |
|
|
architecture arch_Tile2Axi of Tile2Axi is
|
34 |
|
|
|
35 |
|
|
component TLToAXI4
|
36 |
|
|
port (
|
37 |
|
|
clock : in std_logic;
|
38 |
|
|
reset : in std_logic;
|
39 |
|
|
io_in_0_a_ready : out std_logic;
|
40 |
|
|
io_in_0_a_valid : in std_logic;
|
41 |
|
|
io_in_0_a_bits_opcode : in std_logic_vector(2 downto 0);
|
42 |
|
|
io_in_0_a_bits_param : in std_logic_vector(2 downto 0);
|
43 |
|
|
io_in_0_a_bits_size : in std_logic_vector(3 downto 0);
|
44 |
|
|
io_in_0_a_bits_source : in std_logic_vector(5 downto 0);
|
45 |
|
|
io_in_0_a_bits_address : in std_logic_vector(31 downto 0);
|
46 |
|
|
io_in_0_a_bits_mask : in std_logic_vector(7 downto 0);
|
47 |
|
|
io_in_0_a_bits_data : in std_logic_vector(63 downto 0);
|
48 |
|
|
io_in_0_b_ready : in std_logic;
|
49 |
|
|
io_in_0_b_valid : out std_logic;
|
50 |
|
|
io_in_0_b_bits_opcode : out std_logic_vector(2 downto 0);
|
51 |
|
|
io_in_0_b_bits_param : out std_logic_vector(1 downto 0);
|
52 |
|
|
io_in_0_b_bits_size : out std_logic_vector(3 downto 0);
|
53 |
|
|
io_in_0_b_bits_source : out std_logic_vector(5 downto 0);
|
54 |
|
|
io_in_0_b_bits_address : out std_logic_vector(31 downto 0);
|
55 |
|
|
io_in_0_b_bits_mask : out std_logic_vector(7 downto 0);
|
56 |
|
|
io_in_0_b_bits_data : out std_logic_vector(63 downto 0);
|
57 |
|
|
io_in_0_c_ready : out std_logic;
|
58 |
|
|
io_in_0_c_valid : in std_logic;
|
59 |
|
|
io_in_0_c_bits_opcode : in std_logic_vector(2 downto 0);
|
60 |
|
|
io_in_0_c_bits_param : in std_logic_vector(2 downto 0);
|
61 |
|
|
io_in_0_c_bits_size : in std_logic_vector(3 downto 0);
|
62 |
|
|
io_in_0_c_bits_source : in std_logic_vector(5 downto 0);
|
63 |
|
|
io_in_0_c_bits_address : in std_logic_vector(31 downto 0);
|
64 |
|
|
io_in_0_c_bits_data : in std_logic_vector(63 downto 0);
|
65 |
|
|
io_in_0_c_bits_error : in std_logic;
|
66 |
|
|
io_in_0_d_ready : in std_logic;
|
67 |
|
|
io_in_0_d_valid : out std_logic;
|
68 |
|
|
io_in_0_d_bits_opcode : out std_logic_vector(2 downto 0);
|
69 |
|
|
io_in_0_d_bits_param : out std_logic_vector(1 downto 0);
|
70 |
|
|
io_in_0_d_bits_size : out std_logic_vector(3 downto 0);
|
71 |
|
|
io_in_0_d_bits_source : out std_logic_vector(5 downto 0);
|
72 |
|
|
io_in_0_d_bits_sink : out std_logic;
|
73 |
|
|
io_in_0_d_bits_addr_lo : out std_logic_vector(2 downto 0);
|
74 |
|
|
io_in_0_d_bits_data : out std_logic_vector(63 downto 0);
|
75 |
|
|
io_in_0_d_bits_error : out std_logic;
|
76 |
|
|
io_in_0_e_ready : out std_logic;
|
77 |
|
|
io_in_0_e_valid : in std_logic;
|
78 |
|
|
io_in_0_e_bits_sink : in std_logic;
|
79 |
|
|
io_out_0_aw_ready : in std_logic;
|
80 |
|
|
io_out_0_aw_valid : out std_logic;
|
81 |
|
|
io_out_0_aw_bits_id : out std_logic_vector(3 downto 0);
|
82 |
|
|
io_out_0_aw_bits_addr : out std_logic_vector(31 downto 0);
|
83 |
|
|
io_out_0_aw_bits_len : out std_logic_vector(7 downto 0);
|
84 |
|
|
io_out_0_aw_bits_size : out std_logic_vector(2 downto 0);
|
85 |
|
|
io_out_0_aw_bits_burst : out std_logic_vector(1 downto 0);
|
86 |
|
|
io_out_0_aw_bits_lock : out std_logic;
|
87 |
|
|
io_out_0_aw_bits_cache : out std_logic_vector(3 downto 0);
|
88 |
|
|
io_out_0_aw_bits_prot : out std_logic_vector(2 downto 0);
|
89 |
|
|
io_out_0_aw_bits_qos : out std_logic_vector(3 downto 0);
|
90 |
|
|
io_out_0_w_ready : in std_logic;
|
91 |
|
|
io_out_0_w_valid : out std_logic;
|
92 |
|
|
io_out_0_w_bits_data : out std_logic_vector(63 downto 0);
|
93 |
|
|
io_out_0_w_bits_strb : out std_logic_vector(7 downto 0);
|
94 |
|
|
io_out_0_w_bits_last : out std_logic;
|
95 |
|
|
io_out_0_b_ready : out std_logic;
|
96 |
|
|
io_out_0_b_valid : in std_logic;
|
97 |
|
|
io_out_0_b_bits_id : in std_logic_vector(3 downto 0);
|
98 |
|
|
io_out_0_b_bits_resp : in std_logic_vector(1 downto 0);
|
99 |
|
|
io_out_0_ar_ready : in std_logic;
|
100 |
|
|
io_out_0_ar_valid : out std_logic;
|
101 |
|
|
io_out_0_ar_bits_id : out std_logic_vector(3 downto 0);
|
102 |
|
|
io_out_0_ar_bits_addr : out std_logic_vector(31 downto 0);
|
103 |
|
|
io_out_0_ar_bits_len : out std_logic_vector(7 downto 0);
|
104 |
|
|
io_out_0_ar_bits_size : out std_logic_vector(2 downto 0);
|
105 |
|
|
io_out_0_ar_bits_burst : out std_logic_vector(1 downto 0);
|
106 |
|
|
io_out_0_ar_bits_lock : out std_logic;
|
107 |
|
|
io_out_0_ar_bits_cache : out std_logic_vector(3 downto 0);
|
108 |
|
|
io_out_0_ar_bits_prot : out std_logic_vector(2 downto 0);
|
109 |
|
|
io_out_0_ar_bits_qos : out std_logic_vector(3 downto 0);
|
110 |
|
|
io_out_0_r_ready : out std_logic;
|
111 |
|
|
io_out_0_r_valid : in std_logic;
|
112 |
|
|
io_out_0_r_bits_id : in std_logic_vector(3 downto 0);
|
113 |
|
|
io_out_0_r_bits_data : in std_logic_vector(63 downto 0);
|
114 |
|
|
io_out_0_r_bits_resp : in std_logic_vector(1 downto 0);
|
115 |
|
|
io_out_0_r_bits_last : in std_logic
|
116 |
|
|
);
|
117 |
|
|
end component;
|
118 |
|
|
|
119 |
|
|
signal reset : std_logic;
|
120 |
|
|
signal wb_a_source : std_logic_vector(5 downto 0);
|
121 |
|
|
signal wb_b_source : std_logic_vector(5 downto 0);
|
122 |
|
|
signal wb_c_source : std_logic_vector(5 downto 0);
|
123 |
|
|
signal wb_d_source : std_logic_vector(5 downto 0);
|
124 |
|
|
signal wb_aw_bits_addr : std_logic_vector(31 downto 0);
|
125 |
|
|
signal wb_ar_bits_addr : std_logic_vector(31 downto 0);
|
126 |
|
|
|
127 |
|
|
begin
|
128 |
|
|
|
129 |
|
|
reset <= not nrst;
|
130 |
|
|
wb_a_source <= "000" & tloi.a_source;
|
131 |
|
|
tlio.b_source <= wb_b_source(2 downto 0);
|
132 |
|
|
wb_c_source <= "000" & tloi.c_source;
|
133 |
|
|
tlio.d_source <= wb_d_source(2 downto 0);
|
134 |
|
|
tlio.d_sink(3 downto 1) <= "000";
|
135 |
|
|
|
136 |
|
|
ver0 : TLToAXI4 port map (
|
137 |
|
|
clock => clk,
|
138 |
|
|
reset => reset,
|
139 |
|
|
io_in_0_a_ready => tlio.a_ready,
|
140 |
|
|
io_in_0_a_valid => tloi.a_valid,
|
141 |
|
|
io_in_0_a_bits_opcode => tloi.a_opcode,
|
142 |
|
|
io_in_0_a_bits_param => tloi.a_param,
|
143 |
|
|
io_in_0_a_bits_size => tloi.a_size,
|
144 |
|
|
io_in_0_a_bits_source => wb_a_source,
|
145 |
|
|
io_in_0_a_bits_address => tloi.a_address,
|
146 |
|
|
io_in_0_a_bits_mask => tloi.a_mask,
|
147 |
|
|
io_in_0_a_bits_data => tloi.a_data,
|
148 |
|
|
io_in_0_b_ready => tloi.b_ready,
|
149 |
|
|
io_in_0_b_valid => tlio.b_valid,
|
150 |
|
|
io_in_0_b_bits_opcode => tlio.b_opcode,
|
151 |
|
|
io_in_0_b_bits_param => tlio.b_param,
|
152 |
|
|
io_in_0_b_bits_size => tlio.b_size,
|
153 |
|
|
io_in_0_b_bits_source => wb_b_source,
|
154 |
|
|
io_in_0_b_bits_address => tlio.b_address,
|
155 |
|
|
io_in_0_b_bits_mask => tlio.b_mask,
|
156 |
|
|
io_in_0_b_bits_data => tlio.b_data,
|
157 |
|
|
io_in_0_c_ready => tlio.c_ready,
|
158 |
|
|
io_in_0_c_valid => tloi.c_valid,
|
159 |
|
|
io_in_0_c_bits_opcode => tloi.c_opcode,
|
160 |
|
|
io_in_0_c_bits_param => tloi.c_param,
|
161 |
|
|
io_in_0_c_bits_size => tloi.c_size,
|
162 |
|
|
io_in_0_c_bits_source => wb_c_source,
|
163 |
|
|
io_in_0_c_bits_address => tloi.c_address,
|
164 |
|
|
io_in_0_c_bits_data => tloi.c_data,
|
165 |
|
|
io_in_0_c_bits_error => tloi.c_error,
|
166 |
|
|
io_in_0_d_ready => tloi.d_ready,
|
167 |
|
|
io_in_0_d_valid => tlio.d_valid,
|
168 |
|
|
io_in_0_d_bits_opcode => tlio.d_opcode,
|
169 |
|
|
io_in_0_d_bits_param => tlio.d_param,
|
170 |
|
|
io_in_0_d_bits_size => tlio.d_size,
|
171 |
|
|
io_in_0_d_bits_source => wb_d_source,
|
172 |
|
|
io_in_0_d_bits_sink => tlio.d_sink(0),
|
173 |
|
|
io_in_0_d_bits_addr_lo => tlio.d_addr_lo,
|
174 |
|
|
io_in_0_d_bits_data => tlio.d_data,
|
175 |
|
|
io_in_0_d_bits_error => tlio.d_error,
|
176 |
|
|
io_in_0_e_ready => tlio.e_ready,
|
177 |
|
|
io_in_0_e_valid => tloi.e_valid,
|
178 |
|
|
io_in_0_e_bits_sink => tloi.e_sink(0),
|
179 |
|
|
io_out_0_aw_ready => msti.aw_ready,
|
180 |
|
|
io_out_0_aw_valid => msto.aw_valid,
|
181 |
|
|
io_out_0_aw_bits_id => msto.aw_id(3 downto 0),
|
182 |
|
|
io_out_0_aw_bits_addr => wb_aw_bits_addr,
|
183 |
|
|
io_out_0_aw_bits_len => msto.aw_bits.len,
|
184 |
|
|
io_out_0_aw_bits_size => msto.aw_bits.size,
|
185 |
|
|
io_out_0_aw_bits_burst => msto.aw_bits.burst,
|
186 |
|
|
io_out_0_aw_bits_lock => msto.aw_bits.lock,
|
187 |
|
|
io_out_0_aw_bits_cache => msto.aw_bits.cache,
|
188 |
|
|
io_out_0_aw_bits_prot => msto.aw_bits.prot,
|
189 |
|
|
io_out_0_aw_bits_qos => msto.aw_bits.qos,
|
190 |
|
|
io_out_0_w_ready => msti.w_ready,
|
191 |
|
|
io_out_0_w_valid => msto.w_valid,
|
192 |
|
|
io_out_0_w_bits_data => msto.w_data,
|
193 |
|
|
io_out_0_w_bits_strb => msto.w_strb,
|
194 |
|
|
io_out_0_w_bits_last => msto.w_last,
|
195 |
|
|
io_out_0_b_ready => msto.b_ready,
|
196 |
|
|
io_out_0_b_valid => msti.b_valid,
|
197 |
|
|
io_out_0_b_bits_id => msti.b_id(3 downto 0),
|
198 |
|
|
io_out_0_b_bits_resp => msti.b_resp,
|
199 |
|
|
io_out_0_ar_ready => msti.ar_ready,
|
200 |
|
|
io_out_0_ar_valid => msto.ar_valid,
|
201 |
|
|
io_out_0_ar_bits_id => msto.ar_id(3 downto 0),
|
202 |
|
|
io_out_0_ar_bits_addr => wb_ar_bits_addr,
|
203 |
|
|
io_out_0_ar_bits_len => msto.ar_bits.len,
|
204 |
|
|
io_out_0_ar_bits_size => msto.ar_bits.size,
|
205 |
|
|
io_out_0_ar_bits_burst => msto.ar_bits.burst,
|
206 |
|
|
io_out_0_ar_bits_lock => msto.ar_bits.lock,
|
207 |
|
|
io_out_0_ar_bits_cache => msto.ar_bits.cache,
|
208 |
|
|
io_out_0_ar_bits_prot => msto.ar_bits.prot,
|
209 |
|
|
io_out_0_ar_bits_qos => msto.ar_bits.qos,
|
210 |
|
|
io_out_0_r_ready => msto.r_ready,
|
211 |
|
|
io_out_0_r_valid => msti.r_valid,
|
212 |
|
|
io_out_0_r_bits_id => msti.r_id(3 downto 0),
|
213 |
|
|
io_out_0_r_bits_data => msti.r_data,
|
214 |
|
|
io_out_0_r_bits_resp => msti.r_resp,
|
215 |
|
|
io_out_0_r_bits_last => msti.r_last
|
216 |
|
|
);
|
217 |
|
|
|
218 |
|
|
msto.aw_bits.addr <= wb_aw_bits_addr(31 downto 3) & "000";
|
219 |
|
|
msto.ar_bits.addr <= wb_ar_bits_addr(31 downto 3) & "000";
|
220 |
|
|
|
221 |
|
|
end;
|