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rud_dp |
///*************************************************************///
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/// ///
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/// Reed-Solomon Decoder (31,19,6) ///
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/// ///
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/// ///
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/// Author : Rudy Dwi Putra ///
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/// rudy.dp@gmail.com ///
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/// ///
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///*************************************************************///
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/// ///
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/// Copyright (C) 2006 Rudy Dwi Putra ///
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/// rudy.dp@gmail.com ///
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/// ///
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/// This source file may be used and distributed without ///
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/// restriction provided that this copyright statement is not ///
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/// removed from the file and that any derivative work contains ///
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/// the original copyright notice and the associated disclaimer.///
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/// ///
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/// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ///
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/// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ///
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/// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ///
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/// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ///
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/// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ///
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/// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ///
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/// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ///
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/// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ///
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/// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ///
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/// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ///
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/// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ///
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/// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ///
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/// POSSIBILITY OF SUCH DAMAGE. ///
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/// ///
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///*************************************************************///
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module RSDecoder(recword, start, clock1, clock2, reset, ready,
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errfound, decode_fail, dataoutstart, dataoutend,
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corr_recword);
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input [4:0] recword;
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input clock1, clock2;
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input start, reset;
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output ready, decode_fail, errfound, dataoutstart, dataoutend;
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output [4:0] corr_recword;
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wire active_sc, active_kes, active_csee, en_sccell;
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wire evalsynd, holdsynd, evalerror, lastdataout;
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wire shift_fifo, hold_fifo, en_infifo, en_outfifo;
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wire errdetect, finish_kes;
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wire [4:0] dataout_fifo, errorvalue;
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wire [4:0] syndvalue0, syndvalue1, syndvalue2, syndvalue3,
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syndvalue4, syndvalue5, syndvalue6, syndvalue7,
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syndvalue8, syndvalue9, syndvalue10, syndvalue11;
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wire [4:0] lambda0, lambda1, lambda2, lambda3, lambda4, lambda5,
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lambda6;
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wire [4:0] homega0, homega1, homega2, homega3, homega4, homega5;
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wire [2:0] rootcntr, lambda_degree;
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//****************************//
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assign en_sccell = shift_fifo;
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SCblock SCblock(recword, clock1, clock2, active_sc, reset, syndvalue0,
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syndvalue1, syndvalue2, syndvalue3, syndvalue4,
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syndvalue5, syndvalue6, syndvalue7, syndvalue8,
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syndvalue9, syndvalue10, syndvalue11, errdetect,
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en_sccell, evalsynd, holdsynd);
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KES_block KESblock(active_kes, clock1, clock2, reset, syndvalue0, syndvalue1, syndvalue2, syndvalue3, syndvalue4, syndvalue5, syndvalue6,
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syndvalue7, syndvalue8, syndvalue9, syndvalue10, syndvalue11,
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lambda0, lambda1, lambda2, lambda3, lambda4, lambda5,
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lambda6, homega0, homega1, homega2, homega3, homega4,
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homega5, lambda_degree, finish_kes);
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CSEEblock CSEEblock(lambda0, lambda1, lambda2, lambda3, lambda4,
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lambda5, lambda6, homega0, homega1, homega2,
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homega3, homega4, homega5, errorvalue, clock1,
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clock2, active_csee, reset, lastdataout, evalerror,
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en_outfifo, rootcntr);
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MainControl controller(start, reset, clock1, clock2, finish_kes,
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errdetect, rootcntr, lambda_degree, active_sc,
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active_kes, active_csee, evalsynd, holdsynd,
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errfound, decode_fail, ready, dataoutstart, dataoutend,
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shift_fifo, hold_fifo, en_infifo, en_outfifo,
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lastdataout, evalerror);
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fifo_register fiforeg(clock1, clock2, shift_fifo, hold_fifo,
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en_outfifo, en_infifo, recword, dataout_fifo);
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// Received word correction//
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gfadder adder(errorvalue, dataout_fifo, corr_recword);
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endmodule
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