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1 2 farooq21 
// This is a verilog File Generated
2 
// By The C++ program That Generates
3 
// An Gallios Field Hardware Multiplier
4 
 
5 
module GF8Mult0(mult_i, mult_o);
6 
  // Inputs are declared here
7 
  input [7:0] mult_i;
8 
  output [7:0] mult_o;
9 
 
10 
  // Declaration of Wires And Register are here
11 
 
12 
  // Combinational Logic Body
13 
  assign mult_o[0] = mult_i[0];
14 
  assign mult_o[1] = mult_i[1];
15 
  assign mult_o[2] = mult_i[2];
16 
  assign mult_o[3] = mult_i[3];
17 
  assign mult_o[4] = mult_i[4];
18 
  assign mult_o[5] = mult_i[5];
19 
  assign mult_o[6] = mult_i[6];
20 
  assign mult_o[7] = mult_i[7];
21 
 
22 
 
23 
endmodule
24 
 
25 
// This is a verilog File Generated
26 
// By The C++ program That Generates
27 
// An Gallios Field Hardware Multiplier
28 
 
29 
module GF8Mult1(mult_i, mult_o);
30 
  // Inputs are declared here
31 
  input [7:0] mult_i;
32 
  output [7:0] mult_o;
33 
 
34 
  // Declaration of Wires And Register are here
35 
 
36 
  // Combinational Logic Body
37 
  assign mult_o[0] = mult_i[7];
38 
  assign mult_o[1] = mult_i[0];
39 
  assign mult_o[2] = mult_i[7]^mult_i[1];
40 
  assign mult_o[3] = mult_i[7]^mult_i[2];
41 
  assign mult_o[4] = mult_i[7]^mult_i[3];
42 
  assign mult_o[5] = mult_i[4];
43 
  assign mult_o[6] = mult_i[5];
44 
  assign mult_o[7] = mult_i[6];
45 
 
46 
 
47 
endmodule
48 
 
49 
// This is a verilog File Generated
50 
// By The C++ program That Generates
51 
// An Gallios Field Hardware Multiplier
52 
 
53 
module GF8Mult2(mult_i, mult_o);
54 
  // Inputs are declared here
55 
  input [7:0] mult_i;
56 
  output [7:0] mult_o;
57 
 
58 
  // Declaration of Wires And Register are here
59 
 
60 
  // Combinational Logic Body
61 
  assign mult_o[0] = mult_i[6];
62 
  assign mult_o[1] = mult_i[7];
63 
  assign mult_o[2] = mult_i[6]^mult_i[0];
64 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[1];
65 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[2];
66 
  assign mult_o[5] = mult_i[7]^mult_i[3];
67 
  assign mult_o[6] = mult_i[4];
68 
  assign mult_o[7] = mult_i[5];
69 
 
70 
 
71 
endmodule
72 
 
73 
// This is a verilog File Generated
74 
// By The C++ program That Generates
75 
// An Gallios Field Hardware Multiplier
76 
 
77 
module GF8Mult3(mult_i, mult_o);
78 
  // Inputs are declared here
79 
  input [7:0] mult_i;
80 
  output [7:0] mult_o;
81 
 
82 
  // Declaration of Wires And Register are here
83 
 
84 
  // Combinational Logic Body
85 
  assign mult_o[0] = mult_i[5];
86 
  assign mult_o[1] = mult_i[6];
87 
  assign mult_o[2] = mult_i[7]^mult_i[5];
88 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[0];
89 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
90 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[2];
91 
  assign mult_o[6] = mult_i[7]^mult_i[3];
92 
  assign mult_o[7] = mult_i[4];
93 
 
94 
 
95 
endmodule
96 
 
97 
// This is a verilog File Generated
98 
// By The C++ program That Generates
99 
// An Gallios Field Hardware Multiplier
100 
 
101 
module GF8Mult4(mult_i, mult_o);
102 
  // Inputs are declared here
103 
  input [7:0] mult_i;
104 
  output [7:0] mult_o;
105 
 
106 
  // Declaration of Wires And Register are here
107 
 
108 
  // Combinational Logic Body
109 
  assign mult_o[0] = mult_i[4];
110 
  assign mult_o[1] = mult_i[5];
111 
  assign mult_o[2] = mult_i[6]^mult_i[4];
112 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4];
113 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
114 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
115 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[2];
116 
  assign mult_o[7] = mult_i[7]^mult_i[3];
117 
 
118 
 
119 
endmodule
120 
 
121 
// This is a verilog File Generated
122 
// By The C++ program That Generates
123 
// An Gallios Field Hardware Multiplier
124 
 
125 
module GF8Mult5(mult_i, mult_o);
126 
  // Inputs are declared here
127 
  input [7:0] mult_i;
128 
  output [7:0] mult_o;
129 
 
130 
  // Declaration of Wires And Register are here
131 
 
132 
  // Combinational Logic Body
133 
  assign mult_o[0] = mult_i[7]^mult_i[3];
134 
  assign mult_o[1] = mult_i[4];
135 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3];
136 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
137 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3];
138 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
139 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
140 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[2];
141 
 
142 
 
143 
endmodule
144 
 
145 
// This is a verilog File Generated
146 
// By The C++ program That Generates
147 
// An Gallios Field Hardware Multiplier
148 
 
149 
module GF8Mult6(mult_i, mult_o);
150 
  // Inputs are declared here
151 
  input [7:0] mult_i;
152 
  output [7:0] mult_o;
153 
 
154 
  // Declaration of Wires And Register are here
155 
 
156 
  // Combinational Logic Body
157 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[2];
158 
  assign mult_o[1] = mult_i[7]^mult_i[3];
159 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
160 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
161 
  assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[2];
162 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3];
163 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
164 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
165 
 
166 
 
167 
endmodule
168 
 
169 
// This is a verilog File Generated
170 
// By The C++ program That Generates
171 
// An Gallios Field Hardware Multiplier
172 
 
173 
module GF8Mult7(mult_i, mult_o);
174 
  // Inputs are declared here
175 
  input [7:0] mult_i;
176 
  output [7:0] mult_o;
177 
 
178 
  // Declaration of Wires And Register are here
179 
 
180 
  // Combinational Logic Body
181 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
182 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[2];
183 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
184 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
185 
  assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
186 
  assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[2];
187 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3];
188 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
189 
 
190 
 
191 
endmodule
192 
 
193 
// This is a verilog File Generated
194 
// By The C++ program That Generates
195 
// An Gallios Field Hardware Multiplier
196 
 
197 
module GF8Mult8(mult_i, mult_o);
198 
  // Inputs are declared here
199 
  input [7:0] mult_i;
200 
  output [7:0] mult_o;
201 
 
202 
  // Declaration of Wires And Register are here
203 
 
204 
  // Combinational Logic Body
205 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
206 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
207 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
208 
  assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
209 
  assign mult_o[4] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
210 
  assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
211 
  assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[2];
212 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3];
213 
 
214 
 
215 
endmodule
216 
 
217 
// This is a verilog File Generated
218 
// By The C++ program That Generates
219 
// An Gallios Field Hardware Multiplier
220 
 
221 
module GF8Mult9(mult_i, mult_o);
222 
  // Inputs are declared here
223 
  input [7:0] mult_i;
224 
  output [7:0] mult_o;
225 
 
226 
  // Declaration of Wires And Register are here
227 
 
228 
  // Combinational Logic Body
229 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3];
230 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
231 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
232 
  assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
233 
  assign mult_o[4] = mult_i[5]^mult_i[1]^mult_i[0];
234 
  assign mult_o[5] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
235 
  assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
236 
  assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[2];
237 
 
238 
 
239 
endmodule
240 
 
241 
// This is a verilog File Generated
242 
// By The C++ program That Generates
243 
// An Gallios Field Hardware Multiplier
244 
 
245 
module GF8Mult10(mult_i, mult_o);
246 
  // Inputs are declared here
247 
  input [7:0] mult_i;
248 
  output [7:0] mult_o;
249 
 
250 
  // Declaration of Wires And Register are here
251 
 
252 
  // Combinational Logic Body
253 
  assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[2];
254 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3];
255 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
256 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
257 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[0];
258 
  assign mult_o[5] = mult_i[5]^mult_i[1]^mult_i[0];
259 
  assign mult_o[6] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
260 
  assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
261 
 
262 
 
263 
endmodule
264 
 
265 
// This is a verilog File Generated
266 
// By The C++ program That Generates
267 
// An Gallios Field Hardware Multiplier
268 
 
269 
module GF8Mult11(mult_i, mult_o);
270 
  // Inputs are declared here
271 
  input [7:0] mult_i;
272 
  output [7:0] mult_o;
273 
 
274 
  // Declaration of Wires And Register are here
275 
 
276 
  // Combinational Logic Body
277 
  assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
278 
  assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[2];
279 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
280 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
281 
  assign mult_o[4] = mult_i[6]^mult_i[3];
282 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[0];
283 
  assign mult_o[6] = mult_i[5]^mult_i[1]^mult_i[0];
284 
  assign mult_o[7] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
285 
 
286 
 
287 
endmodule
288 
 
289 
// This is a verilog File Generated
290 
// By The C++ program That Generates
291 
// An Gallios Field Hardware Multiplier
292 
 
293 
module GF8Mult12(mult_i, mult_o);
294 
  // Inputs are declared here
295 
  input [7:0] mult_i;
296 
  output [7:0] mult_o;
297 
 
298 
  // Declaration of Wires And Register are here
299 
 
300 
  // Combinational Logic Body
301 
  assign mult_o[0] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
302 
  assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
303 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
304 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
305 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[2];
306 
  assign mult_o[5] = mult_i[6]^mult_i[3];
307 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[0];
308 
  assign mult_o[7] = mult_i[5]^mult_i[1]^mult_i[0];
309 
 
310 
 
311 
endmodule
312 
 
313 
// This is a verilog File Generated
314 
// By The C++ program That Generates
315 
// An Gallios Field Hardware Multiplier
316 
 
317 
module GF8Mult13(mult_i, mult_o);
318 
  // Inputs are declared here
319 
  input [7:0] mult_i;
320 
  output [7:0] mult_o;
321 
 
322 
  // Declaration of Wires And Register are here
323 
 
324 
  // Combinational Logic Body
325 
  assign mult_o[0] = mult_i[5]^mult_i[1]^mult_i[0];
326 
  assign mult_o[1] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
327 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
328 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
329 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
330 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[2];
331 
  assign mult_o[6] = mult_i[6]^mult_i[3];
332 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[0];
333 
 
334 
 
335 
endmodule
336 
 
337 
// This is a verilog File Generated
338 
// By The C++ program That Generates
339 
// An Gallios Field Hardware Multiplier
340 
 
341 
module GF8Mult14(mult_i, mult_o);
342 
  // Inputs are declared here
343 
  input [7:0] mult_i;
344 
  output [7:0] mult_o;
345 
 
346 
  // Declaration of Wires And Register are here
347 
 
348 
  // Combinational Logic Body
349 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[0];
350 
  assign mult_o[1] = mult_i[5]^mult_i[1]^mult_i[0];
351 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
352 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
353 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
354 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
355 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[2];
356 
  assign mult_o[7] = mult_i[6]^mult_i[3];
357 
 
358 
 
359 
endmodule
360 
 
361 
// This is a verilog File Generated
362 
// By The C++ program That Generates
363 
// An Gallios Field Hardware Multiplier
364 
 
365 
module GF8Mult15(mult_i, mult_o);
366 
  // Inputs are declared here
367 
  input [7:0] mult_i;
368 
  output [7:0] mult_o;
369 
 
370 
  // Declaration of Wires And Register are here
371 
 
372 
  // Combinational Logic Body
373 
  assign mult_o[0] = mult_i[6]^mult_i[3];
374 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[0];
375 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
376 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
377 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
378 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
379 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
380 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[2];
381 
 
382 
 
383 
endmodule
384 
 
385 
// This is a verilog File Generated
386 
// By The C++ program That Generates
387 
// An Gallios Field Hardware Multiplier
388 
 
389 
module GF8Mult16(mult_i, mult_o);
390 
  // Inputs are declared here
391 
  input [7:0] mult_i;
392 
  output [7:0] mult_o;
393 
 
394 
  // Declaration of Wires And Register are here
395 
 
396 
  // Combinational Logic Body
397 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[2];
398 
  assign mult_o[1] = mult_i[6]^mult_i[3];
399 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
400 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
401 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
402 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
403 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
404 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
405 
 
406 
 
407 
endmodule
408 
 
409 
// This is a verilog File Generated
410 
// By The C++ program That Generates
411 
// An Gallios Field Hardware Multiplier
412 
 
413 
module GF8Mult17(mult_i, mult_o);
414 
  // Inputs are declared here
415 
  input [7:0] mult_i;
416 
  output [7:0] mult_o;
417 
 
418 
  // Declaration of Wires And Register are here
419 
 
420 
  // Combinational Logic Body
421 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
422 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[2];
423 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
424 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
425 
  assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
426 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
427 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
428 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
429 
 
430 
 
431 
endmodule
432 
 
433 
// This is a verilog File Generated
434 
// By The C++ program That Generates
435 
// An Gallios Field Hardware Multiplier
436 
 
437 
module GF8Mult18(mult_i, mult_o);
438 
  // Inputs are declared here
439 
  input [7:0] mult_i;
440 
  output [7:0] mult_o;
441 
 
442 
  // Declaration of Wires And Register are here
443 
 
444 
  // Combinational Logic Body
445 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
446 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
447 
  assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
448 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
449 
  assign mult_o[4] = mult_i[3]^mult_i[2]^mult_i[1];
450 
  assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
451 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
452 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
453 
 
454 
 
455 
endmodule
456 
 
457 
// This is a verilog File Generated
458 
// By The C++ program That Generates
459 
// An Gallios Field Hardware Multiplier
460 
 
461 
module GF8Mult19(mult_i, mult_o);
462 
  // Inputs are declared here
463 
  input [7:0] mult_i;
464 
  output [7:0] mult_o;
465 
 
466 
  // Declaration of Wires And Register are here
467 
 
468 
  // Combinational Logic Body
469 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
470 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
471 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
472 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
473 
  assign mult_o[4] = mult_i[2]^mult_i[1]^mult_i[0];
474 
  assign mult_o[5] = mult_i[3]^mult_i[2]^mult_i[1];
475 
  assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
476 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
477 
 
478 
 
479 
endmodule
480 
 
481 
// This is a verilog File Generated
482 
// By The C++ program That Generates
483 
// An Gallios Field Hardware Multiplier
484 
 
485 
module GF8Mult20(mult_i, mult_o);
486 
  // Inputs are declared here
487 
  input [7:0] mult_i;
488 
  output [7:0] mult_o;
489 
 
490 
  // Declaration of Wires And Register are here
491 
 
492 
  // Combinational Logic Body
493 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
494 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
495 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
496 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
497 
  assign mult_o[4] = mult_i[1]^mult_i[0];
498 
  assign mult_o[5] = mult_i[2]^mult_i[1]^mult_i[0];
499 
  assign mult_o[6] = mult_i[3]^mult_i[2]^mult_i[1];
500 
  assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
501 
 
502 
 
503 
endmodule
504 
 
505 
// This is a verilog File Generated
506 
// By The C++ program That Generates
507 
// An Gallios Field Hardware Multiplier
508 
 
509 
module GF8Mult21(mult_i, mult_o);
510 
  // Inputs are declared here
511 
  input [7:0] mult_i;
512 
  output [7:0] mult_o;
513 
 
514 
  // Declaration of Wires And Register are here
515 
 
516 
  // Combinational Logic Body
517 
  assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
518 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
519 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
520 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
521 
  assign mult_o[4] = mult_i[7]^mult_i[0];
522 
  assign mult_o[5] = mult_i[1]^mult_i[0];
523 
  assign mult_o[6] = mult_i[2]^mult_i[1]^mult_i[0];
524 
  assign mult_o[7] = mult_i[3]^mult_i[2]^mult_i[1];
525 
 
526 
 
527 
endmodule
528 
 
529 
// This is a verilog File Generated
530 
// By The C++ program That Generates
531 
// An Gallios Field Hardware Multiplier
532 
 
533 
module GF8Mult22(mult_i, mult_o);
534 
  // Inputs are declared here
535 
  input [7:0] mult_i;
536 
  output [7:0] mult_o;
537 
 
538 
  // Declaration of Wires And Register are here
539 
 
540 
  // Combinational Logic Body
541 
  assign mult_o[0] = mult_i[3]^mult_i[2]^mult_i[1];
542 
  assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
543 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[2];
544 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
545 
  assign mult_o[4] = mult_i[7]^mult_i[6];
546 
  assign mult_o[5] = mult_i[7]^mult_i[0];
547 
  assign mult_o[6] = mult_i[1]^mult_i[0];
548 
  assign mult_o[7] = mult_i[2]^mult_i[1]^mult_i[0];
549 
 
550 
 
551 
endmodule
552 
 
553 
// This is a verilog File Generated
554 
// By The C++ program That Generates
555 
// An Gallios Field Hardware Multiplier
556 
 
557 
module GF8Mult23(mult_i, mult_o);
558 
  // Inputs are declared here
559 
  input [7:0] mult_i;
560 
  output [7:0] mult_o;
561 
 
562 
  // Declaration of Wires And Register are here
563 
 
564 
  // Combinational Logic Body
565 
  assign mult_o[0] = mult_i[2]^mult_i[1]^mult_i[0];
566 
  assign mult_o[1] = mult_i[3]^mult_i[2]^mult_i[1];
567 
  assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[1];
568 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
569 
  assign mult_o[4] = mult_i[6]^mult_i[5];
570 
  assign mult_o[5] = mult_i[7]^mult_i[6];
571 
  assign mult_o[6] = mult_i[7]^mult_i[0];
572 
  assign mult_o[7] = mult_i[1]^mult_i[0];
573 
 
574 
 
575 
endmodule
576 
 
577 
// This is a verilog File Generated
578 
// By The C++ program That Generates
579 
// An Gallios Field Hardware Multiplier
580 
 
581 
module GF8Mult24(mult_i, mult_o);
582 
  // Inputs are declared here
583 
  input [7:0] mult_i;
584 
  output [7:0] mult_o;
585 
 
586 
  // Declaration of Wires And Register are here
587 
 
588 
  // Combinational Logic Body
589 
  assign mult_o[0] = mult_i[1]^mult_i[0];
590 
  assign mult_o[1] = mult_i[2]^mult_i[1]^mult_i[0];
591 
  assign mult_o[2] = mult_i[3]^mult_i[2]^mult_i[0];
592 
  assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[0];
593 
  assign mult_o[4] = mult_i[5]^mult_i[4];
594 
  assign mult_o[5] = mult_i[6]^mult_i[5];
595 
  assign mult_o[6] = mult_i[7]^mult_i[6];
596 
  assign mult_o[7] = mult_i[7]^mult_i[0];
597 
 
598 
 
599 
endmodule
600 
 
601 
// This is a verilog File Generated
602 
// By The C++ program That Generates
603 
// An Gallios Field Hardware Multiplier
604 
 
605 
module GF8Mult25(mult_i, mult_o);
606 
  // Inputs are declared here
607 
  input [7:0] mult_i;
608 
  output [7:0] mult_o;
609 
 
610 
  // Declaration of Wires And Register are here
611 
 
612 
  // Combinational Logic Body
613 
  assign mult_o[0] = mult_i[7]^mult_i[0];
614 
  assign mult_o[1] = mult_i[1]^mult_i[0];
615 
  assign mult_o[2] = mult_i[7]^mult_i[2]^mult_i[1];
616 
  assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[2];
617 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3];
618 
  assign mult_o[5] = mult_i[5]^mult_i[4];
619 
  assign mult_o[6] = mult_i[6]^mult_i[5];
620 
  assign mult_o[7] = mult_i[7]^mult_i[6];
621 
 
622 
 
623 
endmodule
624 
 
625 
// This is a verilog File Generated
626 
// By The C++ program That Generates
627 
// An Gallios Field Hardware Multiplier
628 
 
629 
module GF8Mult26(mult_i, mult_o);
630 
  // Inputs are declared here
631 
  input [7:0] mult_i;
632 
  output [7:0] mult_o;
633 
 
634 
  // Declaration of Wires And Register are here
635 
 
636 
  // Combinational Logic Body
637 
  assign mult_o[0] = mult_i[7]^mult_i[6];
638 
  assign mult_o[1] = mult_i[7]^mult_i[0];
639 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
640 
  assign mult_o[3] = mult_i[6]^mult_i[2]^mult_i[1];
641 
  assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[2];
642 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3];
643 
  assign mult_o[6] = mult_i[5]^mult_i[4];
644 
  assign mult_o[7] = mult_i[6]^mult_i[5];
645 
 
646 
 
647 
endmodule
648 
 
649 
// This is a verilog File Generated
650 
// By The C++ program That Generates
651 
// An Gallios Field Hardware Multiplier
652 
 
653 
module GF8Mult27(mult_i, mult_o);
654 
  // Inputs are declared here
655 
  input [7:0] mult_i;
656 
  output [7:0] mult_o;
657 
 
658 
  // Declaration of Wires And Register are here
659 
 
660 
  // Combinational Logic Body
661 
  assign mult_o[0] = mult_i[6]^mult_i[5];
662 
  assign mult_o[1] = mult_i[7]^mult_i[6];
663 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
664 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
665 
  assign mult_o[4] = mult_i[5]^mult_i[2]^mult_i[1];
666 
  assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[2];
667 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3];
668 
  assign mult_o[7] = mult_i[5]^mult_i[4];
669 
 
670 
 
671 
endmodule
672 
 
673 
// This is a verilog File Generated
674 
// By The C++ program That Generates
675 
// An Gallios Field Hardware Multiplier
676 
 
677 
module GF8Mult28(mult_i, mult_o);
678 
  // Inputs are declared here
679 
  input [7:0] mult_i;
680 
  output [7:0] mult_o;
681 
 
682 
  // Declaration of Wires And Register are here
683 
 
684 
  // Combinational Logic Body
685 
  assign mult_o[0] = mult_i[5]^mult_i[4];
686 
  assign mult_o[1] = mult_i[6]^mult_i[5];
687 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
688 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
689 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
690 
  assign mult_o[5] = mult_i[5]^mult_i[2]^mult_i[1];
691 
  assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[2];
692 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3];
693 
 
694 
 
695 
endmodule
696 
 
697 
// This is a verilog File Generated
698 
// By The C++ program That Generates
699 
// An Gallios Field Hardware Multiplier
700 
 
701 
module GF8Mult29(mult_i, mult_o);
702 
  // Inputs are declared here
703 
  input [7:0] mult_i;
704 
  output [7:0] mult_o;
705 
 
706 
  // Declaration of Wires And Register are here
707 
 
708 
  // Combinational Logic Body
709 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3];
710 
  assign mult_o[1] = mult_i[5]^mult_i[4];
711 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
712 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3];
713 
  assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[0];
714 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
715 
  assign mult_o[6] = mult_i[5]^mult_i[2]^mult_i[1];
716 
  assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[2];
717 
 
718 
 
719 
endmodule
720 
 
721 
// This is a verilog File Generated
722 
// By The C++ program That Generates
723 
// An Gallios Field Hardware Multiplier
724 
 
725 
module GF8Mult30(mult_i, mult_o);
726 
  // Inputs are declared here
727 
  input [7:0] mult_i;
728 
  output [7:0] mult_o;
729 
 
730 
  // Declaration of Wires And Register are here
731 
 
732 
  // Combinational Logic Body
733 
  assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[2];
734 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3];
735 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
736 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
737 
  assign mult_o[4] = mult_i[5]^mult_i[2];
738 
  assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[0];
739 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
740 
  assign mult_o[7] = mult_i[5]^mult_i[2]^mult_i[1];
741 
 
742 
 
743 
endmodule
744 
 
745 
// This is a verilog File Generated
746 
// By The C++ program That Generates
747 
// An Gallios Field Hardware Multiplier
748 
 
749 
module GF8Mult31(mult_i, mult_o);
750 
  // Inputs are declared here
751 
  input [7:0] mult_i;
752 
  output [7:0] mult_o;
753 
 
754 
  // Declaration of Wires And Register are here
755 
 
756 
  // Combinational Logic Body
757 
  assign mult_o[0] = mult_i[5]^mult_i[2]^mult_i[1];
758 
  assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[2];
759 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
760 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
761 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[1];
762 
  assign mult_o[5] = mult_i[5]^mult_i[2];
763 
  assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[0];
764 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
765 
 
766 
 
767 
endmodule
768 
 
769 
// This is a verilog File Generated
770 
// By The C++ program That Generates
771 
// An Gallios Field Hardware Multiplier
772 
 
773 
module GF8Mult32(mult_i, mult_o);
774 
  // Inputs are declared here
775 
  input [7:0] mult_i;
776 
  output [7:0] mult_o;
777 
 
778 
  // Declaration of Wires And Register are here
779 
 
780 
  // Combinational Logic Body
781 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
782 
  assign mult_o[1] = mult_i[5]^mult_i[2]^mult_i[1];
783 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
784 
  assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
785 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
786 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[1];
787 
  assign mult_o[6] = mult_i[5]^mult_i[2];
788 
  assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[0];
789 
 
790 
 
791 
endmodule
792 
 
793 
// This is a verilog File Generated
794 
// By The C++ program That Generates
795 
// An Gallios Field Hardware Multiplier
796 
 
797 
module GF8Mult33(mult_i, mult_o);
798 
  // Inputs are declared here
799 
  input [7:0] mult_i;
800 
  output [7:0] mult_o;
801 
 
802 
  // Declaration of Wires And Register are here
803 
 
804 
  // Combinational Logic Body
805 
  assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[0];
806 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
807 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
808 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
809 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[2];
810 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
811 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[1];
812 
  assign mult_o[7] = mult_i[5]^mult_i[2];
813 
 
814 
 
815 
endmodule
816 
 
817 
// This is a verilog File Generated
818 
// By The C++ program That Generates
819 
// An Gallios Field Hardware Multiplier
820 
 
821 
module GF8Mult34(mult_i, mult_o);
822 
  // Inputs are declared here
823 
  input [7:0] mult_i;
824 
  output [7:0] mult_o;
825 
 
826 
  // Declaration of Wires And Register are here
827 
 
828 
  // Combinational Logic Body
829 
  assign mult_o[0] = mult_i[5]^mult_i[2];
830 
  assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[0];
831 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
832 
  assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
833 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
834 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[2];
835 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
836 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[1];
837 
 
838 
 
839 
endmodule
840 
 
841 
// This is a verilog File Generated
842 
// By The C++ program That Generates
843 
// An Gallios Field Hardware Multiplier
844 
 
845 
module GF8Mult35(mult_i, mult_o);
846 
  // Inputs are declared here
847 
  input [7:0] mult_i;
848 
  output [7:0] mult_o;
849 
 
850 
  // Declaration of Wires And Register are here
851 
 
852 
  // Combinational Logic Body
853 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[1];
854 
  assign mult_o[1] = mult_i[5]^mult_i[2];
855 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
856 
  assign mult_o[3] = mult_i[5]^mult_i[2]^mult_i[0];
857 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
858 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
859 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[2];
860 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
861 
 
862 
 
863 
endmodule
864 
 
865 
// This is a verilog File Generated
866 
// By The C++ program That Generates
867 
// An Gallios Field Hardware Multiplier
868 
 
869 
module GF8Mult36(mult_i, mult_o);
870 
  // Inputs are declared here
871 
  input [7:0] mult_i;
872 
  output [7:0] mult_o;
873 
 
874 
  // Declaration of Wires And Register are here
875 
 
876 
  // Combinational Logic Body
877 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
878 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[1];
879 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
880 
  assign mult_o[3] = mult_i[4]^mult_i[1];
881 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
882 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
883 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
884 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[2];
885 
 
886 
 
887 
endmodule
888 
 
889 
// This is a verilog File Generated
890 
// By The C++ program That Generates
891 
// An Gallios Field Hardware Multiplier
892 
 
893 
module GF8Mult37(mult_i, mult_o);
894 
  // Inputs are declared here
895 
  input [7:0] mult_i;
896 
  output [7:0] mult_o;
897 
 
898 
  // Declaration of Wires And Register are here
899 
 
900 
  // Combinational Logic Body
901 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[2];
902 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
903 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
904 
  assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[0];
905 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
906 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
907 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
908 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
909 
 
910 
 
911 
endmodule
912 
 
913 
// This is a verilog File Generated
914 
// By The C++ program That Generates
915 
// An Gallios Field Hardware Multiplier
916 
 
917 
module GF8Mult38(mult_i, mult_o);
918 
  // Inputs are declared here
919 
  input [7:0] mult_i;
920 
  output [7:0] mult_o;
921 
 
922 
  // Declaration of Wires And Register are here
923 
 
924 
  // Combinational Logic Body
925 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
926 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[2];
927 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
928 
  assign mult_o[3] = mult_i[6]^mult_i[2];
929 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
930 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
931 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
932 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
933 
 
934 
 
935 
endmodule
936 
 
937 
// This is a verilog File Generated
938 
// By The C++ program That Generates
939 
// An Gallios Field Hardware Multiplier
940 
 
941 
module GF8Mult39(mult_i, mult_o);
942 
  // Inputs are declared here
943 
  input [7:0] mult_i;
944 
  output [7:0] mult_o;
945 
 
946 
  // Declaration of Wires And Register are here
947 
 
948 
  // Combinational Logic Body
949 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
950 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
951 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
952 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[1];
953 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
954 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
955 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
956 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
957 
 
958 
 
959 
endmodule
960 
 
961 
// This is a verilog File Generated
962 
// By The C++ program That Generates
963 
// An Gallios Field Hardware Multiplier
964 
 
965 
module GF8Mult40(mult_i, mult_o);
966 
  // Inputs are declared here
967 
  input [7:0] mult_i;
968 
  output [7:0] mult_o;
969 
 
970 
  // Declaration of Wires And Register are here
971 
 
972 
  // Combinational Logic Body
973 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
974 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
975 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
976 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[0];
977 
  assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
978 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
979 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
980 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
981 
 
982 
 
983 
endmodule
984 
 
985 
// This is a verilog File Generated
986 
// By The C++ program That Generates
987 
// An Gallios Field Hardware Multiplier
988 
 
989 
module GF8Mult41(mult_i, mult_o);
990 
  // Inputs are declared here
991 
  input [7:0] mult_i;
992 
  output [7:0] mult_o;
993 
 
994 
  // Declaration of Wires And Register are here
995 
 
996 
  // Combinational Logic Body
997 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
998 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
999 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1000 
  assign mult_o[3] = mult_i[5]^mult_i[3];
1001 
  assign mult_o[4] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
1002 
  assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
1003 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
1004 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1005 
 
1006 
 
1007 
endmodule
1008 
 
1009 
// This is a verilog File Generated
1010 
// By The C++ program That Generates
1011 
// An Gallios Field Hardware Multiplier
1012 
 
1013 
module GF8Mult42(mult_i, mult_o);
1014 
  // Inputs are declared here
1015 
  input [7:0] mult_i;
1016 
  output [7:0] mult_o;
1017 
 
1018 
  // Declaration of Wires And Register are here
1019 
 
1020 
  // Combinational Logic Body
1021 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1022 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
1023 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1024 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[2];
1025 
  assign mult_o[4] = mult_i[4]^mult_i[1]^mult_i[0];
1026 
  assign mult_o[5] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
1027 
  assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
1028 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
1029 
 
1030 
 
1031 
endmodule
1032 
 
1033 
// This is a verilog File Generated
1034 
// By The C++ program That Generates
1035 
// An Gallios Field Hardware Multiplier
1036 
 
1037 
module GF8Mult43(mult_i, mult_o);
1038 
  // Inputs are declared here
1039 
  input [7:0] mult_i;
1040 
  output [7:0] mult_o;
1041 
 
1042 
  // Declaration of Wires And Register are here
1043 
 
1044 
  // Combinational Logic Body
1045 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
1046 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1047 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
1048 
  assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[1];
1049 
  assign mult_o[4] = mult_i[3]^mult_i[0];
1050 
  assign mult_o[5] = mult_i[4]^mult_i[1]^mult_i[0];
1051 
  assign mult_o[6] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
1052 
  assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
1053 
 
1054 
 
1055 
endmodule
1056 
 
1057 
// This is a verilog File Generated
1058 
// By The C++ program That Generates
1059 
// An Gallios Field Hardware Multiplier
1060 
 
1061 
module GF8Mult44(mult_i, mult_o);
1062 
  // Inputs are declared here
1063 
  input [7:0] mult_i;
1064 
  output [7:0] mult_o;
1065 
 
1066 
  // Declaration of Wires And Register are here
1067 
 
1068 
  // Combinational Logic Body
1069 
  assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
1070 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
1071 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1072 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
1073 
  assign mult_o[4] = mult_i[2];
1074 
  assign mult_o[5] = mult_i[3]^mult_i[0];
1075 
  assign mult_o[6] = mult_i[4]^mult_i[1]^mult_i[0];
1076 
  assign mult_o[7] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
1077 
 
1078 
 
1079 
endmodule
1080 
 
1081 
// This is a verilog File Generated
1082 
// By The C++ program That Generates
1083 
// An Gallios Field Hardware Multiplier
1084 
 
1085 
module GF8Mult45(mult_i, mult_o);
1086 
  // Inputs are declared here
1087 
  input [7:0] mult_i;
1088 
  output [7:0] mult_o;
1089 
 
1090 
  // Declaration of Wires And Register are here
1091 
 
1092 
  // Combinational Logic Body
1093 
  assign mult_o[0] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
1094 
  assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
1095 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
1096 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[1];
1097 
  assign mult_o[4] = mult_i[7]^mult_i[1];
1098 
  assign mult_o[5] = mult_i[2];
1099 
  assign mult_o[6] = mult_i[3]^mult_i[0];
1100 
  assign mult_o[7] = mult_i[4]^mult_i[1]^mult_i[0];
1101 
 
1102 
 
1103 
endmodule
1104 
 
1105 
// This is a verilog File Generated
1106 
// By The C++ program That Generates
1107 
// An Gallios Field Hardware Multiplier
1108 
 
1109 
module GF8Mult46(mult_i, mult_o);
1110 
  // Inputs are declared here
1111 
  input [7:0] mult_i;
1112 
  output [7:0] mult_o;
1113 
 
1114 
  // Declaration of Wires And Register are here
1115 
 
1116 
  // Combinational Logic Body
1117 
  assign mult_o[0] = mult_i[4]^mult_i[1]^mult_i[0];
1118 
  assign mult_o[1] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
1119 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
1120 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
1121 
  assign mult_o[4] = mult_i[6]^mult_i[0];
1122 
  assign mult_o[5] = mult_i[7]^mult_i[1];
1123 
  assign mult_o[6] = mult_i[2];
1124 
  assign mult_o[7] = mult_i[3]^mult_i[0];
1125 
 
1126 
 
1127 
endmodule
1128 
 
1129 
// This is a verilog File Generated
1130 
// By The C++ program That Generates
1131 
// An Gallios Field Hardware Multiplier
1132 
 
1133 
module GF8Mult47(mult_i, mult_o);
1134 
  // Inputs are declared here
1135 
  input [7:0] mult_i;
1136 
  output [7:0] mult_o;
1137 
 
1138 
  // Declaration of Wires And Register are here
1139 
 
1140 
  // Combinational Logic Body
1141 
  assign mult_o[0] = mult_i[3]^mult_i[0];
1142 
  assign mult_o[1] = mult_i[4]^mult_i[1]^mult_i[0];
1143 
  assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
1144 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[2];
1145 
  assign mult_o[4] = mult_i[7]^mult_i[5];
1146 
  assign mult_o[5] = mult_i[6]^mult_i[0];
1147 
  assign mult_o[6] = mult_i[7]^mult_i[1];
1148 
  assign mult_o[7] = mult_i[2];
1149 
 
1150 
 
1151 
endmodule
1152 
 
1153 
// This is a verilog File Generated
1154 
// By The C++ program That Generates
1155 
// An Gallios Field Hardware Multiplier
1156 
 
1157 
module GF8Mult48(mult_i, mult_o);
1158 
  // Inputs are declared here
1159 
  input [7:0] mult_i;
1160 
  output [7:0] mult_o;
1161 
 
1162 
  // Declaration of Wires And Register are here
1163 
 
1164 
  // Combinational Logic Body
1165 
  assign mult_o[0] = mult_i[2];
1166 
  assign mult_o[1] = mult_i[3]^mult_i[0];
1167 
  assign mult_o[2] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1168 
  assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[1];
1169 
  assign mult_o[4] = mult_i[6]^mult_i[4];
1170 
  assign mult_o[5] = mult_i[7]^mult_i[5];
1171 
  assign mult_o[6] = mult_i[6]^mult_i[0];
1172 
  assign mult_o[7] = mult_i[7]^mult_i[1];
1173 
 
1174 
 
1175 
endmodule
1176 
 
1177 
// This is a verilog File Generated
1178 
// By The C++ program That Generates
1179 
// An Gallios Field Hardware Multiplier
1180 
 
1181 
module GF8Mult49(mult_i, mult_o);
1182 
  // Inputs are declared here
1183 
  input [7:0] mult_i;
1184 
  output [7:0] mult_o;
1185 
 
1186 
  // Declaration of Wires And Register are here
1187 
 
1188 
  // Combinational Logic Body
1189 
  assign mult_o[0] = mult_i[7]^mult_i[1];
1190 
  assign mult_o[1] = mult_i[2];
1191 
  assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
1192 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
1193 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3];
1194 
  assign mult_o[5] = mult_i[6]^mult_i[4];
1195 
  assign mult_o[6] = mult_i[7]^mult_i[5];
1196 
  assign mult_o[7] = mult_i[6]^mult_i[0];
1197 
 
1198 
 
1199 
endmodule
1200 
 
1201 
// This is a verilog File Generated
1202 
// By The C++ program That Generates
1203 
// An Gallios Field Hardware Multiplier
1204 
 
1205 
module GF8Mult50(mult_i, mult_o);
1206 
  // Inputs are declared here
1207 
  input [7:0] mult_i;
1208 
  output [7:0] mult_o;
1209 
 
1210 
  // Declaration of Wires And Register are here
1211 
 
1212 
  // Combinational Logic Body
1213 
  assign mult_o[0] = mult_i[6]^mult_i[0];
1214 
  assign mult_o[1] = mult_i[7]^mult_i[1];
1215 
  assign mult_o[2] = mult_i[6]^mult_i[2]^mult_i[0];
1216 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
1217 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
1218 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3];
1219 
  assign mult_o[6] = mult_i[6]^mult_i[4];
1220 
  assign mult_o[7] = mult_i[7]^mult_i[5];
1221 
 
1222 
 
1223 
endmodule
1224 
 
1225 
// This is a verilog File Generated
1226 
// By The C++ program That Generates
1227 
// An Gallios Field Hardware Multiplier
1228 
 
1229 
module GF8Mult51(mult_i, mult_o);
1230 
  // Inputs are declared here
1231 
  input [7:0] mult_i;
1232 
  output [7:0] mult_o;
1233 
 
1234 
  // Declaration of Wires And Register are here
1235 
 
1236 
  // Combinational Logic Body
1237 
  assign mult_o[0] = mult_i[7]^mult_i[5];
1238 
  assign mult_o[1] = mult_i[6]^mult_i[0];
1239 
  assign mult_o[2] = mult_i[5]^mult_i[1];
1240 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
1241 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
1242 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
1243 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3];
1244 
  assign mult_o[7] = mult_i[6]^mult_i[4];
1245 
 
1246 
 
1247 
endmodule
1248 
 
1249 
// This is a verilog File Generated
1250 
// By The C++ program That Generates
1251 
// An Gallios Field Hardware Multiplier
1252 
 
1253 
module GF8Mult52(mult_i, mult_o);
1254 
  // Inputs are declared here
1255 
  input [7:0] mult_i;
1256 
  output [7:0] mult_o;
1257 
 
1258 
  // Declaration of Wires And Register are here
1259 
 
1260 
  // Combinational Logic Body
1261 
  assign mult_o[0] = mult_i[6]^mult_i[4];
1262 
  assign mult_o[1] = mult_i[7]^mult_i[5];
1263 
  assign mult_o[2] = mult_i[4]^mult_i[0];
1264 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
1265 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1266 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
1267 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
1268 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3];
1269 
 
1270 
 
1271 
endmodule
1272 
 
1273 
// This is a verilog File Generated
1274 
// By The C++ program That Generates
1275 
// An Gallios Field Hardware Multiplier
1276 
 
1277 
module GF8Mult53(mult_i, mult_o);
1278 
  // Inputs are declared here
1279 
  input [7:0] mult_i;
1280 
  output [7:0] mult_o;
1281 
 
1282 
  // Declaration of Wires And Register are here
1283 
 
1284 
  // Combinational Logic Body
1285 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3];
1286 
  assign mult_o[1] = mult_i[6]^mult_i[4];
1287 
  assign mult_o[2] = mult_i[3];
1288 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
1289 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
1290 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1291 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
1292 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
1293 
 
1294 
 
1295 
endmodule
1296 
 
1297 
// This is a verilog File Generated
1298 
// By The C++ program That Generates
1299 
// An Gallios Field Hardware Multiplier
1300 
 
1301 
module GF8Mult54(mult_i, mult_o);
1302 
  // Inputs are declared here
1303 
  input [7:0] mult_i;
1304 
  output [7:0] mult_o;
1305 
 
1306 
  // Declaration of Wires And Register are here
1307 
 
1308 
  // Combinational Logic Body
1309 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
1310 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3];
1311 
  assign mult_o[2] = mult_i[7]^mult_i[2];
1312 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
1313 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1314 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
1315 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1316 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
1317 
 
1318 
 
1319 
endmodule
1320 
 
1321 
// This is a verilog File Generated
1322 
// By The C++ program That Generates
1323 
// An Gallios Field Hardware Multiplier
1324 
 
1325 
module GF8Mult55(mult_i, mult_o);
1326 
  // Inputs are declared here
1327 
  input [7:0] mult_i;
1328 
  output [7:0] mult_o;
1329 
 
1330 
  // Declaration of Wires And Register are here
1331 
 
1332 
  // Combinational Logic Body
1333 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
1334 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
1335 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[1];
1336 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
1337 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
1338 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1339 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
1340 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1341 
 
1342 
 
1343 
endmodule
1344 
 
1345 
// This is a verilog File Generated
1346 
// By The C++ program That Generates
1347 
// An Gallios Field Hardware Multiplier
1348 
 
1349 
module GF8Mult56(mult_i, mult_o);
1350 
  // Inputs are declared here
1351 
  input [7:0] mult_i;
1352 
  output [7:0] mult_o;
1353 
 
1354 
  // Declaration of Wires And Register are here
1355 
 
1356 
  // Combinational Logic Body
1357 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1358 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
1359 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[0];
1360 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1361 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1362 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
1363 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1364 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
1365 
 
1366 
 
1367 
endmodule
1368 
 
1369 
// This is a verilog File Generated
1370 
// By The C++ program That Generates
1371 
// An Gallios Field Hardware Multiplier
1372 
 
1373 
module GF8Mult57(mult_i, mult_o);
1374 
  // Inputs are declared here
1375 
  input [7:0] mult_i;
1376 
  output [7:0] mult_o;
1377 
 
1378 
  // Declaration of Wires And Register are here
1379 
 
1380 
  // Combinational Logic Body
1381 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
1382 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1383 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4];
1384 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1385 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1386 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1387 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
1388 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1389 
 
1390 
 
1391 
endmodule
1392 
 
1393 
// This is a verilog File Generated
1394 
// By The C++ program That Generates
1395 
// An Gallios Field Hardware Multiplier
1396 
 
1397 
module GF8Mult58(mult_i, mult_o);
1398 
  // Inputs are declared here
1399 
  input [7:0] mult_i;
1400 
  output [7:0] mult_o;
1401 
 
1402 
  // Declaration of Wires And Register are here
1403 
 
1404 
  // Combinational Logic Body
1405 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1406 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
1407 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
1408 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
1409 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
1410 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1411 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1412 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
1413 
 
1414 
 
1415 
endmodule
1416 
 
1417 
// This is a verilog File Generated
1418 
// By The C++ program That Generates
1419 
// An Gallios Field Hardware Multiplier
1420 
 
1421 
module GF8Mult59(mult_i, mult_o);
1422 
  // Inputs are declared here
1423 
  input [7:0] mult_i;
1424 
  output [7:0] mult_o;
1425 
 
1426 
  // Declaration of Wires And Register are here
1427 
 
1428 
  // Combinational Logic Body
1429 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
1430 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1431 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
1432 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
1433 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
1434 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
1435 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1436 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1437 
 
1438 
 
1439 
endmodule
1440 
 
1441 
// This is a verilog File Generated
1442 
// By The C++ program That Generates
1443 
// An Gallios Field Hardware Multiplier
1444 
 
1445 
module GF8Mult60(mult_i, mult_o);
1446 
  // Inputs are declared here
1447 
  input [7:0] mult_i;
1448 
  output [7:0] mult_o;
1449 
 
1450 
  // Declaration of Wires And Register are here
1451 
 
1452 
  // Combinational Logic Body
1453 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1454 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
1455 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
1456 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1457 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1458 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
1459 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
1460 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1461 
 
1462 
 
1463 
endmodule
1464 
 
1465 
// This is a verilog File Generated
1466 
// By The C++ program That Generates
1467 
// An Gallios Field Hardware Multiplier
1468 
 
1469 
module GF8Mult61(mult_i, mult_o);
1470 
  // Inputs are declared here
1471 
  input [7:0] mult_i;
1472 
  output [7:0] mult_o;
1473 
 
1474 
  // Declaration of Wires And Register are here
1475 
 
1476 
  // Combinational Logic Body
1477 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1478 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1479 
  assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1480 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1481 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
1482 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1483 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
1484 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
1485 
 
1486 
 
1487 
endmodule
1488 
 
1489 
// This is a verilog File Generated
1490 
// By The C++ program That Generates
1491 
// An Gallios Field Hardware Multiplier
1492 
 
1493 
module GF8Mult62(mult_i, mult_o);
1494 
  // Inputs are declared here
1495 
  input [7:0] mult_i;
1496 
  output [7:0] mult_o;
1497 
 
1498 
  // Declaration of Wires And Register are here
1499 
 
1500 
  // Combinational Logic Body
1501 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
1502 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1503 
  assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
1504 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
1505 
  assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
1506 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
1507 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1508 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
1509 
 
1510 
 
1511 
endmodule
1512 
 
1513 
// This is a verilog File Generated
1514 
// By The C++ program That Generates
1515 
// An Gallios Field Hardware Multiplier
1516 
 
1517 
module GF8Mult63(mult_i, mult_o);
1518 
  // Inputs are declared here
1519 
  input [7:0] mult_i;
1520 
  output [7:0] mult_o;
1521 
 
1522 
  // Declaration of Wires And Register are here
1523 
 
1524 
  // Combinational Logic Body
1525 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
1526 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
1527 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
1528 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
1529 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
1530 
  assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
1531 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
1532 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1533 
 
1534 
 
1535 
endmodule
1536 
 
1537 
// This is a verilog File Generated
1538 
// By The C++ program That Generates
1539 
// An Gallios Field Hardware Multiplier
1540 
 
1541 
module GF8Mult64(mult_i, mult_o);
1542 
  // Inputs are declared here
1543 
  input [7:0] mult_i;
1544 
  output [7:0] mult_o;
1545 
 
1546 
  // Declaration of Wires And Register are here
1547 
 
1548 
  // Combinational Logic Body
1549 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1550 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
1551 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
1552 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
1553 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
1554 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
1555 
  assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
1556 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
1557 
 
1558 
 
1559 
endmodule
1560 
 
1561 
// This is a verilog File Generated
1562 
// By The C++ program That Generates
1563 
// An Gallios Field Hardware Multiplier
1564 
 
1565 
module GF8Mult65(mult_i, mult_o);
1566 
  // Inputs are declared here
1567 
  input [7:0] mult_i;
1568 
  output [7:0] mult_o;
1569 
 
1570 
  // Declaration of Wires And Register are here
1571 
 
1572 
  // Combinational Logic Body
1573 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
1574 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
1575 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
1576 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
1577 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
1578 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
1579 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
1580 
  assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
1581 
 
1582 
 
1583 
endmodule
1584 
 
1585 
// This is a verilog File Generated
1586 
// By The C++ program That Generates
1587 
// An Gallios Field Hardware Multiplier
1588 
 
1589 
module GF8Mult66(mult_i, mult_o);
1590 
  // Inputs are declared here
1591 
  input [7:0] mult_i;
1592 
  output [7:0] mult_o;
1593 
 
1594 
  // Declaration of Wires And Register are here
1595 
 
1596 
  // Combinational Logic Body
1597 
  assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
1598 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
1599 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
1600 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
1601 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[2];
1602 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
1603 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
1604 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
1605 
 
1606 
 
1607 
endmodule
1608 
 
1609 
// This is a verilog File Generated
1610 
// By The C++ program That Generates
1611 
// An Gallios Field Hardware Multiplier
1612 
 
1613 
module GF8Mult67(mult_i, mult_o);
1614 
  // Inputs are declared here
1615 
  input [7:0] mult_i;
1616 
  output [7:0] mult_o;
1617 
 
1618 
  // Declaration of Wires And Register are here
1619 
 
1620 
  // Combinational Logic Body
1621 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
1622 
  assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
1623 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
1624 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
1625 
  assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[1];
1626 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[2];
1627 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
1628 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
1629 
 
1630 
 
1631 
endmodule
1632 
 
1633 
// This is a verilog File Generated
1634 
// By The C++ program That Generates
1635 
// An Gallios Field Hardware Multiplier
1636 
 
1637 
module GF8Mult68(mult_i, mult_o);
1638 
  // Inputs are declared here
1639 
  input [7:0] mult_i;
1640 
  output [7:0] mult_o;
1641 
 
1642 
  // Declaration of Wires And Register are here
1643 
 
1644 
  // Combinational Logic Body
1645 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
1646 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
1647 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
1648 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1649 
  assign mult_o[4] = mult_i[3]^mult_i[2]^mult_i[0];
1650 
  assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[1];
1651 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[2];
1652 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
1653 
 
1654 
 
1655 
endmodule
1656 
 
1657 
// This is a verilog File Generated
1658 
// By The C++ program That Generates
1659 
// An Gallios Field Hardware Multiplier
1660 
 
1661 
module GF8Mult69(mult_i, mult_o);
1662 
  // Inputs are declared here
1663 
  input [7:0] mult_i;
1664 
  output [7:0] mult_o;
1665 
 
1666 
  // Declaration of Wires And Register are here
1667 
 
1668 
  // Combinational Logic Body
1669 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
1670 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
1671 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1672 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1673 
  assign mult_o[4] = mult_i[7]^mult_i[2]^mult_i[1];
1674 
  assign mult_o[5] = mult_i[3]^mult_i[2]^mult_i[0];
1675 
  assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[1];
1676 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[2];
1677 
 
1678 
 
1679 
endmodule
1680 
 
1681 
// This is a verilog File Generated
1682 
// By The C++ program That Generates
1683 
// An Gallios Field Hardware Multiplier
1684 
 
1685 
module GF8Mult70(mult_i, mult_o);
1686 
  // Inputs are declared here
1687 
  input [7:0] mult_i;
1688 
  output [7:0] mult_o;
1689 
 
1690 
  // Declaration of Wires And Register are here
1691 
 
1692 
  // Combinational Logic Body
1693 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[2];
1694 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
1695 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
1696 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1697 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
1698 
  assign mult_o[5] = mult_i[7]^mult_i[2]^mult_i[1];
1699 
  assign mult_o[6] = mult_i[3]^mult_i[2]^mult_i[0];
1700 
  assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[1];
1701 
 
1702 
 
1703 
endmodule
1704 
 
1705 
// This is a verilog File Generated
1706 
// By The C++ program That Generates
1707 
// An Gallios Field Hardware Multiplier
1708 
 
1709 
module GF8Mult71(mult_i, mult_o);
1710 
  // Inputs are declared here
1711 
  input [7:0] mult_i;
1712 
  output [7:0] mult_o;
1713 
 
1714 
  // Declaration of Wires And Register are here
1715 
 
1716 
  // Combinational Logic Body
1717 
  assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[1];
1718 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[2];
1719 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
1720 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
1721 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
1722 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
1723 
  assign mult_o[6] = mult_i[7]^mult_i[2]^mult_i[1];
1724 
  assign mult_o[7] = mult_i[3]^mult_i[2]^mult_i[0];
1725 
 
1726 
 
1727 
endmodule
1728 
 
1729 
// This is a verilog File Generated
1730 
// By The C++ program That Generates
1731 
// An Gallios Field Hardware Multiplier
1732 
 
1733 
module GF8Mult72(mult_i, mult_o);
1734 
  // Inputs are declared here
1735 
  input [7:0] mult_i;
1736 
  output [7:0] mult_o;
1737 
 
1738 
  // Declaration of Wires And Register are here
1739 
 
1740 
  // Combinational Logic Body
1741 
  assign mult_o[0] = mult_i[3]^mult_i[2]^mult_i[0];
1742 
  assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[1];
1743 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
1744 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
1745 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
1746 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
1747 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
1748 
  assign mult_o[7] = mult_i[7]^mult_i[2]^mult_i[1];
1749 
 
1750 
 
1751 
endmodule
1752 
 
1753 
// This is a verilog File Generated
1754 
// By The C++ program That Generates
1755 
// An Gallios Field Hardware Multiplier
1756 
 
1757 
module GF8Mult73(mult_i, mult_o);
1758 
  // Inputs are declared here
1759 
  input [7:0] mult_i;
1760 
  output [7:0] mult_o;
1761 
 
1762 
  // Declaration of Wires And Register are here
1763 
 
1764 
  // Combinational Logic Body
1765 
  assign mult_o[0] = mult_i[7]^mult_i[2]^mult_i[1];
1766 
  assign mult_o[1] = mult_i[3]^mult_i[2]^mult_i[0];
1767 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
1768 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1769 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
1770 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
1771 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
1772 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
1773 
 
1774 
 
1775 
endmodule
1776 
 
1777 
// This is a verilog File Generated
1778 
// By The C++ program That Generates
1779 
// An Gallios Field Hardware Multiplier
1780 
 
1781 
module GF8Mult74(mult_i, mult_o);
1782 
  // Inputs are declared here
1783 
  input [7:0] mult_i;
1784 
  output [7:0] mult_o;
1785 
 
1786 
  // Declaration of Wires And Register are here
1787 
 
1788 
  // Combinational Logic Body
1789 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
1790 
  assign mult_o[1] = mult_i[7]^mult_i[2]^mult_i[1];
1791 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
1792 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1793 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
1794 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
1795 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
1796 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
1797 
 
1798 
 
1799 
endmodule
1800 
 
1801 
// This is a verilog File Generated
1802 
// By The C++ program That Generates
1803 
// An Gallios Field Hardware Multiplier
1804 
 
1805 
module GF8Mult75(mult_i, mult_o);
1806 
  // Inputs are declared here
1807 
  input [7:0] mult_i;
1808 
  output [7:0] mult_o;
1809 
 
1810 
  // Declaration of Wires And Register are here
1811 
 
1812 
  // Combinational Logic Body
1813 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
1814 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
1815 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
1816 
  assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1817 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
1818 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
1819 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
1820 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
1821 
 
1822 
 
1823 
endmodule
1824 
 
1825 
// This is a verilog File Generated
1826 
// By The C++ program That Generates
1827 
// An Gallios Field Hardware Multiplier
1828 
 
1829 
module GF8Mult76(mult_i, mult_o);
1830 
  // Inputs are declared here
1831 
  input [7:0] mult_i;
1832 
  output [7:0] mult_o;
1833 
 
1834 
  // Declaration of Wires And Register are here
1835 
 
1836 
  // Combinational Logic Body
1837 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
1838 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
1839 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
1840 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1841 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1842 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
1843 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
1844 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
1845 
 
1846 
 
1847 
endmodule
1848 
 
1849 
// This is a verilog File Generated
1850 
// By The C++ program That Generates
1851 
// An Gallios Field Hardware Multiplier
1852 
 
1853 
module GF8Mult77(mult_i, mult_o);
1854 
  // Inputs are declared here
1855 
  input [7:0] mult_i;
1856 
  output [7:0] mult_o;
1857 
 
1858 
  // Declaration of Wires And Register are here
1859 
 
1860 
  // Combinational Logic Body
1861 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
1862 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
1863 
  assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[0];
1864 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
1865 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1866 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1867 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
1868 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
1869 
 
1870 
 
1871 
endmodule
1872 
 
1873 
// This is a verilog File Generated
1874 
// By The C++ program That Generates
1875 
// An Gallios Field Hardware Multiplier
1876 
 
1877 
module GF8Mult78(mult_i, mult_o);
1878 
  // Inputs are declared here
1879 
  input [7:0] mult_i;
1880 
  output [7:0] mult_o;
1881 
 
1882 
  // Declaration of Wires And Register are here
1883 
 
1884 
  // Combinational Logic Body
1885 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
1886 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
1887 
  assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[2];
1888 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
1889 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1890 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1891 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1892 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
1893 
 
1894 
 
1895 
endmodule
1896 
 
1897 
// This is a verilog File Generated
1898 
// By The C++ program That Generates
1899 
// An Gallios Field Hardware Multiplier
1900 
 
1901 
module GF8Mult79(mult_i, mult_o);
1902 
  // Inputs are declared here
1903 
  input [7:0] mult_i;
1904 
  output [7:0] mult_o;
1905 
 
1906 
  // Declaration of Wires And Register are here
1907 
 
1908 
  // Combinational Logic Body
1909 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
1910 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
1911 
  assign mult_o[2] = mult_i[6]^mult_i[2]^mult_i[1];
1912 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[1];
1913 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1914 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1915 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1916 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1917 
 
1918 
 
1919 
endmodule
1920 
 
1921 
// This is a verilog File Generated
1922 
// By The C++ program That Generates
1923 
// An Gallios Field Hardware Multiplier
1924 
 
1925 
module GF8Mult80(mult_i, mult_o);
1926 
  // Inputs are declared here
1927 
  input [7:0] mult_i;
1928 
  output [7:0] mult_o;
1929 
 
1930 
  // Declaration of Wires And Register are here
1931 
 
1932 
  // Combinational Logic Body
1933 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1934 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
1935 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
1936 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
1937 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1938 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1939 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1940 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1941 
 
1942 
 
1943 
endmodule
1944 
 
1945 
// This is a verilog File Generated
1946 
// By The C++ program That Generates
1947 
// An Gallios Field Hardware Multiplier
1948 
 
1949 
module GF8Mult81(mult_i, mult_o);
1950 
  // Inputs are declared here
1951 
  input [7:0] mult_i;
1952 
  output [7:0] mult_o;
1953 
 
1954 
  // Declaration of Wires And Register are here
1955 
 
1956 
  // Combinational Logic Body
1957 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1958 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1959 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
1960 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
1961 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
1962 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1963 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1964 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1965 
 
1966 
 
1967 
endmodule
1968 
 
1969 
// This is a verilog File Generated
1970 
// By The C++ program That Generates
1971 
// An Gallios Field Hardware Multiplier
1972 
 
1973 
module GF8Mult82(mult_i, mult_o);
1974 
  // Inputs are declared here
1975 
  input [7:0] mult_i;
1976 
  output [7:0] mult_o;
1977 
 
1978 
  // Declaration of Wires And Register are here
1979 
 
1980 
  // Combinational Logic Body
1981 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
1982 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
1983 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3];
1984 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
1985 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1986 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
1987 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
1988 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
1989 
 
1990 
 
1991 
endmodule
1992 
 
1993 
// This is a verilog File Generated
1994 
// By The C++ program That Generates
1995 
// An Gallios Field Hardware Multiplier
1996 
 
1997 
module GF8Mult83(mult_i, mult_o);
1998 
  // Inputs are declared here
1999 
  input [7:0] mult_i;
2000 
  output [7:0] mult_o;
2001 
 
2002 
  // Declaration of Wires And Register are here
2003 
 
2004 
  // Combinational Logic Body
2005 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2006 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2007 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
2008 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2009 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2010 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2011 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
2012 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
2013 
 
2014 
 
2015 
endmodule
2016 
 
2017 
// This is a verilog File Generated
2018 
// By The C++ program That Generates
2019 
// An Gallios Field Hardware Multiplier
2020 
 
2021 
module GF8Mult84(mult_i, mult_o);
2022 
  // Inputs are declared here
2023 
  input [7:0] mult_i;
2024 
  output [7:0] mult_o;
2025 
 
2026 
  // Declaration of Wires And Register are here
2027 
 
2028 
  // Combinational Logic Body
2029 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
2030 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2031 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
2032 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
2033 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2034 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2035 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2036 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
2037 
 
2038 
 
2039 
endmodule
2040 
 
2041 
// This is a verilog File Generated
2042 
// By The C++ program That Generates
2043 
// An Gallios Field Hardware Multiplier
2044 
 
2045 
module GF8Mult85(mult_i, mult_o);
2046 
  // Inputs are declared here
2047 
  input [7:0] mult_i;
2048 
  output [7:0] mult_o;
2049 
 
2050 
  // Declaration of Wires And Register are here
2051 
 
2052 
  // Combinational Logic Body
2053 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
2054 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
2055 
  assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
2056 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
2057 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2058 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2059 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2060 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2061 
 
2062 
 
2063 
endmodule
2064 
 
2065 
// This is a verilog File Generated
2066 
// By The C++ program That Generates
2067 
// An Gallios Field Hardware Multiplier
2068 
 
2069 
module GF8Mult86(mult_i, mult_o);
2070 
  // Inputs are declared here
2071 
  input [7:0] mult_i;
2072 
  output [7:0] mult_o;
2073 
 
2074 
  // Declaration of Wires And Register are here
2075 
 
2076 
  // Combinational Logic Body
2077 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2078 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
2079 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
2080 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
2081 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2082 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2083 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2084 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2085 
 
2086 
 
2087 
endmodule
2088 
 
2089 
// This is a verilog File Generated
2090 
// By The C++ program That Generates
2091 
// An Gallios Field Hardware Multiplier
2092 
 
2093 
module GF8Mult87(mult_i, mult_o);
2094 
  // Inputs are declared here
2095 
  input [7:0] mult_i;
2096 
  output [7:0] mult_o;
2097 
 
2098 
  // Declaration of Wires And Register are here
2099 
 
2100 
  // Combinational Logic Body
2101 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2102 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2103 
  assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
2104 
  assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
2105 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
2106 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2107 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2108 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2109 
 
2110 
 
2111 
endmodule
2112 
 
2113 
// This is a verilog File Generated
2114 
// By The C++ program That Generates
2115 
// An Gallios Field Hardware Multiplier
2116 
 
2117 
module GF8Mult88(mult_i, mult_o);
2118 
  // Inputs are declared here
2119 
  input [7:0] mult_i;
2120 
  output [7:0] mult_o;
2121 
 
2122 
  // Declaration of Wires And Register are here
2123 
 
2124 
  // Combinational Logic Body
2125 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2126 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2127 
  assign mult_o[2] = mult_i[5]^mult_i[2]^mult_i[0];
2128 
  assign mult_o[3] = mult_i[4]^mult_i[2]^mult_i[0];
2129 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
2130 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
2131 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2132 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2133 
 
2134 
 
2135 
endmodule
2136 
 
2137 
// This is a verilog File Generated
2138 
// By The C++ program That Generates
2139 
// An Gallios Field Hardware Multiplier
2140 
 
2141 
module GF8Mult89(mult_i, mult_o);
2142 
  // Inputs are declared here
2143 
  input [7:0] mult_i;
2144 
  output [7:0] mult_o;
2145 
 
2146 
  // Declaration of Wires And Register are here
2147 
 
2148 
  // Combinational Logic Body
2149 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2150 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2151 
  assign mult_o[2] = mult_i[4]^mult_i[1];
2152 
  assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[1];
2153 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
2154 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
2155 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
2156 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2157 
 
2158 
 
2159 
endmodule
2160 
 
2161 
// This is a verilog File Generated
2162 
// By The C++ program That Generates
2163 
// An Gallios Field Hardware Multiplier
2164 
 
2165 
module GF8Mult90(mult_i, mult_o);
2166 
  // Inputs are declared here
2167 
  input [7:0] mult_i;
2168 
  output [7:0] mult_o;
2169 
 
2170 
  // Declaration of Wires And Register are here
2171 
 
2172 
  // Combinational Logic Body
2173 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2174 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2175 
  assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[0];
2176 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
2177 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2178 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
2179 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
2180 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
2181 
 
2182 
 
2183 
endmodule
2184 
 
2185 
// This is a verilog File Generated
2186 
// By The C++ program That Generates
2187 
// An Gallios Field Hardware Multiplier
2188 
 
2189 
module GF8Mult91(mult_i, mult_o);
2190 
  // Inputs are declared here
2191 
  input [7:0] mult_i;
2192 
  output [7:0] mult_o;
2193 
 
2194 
  // Declaration of Wires And Register are here
2195 
 
2196 
  // Combinational Logic Body
2197 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
2198 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2199 
  assign mult_o[2] = mult_i[6]^mult_i[2];
2200 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[1];
2201 
  assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
2202 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2203 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
2204 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
2205 
 
2206 
 
2207 
endmodule
2208 
 
2209 
// This is a verilog File Generated
2210 
// By The C++ program That Generates
2211 
// An Gallios Field Hardware Multiplier
2212 
 
2213 
module GF8Mult92(mult_i, mult_o);
2214 
  // Inputs are declared here
2215 
  input [7:0] mult_i;
2216 
  output [7:0] mult_o;
2217 
 
2218 
  // Declaration of Wires And Register are here
2219 
 
2220 
  // Combinational Logic Body
2221 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
2222 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
2223 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[1];
2224 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[0];
2225 
  assign mult_o[4] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2226 
  assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
2227 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2228 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
2229 
 
2230 
 
2231 
endmodule
2232 
 
2233 
// This is a verilog File Generated
2234 
// By The C++ program That Generates
2235 
// An Gallios Field Hardware Multiplier
2236 
 
2237 
module GF8Mult93(mult_i, mult_o);
2238 
  // Inputs are declared here
2239 
  input [7:0] mult_i;
2240 
  output [7:0] mult_o;
2241 
 
2242 
  // Declaration of Wires And Register are here
2243 
 
2244 
  // Combinational Logic Body
2245 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
2246 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
2247 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[0];
2248 
  assign mult_o[3] = mult_i[4]^mult_i[3];
2249 
  assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
2250 
  assign mult_o[5] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2251 
  assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
2252 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2253 
 
2254 
 
2255 
endmodule
2256 
 
2257 
// This is a verilog File Generated
2258 
// By The C++ program That Generates
2259 
// An Gallios Field Hardware Multiplier
2260 
 
2261 
module GF8Mult94(mult_i, mult_o);
2262 
  // Inputs are declared here
2263 
  input [7:0] mult_i;
2264 
  output [7:0] mult_o;
2265 
 
2266 
  // Declaration of Wires And Register are here
2267 
 
2268 
  // Combinational Logic Body
2269 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2270 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
2271 
  assign mult_o[2] = mult_i[5]^mult_i[3];
2272 
  assign mult_o[3] = mult_i[3]^mult_i[2];
2273 
  assign mult_o[4] = mult_i[6]^mult_i[2]^mult_i[0];
2274 
  assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
2275 
  assign mult_o[6] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2276 
  assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
2277 
 
2278 
 
2279 
endmodule
2280 
 
2281 
// This is a verilog File Generated
2282 
// By The C++ program That Generates
2283 
// An Gallios Field Hardware Multiplier
2284 
 
2285 
module GF8Mult95(mult_i, mult_o);
2286 
  // Inputs are declared here
2287 
  input [7:0] mult_i;
2288 
  output [7:0] mult_o;
2289 
 
2290 
  // Declaration of Wires And Register are here
2291 
 
2292 
  // Combinational Logic Body
2293 
  assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
2294 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2295 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[2];
2296 
  assign mult_o[3] = mult_i[2]^mult_i[1];
2297 
  assign mult_o[4] = mult_i[5]^mult_i[1];
2298 
  assign mult_o[5] = mult_i[6]^mult_i[2]^mult_i[0];
2299 
  assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
2300 
  assign mult_o[7] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2301 
 
2302 
 
2303 
endmodule
2304 
 
2305 
// This is a verilog File Generated
2306 
// By The C++ program That Generates
2307 
// An Gallios Field Hardware Multiplier
2308 
 
2309 
module GF8Mult96(mult_i, mult_o);
2310 
  // Inputs are declared here
2311 
  input [7:0] mult_i;
2312 
  output [7:0] mult_o;
2313 
 
2314 
  // Declaration of Wires And Register are here
2315 
 
2316 
  // Combinational Logic Body
2317 
  assign mult_o[0] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2318 
  assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
2319 
  assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[1];
2320 
  assign mult_o[3] = mult_i[7]^mult_i[1]^mult_i[0];
2321 
  assign mult_o[4] = mult_i[4]^mult_i[0];
2322 
  assign mult_o[5] = mult_i[5]^mult_i[1];
2323 
  assign mult_o[6] = mult_i[6]^mult_i[2]^mult_i[0];
2324 
  assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
2325 
 
2326 
 
2327 
endmodule
2328 
 
2329 
// This is a verilog File Generated
2330 
// By The C++ program That Generates
2331 
// An Gallios Field Hardware Multiplier
2332 
 
2333 
module GF8Mult97(mult_i, mult_o);
2334 
  // Inputs are declared here
2335 
  input [7:0] mult_i;
2336 
  output [7:0] mult_o;
2337 
 
2338 
  // Declaration of Wires And Register are here
2339 
 
2340 
  // Combinational Logic Body
2341 
  assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
2342 
  assign mult_o[1] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2343 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
2344 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[0];
2345 
  assign mult_o[4] = mult_i[3];
2346 
  assign mult_o[5] = mult_i[4]^mult_i[0];
2347 
  assign mult_o[6] = mult_i[5]^mult_i[1];
2348 
  assign mult_o[7] = mult_i[6]^mult_i[2]^mult_i[0];
2349 
 
2350 
 
2351 
endmodule
2352 
 
2353 
// This is a verilog File Generated
2354 
// By The C++ program That Generates
2355 
// An Gallios Field Hardware Multiplier
2356 
 
2357 
module GF8Mult98(mult_i, mult_o);
2358 
  // Inputs are declared here
2359 
  input [7:0] mult_i;
2360 
  output [7:0] mult_o;
2361 
 
2362 
  // Declaration of Wires And Register are here
2363 
 
2364 
  // Combinational Logic Body
2365 
  assign mult_o[0] = mult_i[6]^mult_i[2]^mult_i[0];
2366 
  assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
2367 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[1];
2368 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5];
2369 
  assign mult_o[4] = mult_i[7]^mult_i[2];
2370 
  assign mult_o[5] = mult_i[3];
2371 
  assign mult_o[6] = mult_i[4]^mult_i[0];
2372 
  assign mult_o[7] = mult_i[5]^mult_i[1];
2373 
 
2374 
 
2375 
endmodule
2376 
 
2377 
// This is a verilog File Generated
2378 
// By The C++ program That Generates
2379 
// An Gallios Field Hardware Multiplier
2380 
 
2381 
module GF8Mult99(mult_i, mult_o);
2382 
  // Inputs are declared here
2383 
  input [7:0] mult_i;
2384 
  output [7:0] mult_o;
2385 
 
2386 
  // Declaration of Wires And Register are here
2387 
 
2388 
  // Combinational Logic Body
2389 
  assign mult_o[0] = mult_i[5]^mult_i[1];
2390 
  assign mult_o[1] = mult_i[6]^mult_i[2]^mult_i[0];
2391 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
2392 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4];
2393 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[1];
2394 
  assign mult_o[5] = mult_i[7]^mult_i[2];
2395 
  assign mult_o[6] = mult_i[3];
2396 
  assign mult_o[7] = mult_i[4]^mult_i[0];
2397 
 
2398 
 
2399 
endmodule
2400 
 
2401 
// This is a verilog File Generated
2402 
// By The C++ program That Generates
2403 
// An Gallios Field Hardware Multiplier
2404 
 
2405 
module GF8Mult100(mult_i, mult_o);
2406 
  // Inputs are declared here
2407 
  input [7:0] mult_i;
2408 
  output [7:0] mult_o;
2409 
 
2410 
  // Declaration of Wires And Register are here
2411 
 
2412 
  // Combinational Logic Body
2413 
  assign mult_o[0] = mult_i[4]^mult_i[0];
2414 
  assign mult_o[1] = mult_i[5]^mult_i[1];
2415 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[2];
2416 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
2417 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[0];
2418 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[1];
2419 
  assign mult_o[6] = mult_i[7]^mult_i[2];
2420 
  assign mult_o[7] = mult_i[3];
2421 
 
2422 
 
2423 
endmodule
2424 
 
2425 
// This is a verilog File Generated
2426 
// By The C++ program That Generates
2427 
// An Gallios Field Hardware Multiplier
2428 
 
2429 
module GF8Mult101(mult_i, mult_o);
2430 
  // Inputs are declared here
2431 
  input [7:0] mult_i;
2432 
  output [7:0] mult_o;
2433 
 
2434 
  // Declaration of Wires And Register are here
2435 
 
2436 
  // Combinational Logic Body
2437 
  assign mult_o[0] = mult_i[3];
2438 
  assign mult_o[1] = mult_i[4]^mult_i[0];
2439 
  assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[1];
2440 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
2441 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4];
2442 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[0];
2443 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[1];
2444 
  assign mult_o[7] = mult_i[7]^mult_i[2];
2445 
 
2446 
 
2447 
endmodule
2448 
 
2449 
// This is a verilog File Generated
2450 
// By The C++ program That Generates
2451 
// An Gallios Field Hardware Multiplier
2452 
 
2453 
module GF8Mult102(mult_i, mult_o);
2454 
  // Inputs are declared here
2455 
  input [7:0] mult_i;
2456 
  output [7:0] mult_o;
2457 
 
2458 
  // Declaration of Wires And Register are here
2459 
 
2460 
  // Combinational Logic Body
2461 
  assign mult_o[0] = mult_i[7]^mult_i[2];
2462 
  assign mult_o[1] = mult_i[3];
2463 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
2464 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
2465 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
2466 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4];
2467 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[0];
2468 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[1];
2469 
 
2470 
 
2471 
endmodule
2472 
 
2473 
// This is a verilog File Generated
2474 
// By The C++ program That Generates
2475 
// An Gallios Field Hardware Multiplier
2476 
 
2477 
module GF8Mult103(mult_i, mult_o);
2478 
  // Inputs are declared here
2479 
  input [7:0] mult_i;
2480 
  output [7:0] mult_o;
2481 
 
2482 
  // Declaration of Wires And Register are here
2483 
 
2484 
  // Combinational Logic Body
2485 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[1];
2486 
  assign mult_o[1] = mult_i[7]^mult_i[2];
2487 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
2488 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2489 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
2490 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
2491 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4];
2492 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[0];
2493 
 
2494 
 
2495 
endmodule
2496 
 
2497 
// This is a verilog File Generated
2498 
// By The C++ program That Generates
2499 
// An Gallios Field Hardware Multiplier
2500 
 
2501 
module GF8Mult104(mult_i, mult_o);
2502 
  // Inputs are declared here
2503 
  input [7:0] mult_i;
2504 
  output [7:0] mult_o;
2505 
 
2506 
  // Declaration of Wires And Register are here
2507 
 
2508 
  // Combinational Logic Body
2509 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[0];
2510 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[1];
2511 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
2512 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
2513 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
2514 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
2515 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
2516 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4];
2517 
 
2518 
 
2519 
endmodule
2520 
 
2521 
// This is a verilog File Generated
2522 
// By The C++ program That Generates
2523 
// An Gallios Field Hardware Multiplier
2524 
 
2525 
module GF8Mult105(mult_i, mult_o);
2526 
  // Inputs are declared here
2527 
  input [7:0] mult_i;
2528 
  output [7:0] mult_o;
2529 
 
2530 
  // Declaration of Wires And Register are here
2531 
 
2532 
  // Combinational Logic Body
2533 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4];
2534 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[0];
2535 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
2536 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
2537 
  assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2538 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
2539 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
2540 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
2541 
 
2542 
 
2543 
endmodule
2544 
 
2545 
// This is a verilog File Generated
2546 
// By The C++ program That Generates
2547 
// An Gallios Field Hardware Multiplier
2548 
 
2549 
module GF8Mult106(mult_i, mult_o);
2550 
  // Inputs are declared here
2551 
  input [7:0] mult_i;
2552 
  output [7:0] mult_o;
2553 
 
2554 
  // Declaration of Wires And Register are here
2555 
 
2556 
  // Combinational Logic Body
2557 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
2558 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4];
2559 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
2560 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
2561 
  assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
2562 
  assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2563 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
2564 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
2565 
 
2566 
 
2567 
endmodule
2568 
 
2569 
// This is a verilog File Generated
2570 
// By The C++ program That Generates
2571 
// An Gallios Field Hardware Multiplier
2572 
 
2573 
module GF8Mult107(mult_i, mult_o);
2574 
  // Inputs are declared here
2575 
  input [7:0] mult_i;
2576 
  output [7:0] mult_o;
2577 
 
2578 
  // Declaration of Wires And Register are here
2579 
 
2580 
  // Combinational Logic Body
2581 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
2582 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
2583 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
2584 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
2585 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
2586 
  assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
2587 
  assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2588 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
2589 
 
2590 
 
2591 
endmodule
2592 
 
2593 
// This is a verilog File Generated
2594 
// By The C++ program That Generates
2595 
// An Gallios Field Hardware Multiplier
2596 
 
2597 
module GF8Mult108(mult_i, mult_o);
2598 
  // Inputs are declared here
2599 
  input [7:0] mult_i;
2600 
  output [7:0] mult_o;
2601 
 
2602 
  // Declaration of Wires And Register are here
2603 
 
2604 
  // Combinational Logic Body
2605 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
2606 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
2607 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
2608 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
2609 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
2610 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
2611 
  assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
2612 
  assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2613 
 
2614 
 
2615 
endmodule
2616 
 
2617 
// This is a verilog File Generated
2618 
// By The C++ program That Generates
2619 
// An Gallios Field Hardware Multiplier
2620 
 
2621 
module GF8Mult109(mult_i, mult_o);
2622 
  // Inputs are declared here
2623 
  input [7:0] mult_i;
2624 
  output [7:0] mult_o;
2625 
 
2626 
  // Declaration of Wires And Register are here
2627 
 
2628 
  // Combinational Logic Body
2629 
  assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2630 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
2631 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2632 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
2633 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
2634 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
2635 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
2636 
  assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
2637 
 
2638 
 
2639 
endmodule
2640 
 
2641 
// This is a verilog File Generated
2642 
// By The C++ program That Generates
2643 
// An Gallios Field Hardware Multiplier
2644 
 
2645 
module GF8Mult110(mult_i, mult_o);
2646 
  // Inputs are declared here
2647 
  input [7:0] mult_i;
2648 
  output [7:0] mult_o;
2649 
 
2650 
  // Declaration of Wires And Register are here
2651 
 
2652 
  // Combinational Logic Body
2653 
  assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
2654 
  assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2655 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2656 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
2657 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
2658 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
2659 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
2660 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
2661 
 
2662 
 
2663 
endmodule
2664 
 
2665 
// This is a verilog File Generated
2666 
// By The C++ program That Generates
2667 
// An Gallios Field Hardware Multiplier
2668 
 
2669 
module GF8Mult111(mult_i, mult_o);
2670 
  // Inputs are declared here
2671 
  input [7:0] mult_i;
2672 
  output [7:0] mult_o;
2673 
 
2674 
  // Declaration of Wires And Register are here
2675 
 
2676 
  // Combinational Logic Body
2677 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
2678 
  assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
2679 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2680 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2681 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
2682 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
2683 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
2684 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
2685 
 
2686 
 
2687 
endmodule
2688 
 
2689 
// This is a verilog File Generated
2690 
// By The C++ program That Generates
2691 
// An Gallios Field Hardware Multiplier
2692 
 
2693 
module GF8Mult112(mult_i, mult_o);
2694 
  // Inputs are declared here
2695 
  input [7:0] mult_i;
2696 
  output [7:0] mult_o;
2697 
 
2698 
  // Declaration of Wires And Register are here
2699 
 
2700 
  // Combinational Logic Body
2701 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
2702 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
2703 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
2704 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2705 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2706 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
2707 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
2708 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
2709 
 
2710 
 
2711 
endmodule
2712 
 
2713 
// This is a verilog File Generated
2714 
// By The C++ program That Generates
2715 
// An Gallios Field Hardware Multiplier
2716 
 
2717 
module GF8Mult113(mult_i, mult_o);
2718 
  // Inputs are declared here
2719 
  input [7:0] mult_i;
2720 
  output [7:0] mult_o;
2721 
 
2722 
  // Declaration of Wires And Register are here
2723 
 
2724 
  // Combinational Logic Body
2725 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
2726 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
2727 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2728 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2729 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2730 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2731 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
2732 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
2733 
 
2734 
 
2735 
endmodule
2736 
 
2737 
// This is a verilog File Generated
2738 
// By The C++ program That Generates
2739 
// An Gallios Field Hardware Multiplier
2740 
 
2741 
module GF8Mult114(mult_i, mult_o);
2742 
  // Inputs are declared here
2743 
  input [7:0] mult_i;
2744 
  output [7:0] mult_o;
2745 
 
2746 
  // Declaration of Wires And Register are here
2747 
 
2748 
  // Combinational Logic Body
2749 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
2750 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
2751 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2752 
  assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2753 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2754 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2755 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2756 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
2757 
 
2758 
 
2759 
endmodule
2760 
 
2761 
// This is a verilog File Generated
2762 
// By The C++ program That Generates
2763 
// An Gallios Field Hardware Multiplier
2764 
 
2765 
module GF8Mult115(mult_i, mult_o);
2766 
  // Inputs are declared here
2767 
  input [7:0] mult_i;
2768 
  output [7:0] mult_o;
2769 
 
2770 
  // Declaration of Wires And Register are here
2771 
 
2772 
  // Combinational Logic Body
2773 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
2774 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
2775 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
2776 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2777 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2778 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2779 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2780 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2781 
 
2782 
 
2783 
endmodule
2784 
 
2785 
// This is a verilog File Generated
2786 
// By The C++ program That Generates
2787 
// An Gallios Field Hardware Multiplier
2788 
 
2789 
module GF8Mult116(mult_i, mult_o);
2790 
  // Inputs are declared here
2791 
  input [7:0] mult_i;
2792 
  output [7:0] mult_o;
2793 
 
2794 
  // Declaration of Wires And Register are here
2795 
 
2796 
  // Combinational Logic Body
2797 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2798 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
2799 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
2800 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
2801 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
2802 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2803 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2804 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2805 
 
2806 
 
2807 
endmodule
2808 
 
2809 
// This is a verilog File Generated
2810 
// By The C++ program That Generates
2811 
// An Gallios Field Hardware Multiplier
2812 
 
2813 
module GF8Mult117(mult_i, mult_o);
2814 
  // Inputs are declared here
2815 
  input [7:0] mult_i;
2816 
  output [7:0] mult_o;
2817 
 
2818 
  // Declaration of Wires And Register are here
2819 
 
2820 
  // Combinational Logic Body
2821 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2822 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2823 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2824 
  assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[0];
2825 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
2826 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
2827 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2828 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2829 
 
2830 
 
2831 
endmodule
2832 
 
2833 
// This is a verilog File Generated
2834 
// By The C++ program That Generates
2835 
// An Gallios Field Hardware Multiplier
2836 
 
2837 
module GF8Mult118(mult_i, mult_o);
2838 
  // Inputs are declared here
2839 
  input [7:0] mult_i;
2840 
  output [7:0] mult_o;
2841 
 
2842 
  // Declaration of Wires And Register are here
2843 
 
2844 
  // Combinational Logic Body
2845 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2846 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2847 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
2848 
  assign mult_o[3] = mult_i[4]^mult_i[2];
2849 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
2850 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
2851 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
2852 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2853 
 
2854 
 
2855 
endmodule
2856 
 
2857 
// This is a verilog File Generated
2858 
// By The C++ program That Generates
2859 
// An Gallios Field Hardware Multiplier
2860 
 
2861 
module GF8Mult119(mult_i, mult_o);
2862 
  // Inputs are declared here
2863 
  input [7:0] mult_i;
2864 
  output [7:0] mult_o;
2865 
 
2866 
  // Declaration of Wires And Register are here
2867 
 
2868 
  // Combinational Logic Body
2869 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2870 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2871 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
2872 
  assign mult_o[3] = mult_i[3]^mult_i[1];
2873 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2874 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
2875 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
2876 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
2877 
 
2878 
 
2879 
endmodule
2880 
 
2881 
// This is a verilog File Generated
2882 
// By The C++ program That Generates
2883 
// An Gallios Field Hardware Multiplier
2884 
 
2885 
module GF8Mult120(mult_i, mult_o);
2886 
  // Inputs are declared here
2887 
  input [7:0] mult_i;
2888 
  output [7:0] mult_o;
2889 
 
2890 
  // Declaration of Wires And Register are here
2891 
 
2892 
  // Combinational Logic Body
2893 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
2894 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2895 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
2896 
  assign mult_o[3] = mult_i[7]^mult_i[2]^mult_i[0];
2897 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2898 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2899 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
2900 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
2901 
 
2902 
 
2903 
endmodule
2904 
 
2905 
// This is a verilog File Generated
2906 
// By The C++ program That Generates
2907 
// An Gallios Field Hardware Multiplier
2908 
 
2909 
module GF8Mult121(mult_i, mult_o);
2910 
  // Inputs are declared here
2911 
  input [7:0] mult_i;
2912 
  output [7:0] mult_o;
2913 
 
2914 
  // Declaration of Wires And Register are here
2915 
 
2916 
  // Combinational Logic Body
2917 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
2918 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
2919 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
2920 
  assign mult_o[3] = mult_i[6]^mult_i[1];
2921 
  assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[0];
2922 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2923 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2924 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
2925 
 
2926 
 
2927 
endmodule
2928 
 
2929 
// This is a verilog File Generated
2930 
// By The C++ program That Generates
2931 
// An Gallios Field Hardware Multiplier
2932 
 
2933 
module GF8Mult122(mult_i, mult_o);
2934 
  // Inputs are declared here
2935 
  input [7:0] mult_i;
2936 
  output [7:0] mult_o;
2937 
 
2938 
  // Declaration of Wires And Register are here
2939 
 
2940 
  // Combinational Logic Body
2941 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
2942 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
2943 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
2944 
  assign mult_o[3] = mult_i[5]^mult_i[0];
2945 
  assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[2];
2946 
  assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[0];
2947 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2948 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2949 
 
2950 
 
2951 
endmodule
2952 
 
2953 
// This is a verilog File Generated
2954 
// By The C++ program That Generates
2955 
// An Gallios Field Hardware Multiplier
2956 
 
2957 
module GF8Mult123(mult_i, mult_o);
2958 
  // Inputs are declared here
2959 
  input [7:0] mult_i;
2960 
  output [7:0] mult_o;
2961 
 
2962 
  // Declaration of Wires And Register are here
2963 
 
2964 
  // Combinational Logic Body
2965 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2966 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
2967 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
2968 
  assign mult_o[3] = mult_i[7]^mult_i[4];
2969 
  assign mult_o[4] = mult_i[6]^mult_i[2]^mult_i[1];
2970 
  assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[2];
2971 
  assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[0];
2972 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2973 
 
2974 
 
2975 
endmodule
2976 
 
2977 
// This is a verilog File Generated
2978 
// By The C++ program That Generates
2979 
// An Gallios Field Hardware Multiplier
2980 
 
2981 
module GF8Mult124(mult_i, mult_o);
2982 
  // Inputs are declared here
2983 
  input [7:0] mult_i;
2984 
  output [7:0] mult_o;
2985 
 
2986 
  // Declaration of Wires And Register are here
2987 
 
2988 
  // Combinational Logic Body
2989 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
2990 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
2991 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
2992 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3];
2993 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
2994 
  assign mult_o[5] = mult_i[6]^mult_i[2]^mult_i[1];
2995 
  assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[2];
2996 
  assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[0];
2997 
 
2998 
 
2999 
endmodule
3000 
 
3001 
// This is a verilog File Generated
3002 
// By The C++ program That Generates
3003 
// An Gallios Field Hardware Multiplier
3004 
 
3005 
module GF8Mult125(mult_i, mult_o);
3006 
  // Inputs are declared here
3007 
  input [7:0] mult_i;
3008 
  output [7:0] mult_o;
3009 
 
3010 
  // Declaration of Wires And Register are here
3011 
 
3012 
  // Combinational Logic Body
3013 
  assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[0];
3014 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
3015 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
3016 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
3017 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
3018 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
3019 
  assign mult_o[6] = mult_i[6]^mult_i[2]^mult_i[1];
3020 
  assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[2];
3021 
 
3022 
 
3023 
endmodule
3024 
 
3025 
// This is a verilog File Generated
3026 
// By The C++ program That Generates
3027 
// An Gallios Field Hardware Multiplier
3028 
 
3029 
module GF8Mult126(mult_i, mult_o);
3030 
  // Inputs are declared here
3031 
  input [7:0] mult_i;
3032 
  output [7:0] mult_o;
3033 
 
3034 
  // Declaration of Wires And Register are here
3035 
 
3036 
  // Combinational Logic Body
3037 
  assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[2];
3038 
  assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[0];
3039 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
3040 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
3041 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3];
3042 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
3043 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
3044 
  assign mult_o[7] = mult_i[6]^mult_i[2]^mult_i[1];
3045 
 
3046 
 
3047 
endmodule
3048 
 
3049 
// This is a verilog File Generated
3050 
// By The C++ program That Generates
3051 
// An Gallios Field Hardware Multiplier
3052 
 
3053 
module GF8Mult127(mult_i, mult_o);
3054 
  // Inputs are declared here
3055 
  input [7:0] mult_i;
3056 
  output [7:0] mult_o;
3057 
 
3058 
  // Declaration of Wires And Register are here
3059 
 
3060 
  // Combinational Logic Body
3061 
  assign mult_o[0] = mult_i[6]^mult_i[2]^mult_i[1];
3062 
  assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[2];
3063 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
3064 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3065 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
3066 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3];
3067 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
3068 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
3069 
 
3070 
 
3071 
endmodule
3072 
 
3073 
// This is a verilog File Generated
3074 
// By The C++ program That Generates
3075 
// An Gallios Field Hardware Multiplier
3076 
 
3077 
module GF8Mult128(mult_i, mult_o);
3078 
  // Inputs are declared here
3079 
  input [7:0] mult_i;
3080 
  output [7:0] mult_o;
3081 
 
3082 
  // Declaration of Wires And Register are here
3083 
 
3084 
  // Combinational Logic Body
3085 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
3086 
  assign mult_o[1] = mult_i[6]^mult_i[2]^mult_i[1];
3087 
  assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
3088 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
3089 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
3090 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
3091 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3];
3092 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
3093 
 
3094 
 
3095 
endmodule
3096 
 
3097 
// This is a verilog File Generated
3098 
// By The C++ program That Generates
3099 
// An Gallios Field Hardware Multiplier
3100 
 
3101 
module GF8Mult129(mult_i, mult_o);
3102 
  // Inputs are declared here
3103 
  input [7:0] mult_i;
3104 
  output [7:0] mult_o;
3105 
 
3106 
  // Declaration of Wires And Register are here
3107 
 
3108 
  // Combinational Logic Body
3109 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
3110 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
3111 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3112 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
3113 
  assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
3114 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
3115 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
3116 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3];
3117 
 
3118 
 
3119 
endmodule
3120 
 
3121 
// This is a verilog File Generated
3122 
// By The C++ program That Generates
3123 
// An Gallios Field Hardware Multiplier
3124 
 
3125 
module GF8Mult130(mult_i, mult_o);
3126 
  // Inputs are declared here
3127 
  input [7:0] mult_i;
3128 
  output [7:0] mult_o;
3129 
 
3130 
  // Declaration of Wires And Register are here
3131 
 
3132 
  // Combinational Logic Body
3133 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3];
3134 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
3135 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
3136 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
3137 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
3138 
  assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
3139 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
3140 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
3141 
 
3142 
 
3143 
endmodule
3144 
 
3145 
// This is a verilog File Generated
3146 
// By The C++ program That Generates
3147 
// An Gallios Field Hardware Multiplier
3148 
 
3149 
module GF8Mult131(mult_i, mult_o);
3150 
  // Inputs are declared here
3151 
  input [7:0] mult_i;
3152 
  output [7:0] mult_o;
3153 
 
3154 
  // Declaration of Wires And Register are here
3155 
 
3156 
  // Combinational Logic Body
3157 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
3158 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3];
3159 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
3160 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
3161 
  assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
3162 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
3163 
  assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
3164 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
3165 
 
3166 
 
3167 
endmodule
3168 
 
3169 
// This is a verilog File Generated
3170 
// By The C++ program That Generates
3171 
// An Gallios Field Hardware Multiplier
3172 
 
3173 
module GF8Mult132(mult_i, mult_o);
3174 
  // Inputs are declared here
3175 
  input [7:0] mult_i;
3176 
  output [7:0] mult_o;
3177 
 
3178 
  // Declaration of Wires And Register are here
3179 
 
3180 
  // Combinational Logic Body
3181 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
3182 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
3183 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[1];
3184 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
3185 
  assign mult_o[4] = mult_i[5]^mult_i[2]^mult_i[0];
3186 
  assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
3187 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
3188 
  assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
3189 
 
3190 
 
3191 
endmodule
3192 
 
3193 
// This is a verilog File Generated
3194 
// By The C++ program That Generates
3195 
// An Gallios Field Hardware Multiplier
3196 
 
3197 
module GF8Mult133(mult_i, mult_o);
3198 
  // Inputs are declared here
3199 
  input [7:0] mult_i;
3200 
  output [7:0] mult_o;
3201 
 
3202 
  // Declaration of Wires And Register are here
3203 
 
3204 
  // Combinational Logic Body
3205 
  assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
3206 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
3207 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
3208 
  assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
3209 
  assign mult_o[4] = mult_i[4]^mult_i[1];
3210 
  assign mult_o[5] = mult_i[5]^mult_i[2]^mult_i[0];
3211 
  assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
3212 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
3213 
 
3214 
 
3215 
endmodule
3216 
 
3217 
// This is a verilog File Generated
3218 
// By The C++ program That Generates
3219 
// An Gallios Field Hardware Multiplier
3220 
 
3221 
module GF8Mult134(mult_i, mult_o);
3222 
  // Inputs are declared here
3223 
  input [7:0] mult_i;
3224 
  output [7:0] mult_o;
3225 
 
3226 
  // Declaration of Wires And Register are here
3227 
 
3228 
  // Combinational Logic Body
3229 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
3230 
  assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
3231 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
3232 
  assign mult_o[3] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
3233 
  assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[0];
3234 
  assign mult_o[5] = mult_i[4]^mult_i[1];
3235 
  assign mult_o[6] = mult_i[5]^mult_i[2]^mult_i[0];
3236 
  assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
3237 
 
3238 
 
3239 
endmodule
3240 
 
3241 
// This is a verilog File Generated
3242 
// By The C++ program That Generates
3243 
// An Gallios Field Hardware Multiplier
3244 
 
3245 
module GF8Mult135(mult_i, mult_o);
3246 
  // Inputs are declared here
3247 
  input [7:0] mult_i;
3248 
  output [7:0] mult_o;
3249 
 
3250 
  // Declaration of Wires And Register are here
3251 
 
3252 
  // Combinational Logic Body
3253 
  assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
3254 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
3255 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
3256 
  assign mult_o[3] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
3257 
  assign mult_o[4] = mult_i[6]^mult_i[2];
3258 
  assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[0];
3259 
  assign mult_o[6] = mult_i[4]^mult_i[1];
3260 
  assign mult_o[7] = mult_i[5]^mult_i[2]^mult_i[0];
3261 
 
3262 
 
3263 
endmodule
3264 
 
3265 
// This is a verilog File Generated
3266 
// By The C++ program That Generates
3267 
// An Gallios Field Hardware Multiplier
3268 
 
3269 
module GF8Mult136(mult_i, mult_o);
3270 
  // Inputs are declared here
3271 
  input [7:0] mult_i;
3272 
  output [7:0] mult_o;
3273 
 
3274 
  // Declaration of Wires And Register are here
3275 
 
3276 
  // Combinational Logic Body
3277 
  assign mult_o[0] = mult_i[5]^mult_i[2]^mult_i[0];
3278 
  assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
3279 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
3280 
  assign mult_o[3] = mult_i[6]^mult_i[1]^mult_i[0];
3281 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[1];
3282 
  assign mult_o[5] = mult_i[6]^mult_i[2];
3283 
  assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[0];
3284 
  assign mult_o[7] = mult_i[4]^mult_i[1];
3285 
 
3286 
 
3287 
endmodule
3288 
 
3289 
// This is a verilog File Generated
3290 
// By The C++ program That Generates
3291 
// An Gallios Field Hardware Multiplier
3292 
 
3293 
module GF8Mult137(mult_i, mult_o);
3294 
  // Inputs are declared here
3295 
  input [7:0] mult_i;
3296 
  output [7:0] mult_o;
3297 
 
3298 
  // Declaration of Wires And Register are here
3299 
 
3300 
  // Combinational Logic Body
3301 
  assign mult_o[0] = mult_i[4]^mult_i[1];
3302 
  assign mult_o[1] = mult_i[5]^mult_i[2]^mult_i[0];
3303 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
3304 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[0];
3305 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[0];
3306 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[1];
3307 
  assign mult_o[6] = mult_i[6]^mult_i[2];
3308 
  assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[0];
3309 
 
3310 
 
3311 
endmodule
3312 
 
3313 
// This is a verilog File Generated
3314 
// By The C++ program That Generates
3315 
// An Gallios Field Hardware Multiplier
3316 
 
3317 
module GF8Mult138(mult_i, mult_o);
3318 
  // Inputs are declared here
3319 
  input [7:0] mult_i;
3320 
  output [7:0] mult_o;
3321 
 
3322 
  // Declaration of Wires And Register are here
3323 
 
3324 
  // Combinational Logic Body
3325 
  assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[0];
3326 
  assign mult_o[1] = mult_i[4]^mult_i[1];
3327 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
3328 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4];
3329 
  assign mult_o[4] = mult_i[5]^mult_i[3];
3330 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[0];
3331 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[1];
3332 
  assign mult_o[7] = mult_i[6]^mult_i[2];
3333 
 
3334 
 
3335 
endmodule
3336 
 
3337 
// This is a verilog File Generated
3338 
// By The C++ program That Generates
3339 
// An Gallios Field Hardware Multiplier
3340 
 
3341 
module GF8Mult139(mult_i, mult_o);
3342 
  // Inputs are declared here
3343 
  input [7:0] mult_i;
3344 
  output [7:0] mult_o;
3345 
 
3346 
  // Declaration of Wires And Register are here
3347 
 
3348 
  // Combinational Logic Body
3349 
  assign mult_o[0] = mult_i[6]^mult_i[2];
3350 
  assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[0];
3351 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
3352 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
3353 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[2];
3354 
  assign mult_o[5] = mult_i[5]^mult_i[3];
3355 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[0];
3356 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[1];
3357 
 
3358 
 
3359 
endmodule
3360 
 
3361 
// This is a verilog File Generated
3362 
// By The C++ program That Generates
3363 
// An Gallios Field Hardware Multiplier
3364 
 
3365 
module GF8Mult140(mult_i, mult_o);
3366 
  // Inputs are declared here
3367 
  input [7:0] mult_i;
3368 
  output [7:0] mult_o;
3369 
 
3370 
  // Declaration of Wires And Register are here
3371 
 
3372 
  // Combinational Logic Body
3373 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[1];
3374 
  assign mult_o[1] = mult_i[6]^mult_i[2];
3375 
  assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
3376 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
3377 
  assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[1];
3378 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[2];
3379 
  assign mult_o[6] = mult_i[5]^mult_i[3];
3380 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[0];
3381 
 
3382 
 
3383 
endmodule
3384 
 
3385 
// This is a verilog File Generated
3386 
// By The C++ program That Generates
3387 
// An Gallios Field Hardware Multiplier
3388 
 
3389 
module GF8Mult141(mult_i, mult_o);
3390 
  // Inputs are declared here
3391 
  input [7:0] mult_i;
3392 
  output [7:0] mult_o;
3393 
 
3394 
  // Declaration of Wires And Register are here
3395 
 
3396 
  // Combinational Logic Body
3397 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[0];
3398 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[1];
3399 
  assign mult_o[2] = mult_i[4]^mult_i[2]^mult_i[0];
3400 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
3401 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
3402 
  assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[1];
3403 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[2];
3404 
  assign mult_o[7] = mult_i[5]^mult_i[3];
3405 
 
3406 
 
3407 
endmodule
3408 
 
3409 
// This is a verilog File Generated
3410 
// By The C++ program That Generates
3411 
// An Gallios Field Hardware Multiplier
3412 
 
3413 
module GF8Mult142(mult_i, mult_o);
3414 
  // Inputs are declared here
3415 
  input [7:0] mult_i;
3416 
  output [7:0] mult_o;
3417 
 
3418 
  // Declaration of Wires And Register are here
3419 
 
3420 
  // Combinational Logic Body
3421 
  assign mult_o[0] = mult_i[5]^mult_i[3];
3422 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[0];
3423 
  assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[1];
3424 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
3425 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[1];
3426 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
3427 
  assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[1];
3428 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[2];
3429 
 
3430 
 
3431 
endmodule
3432 
 
3433 
// This is a verilog File Generated
3434 
// By The C++ program That Generates
3435 
// An Gallios Field Hardware Multiplier
3436 
 
3437 
module GF8Mult143(mult_i, mult_o);
3438 
  // Inputs are declared here
3439 
  input [7:0] mult_i;
3440 
  output [7:0] mult_o;
3441 
 
3442 
  // Declaration of Wires And Register are here
3443 
 
3444 
  // Combinational Logic Body
3445 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[2];
3446 
  assign mult_o[1] = mult_i[5]^mult_i[3];
3447 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
3448 
  assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
3449 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
3450 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[1];
3451 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
3452 
  assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[1];
3453 
 
3454 
 
3455 
endmodule
3456 
 
3457 
// This is a verilog File Generated
3458 
// By The C++ program That Generates
3459 
// An Gallios Field Hardware Multiplier
3460 
 
3461 
module GF8Mult144(mult_i, mult_o);
3462 
  // Inputs are declared here
3463 
  input [7:0] mult_i;
3464 
  output [7:0] mult_o;
3465 
 
3466 
  // Declaration of Wires And Register are here
3467 
 
3468 
  // Combinational Logic Body
3469 
  assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[1];
3470 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[2];
3471 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[1];
3472 
  assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
3473 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[2];
3474 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
3475 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[1];
3476 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
3477 
 
3478 
 
3479 
endmodule
3480 
 
3481 
// This is a verilog File Generated
3482 
// By The C++ program That Generates
3483 
// An Gallios Field Hardware Multiplier
3484 
 
3485 
module GF8Mult145(mult_i, mult_o);
3486 
  // Inputs are declared here
3487 
  input [7:0] mult_i;
3488 
  output [7:0] mult_o;
3489 
 
3490 
  // Declaration of Wires And Register are here
3491 
 
3492 
  // Combinational Logic Body
3493 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
3494 
  assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[1];
3495 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[0];
3496 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
3497 
  assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[1];
3498 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[2];
3499 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
3500 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[1];
3501 
 
3502 
 
3503 
endmodule
3504 
 
3505 
// This is a verilog File Generated
3506 
// By The C++ program That Generates
3507 
// An Gallios Field Hardware Multiplier
3508 
 
3509 
module GF8Mult146(mult_i, mult_o);
3510 
  // Inputs are declared here
3511 
  input [7:0] mult_i;
3512 
  output [7:0] mult_o;
3513 
 
3514 
  // Declaration of Wires And Register are here
3515 
 
3516 
  // Combinational Logic Body
3517 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[1];
3518 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
3519 
  assign mult_o[2] = mult_i[4]^mult_i[3];
3520 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
3521 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
3522 
  assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[1];
3523 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[2];
3524 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
3525 
 
3526 
 
3527 
endmodule
3528 
 
3529 
// This is a verilog File Generated
3530 
// By The C++ program That Generates
3531 
// An Gallios Field Hardware Multiplier
3532 
 
3533 
module GF8Mult147(mult_i, mult_o);
3534 
  // Inputs are declared here
3535 
  input [7:0] mult_i;
3536 
  output [7:0] mult_o;
3537 
 
3538 
  // Declaration of Wires And Register are here
3539 
 
3540 
  // Combinational Logic Body
3541 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
3542 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[1];
3543 
  assign mult_o[2] = mult_i[3]^mult_i[2];
3544 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
3545 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
3546 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
3547 
  assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[1];
3548 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[2];
3549 
 
3550 
 
3551 
endmodule
3552 
 
3553 
// This is a verilog File Generated
3554 
// By The C++ program That Generates
3555 
// An Gallios Field Hardware Multiplier
3556 
 
3557 
module GF8Mult148(mult_i, mult_o);
3558 
  // Inputs are declared here
3559 
  input [7:0] mult_i;
3560 
  output [7:0] mult_o;
3561 
 
3562 
  // Declaration of Wires And Register are here
3563 
 
3564 
  // Combinational Logic Body
3565 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[2];
3566 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
3567 
  assign mult_o[2] = mult_i[2]^mult_i[1];
3568 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3];
3569 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
3570 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
3571 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
3572 
  assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[1];
3573 
 
3574 
 
3575 
endmodule
3576 
 
3577 
// This is a verilog File Generated
3578 
// By The C++ program That Generates
3579 
// An Gallios Field Hardware Multiplier
3580 
 
3581 
module GF8Mult149(mult_i, mult_o);
3582 
  // Inputs are declared here
3583 
  input [7:0] mult_i;
3584 
  output [7:0] mult_o;
3585 
 
3586 
  // Declaration of Wires And Register are here
3587 
 
3588 
  // Combinational Logic Body
3589 
  assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[1];
3590 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[2];
3591 
  assign mult_o[2] = mult_i[7]^mult_i[1]^mult_i[0];
3592 
  assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[2];
3593 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
3594 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
3595 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
3596 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
3597 
 
3598 
 
3599 
endmodule
3600 
 
3601 
// This is a verilog File Generated
3602 
// By The C++ program That Generates
3603 
// An Gallios Field Hardware Multiplier
3604 
 
3605 
module GF8Mult150(mult_i, mult_o);
3606 
  // Inputs are declared here
3607 
  input [7:0] mult_i;
3608 
  output [7:0] mult_o;
3609 
 
3610 
  // Declaration of Wires And Register are here
3611 
 
3612 
  // Combinational Logic Body
3613 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
3614 
  assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[1];
3615 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[0];
3616 
  assign mult_o[3] = mult_i[4]^mult_i[2]^mult_i[1];
3617 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3618 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
3619 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
3620 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
3621 
 
3622 
 
3623 
endmodule
3624 
 
3625 
// This is a verilog File Generated
3626 
// By The C++ program That Generates
3627 
// An Gallios Field Hardware Multiplier
3628 
 
3629 
module GF8Mult151(mult_i, mult_o);
3630 
  // Inputs are declared here
3631 
  input [7:0] mult_i;
3632 
  output [7:0] mult_o;
3633 
 
3634 
  // Declaration of Wires And Register are here
3635 
 
3636 
  // Combinational Logic Body
3637 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
3638 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
3639 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5];
3640 
  assign mult_o[3] = mult_i[3]^mult_i[1]^mult_i[0];
3641 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
3642 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3643 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
3644 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
3645 
 
3646 
 
3647 
endmodule
3648 
 
3649 
// This is a verilog File Generated
3650 
// By The C++ program That Generates
3651 
// An Gallios Field Hardware Multiplier
3652 
 
3653 
module GF8Mult152(mult_i, mult_o);
3654 
  // Inputs are declared here
3655 
  input [7:0] mult_i;
3656 
  output [7:0] mult_o;
3657 
 
3658 
  // Declaration of Wires And Register are here
3659 
 
3660 
  // Combinational Logic Body
3661 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
3662 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
3663 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4];
3664 
  assign mult_o[3] = mult_i[2]^mult_i[0];
3665 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3666 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
3667 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3668 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
3669 
 
3670 
 
3671 
endmodule
3672 
 
3673 
// This is a verilog File Generated
3674 
// By The C++ program That Generates
3675 
// An Gallios Field Hardware Multiplier
3676 
 
3677 
module GF8Mult153(mult_i, mult_o);
3678 
  // Inputs are declared here
3679 
  input [7:0] mult_i;
3680 
  output [7:0] mult_o;
3681 
 
3682 
  // Declaration of Wires And Register are here
3683 
 
3684 
  // Combinational Logic Body
3685 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
3686 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
3687 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
3688 
  assign mult_o[3] = mult_i[1];
3689 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3690 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3691 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
3692 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3693 
 
3694 
 
3695 
endmodule
3696 
 
3697 
// This is a verilog File Generated
3698 
// By The C++ program That Generates
3699 
// An Gallios Field Hardware Multiplier
3700 
 
3701 
module GF8Mult154(mult_i, mult_o);
3702 
  // Inputs are declared here
3703 
  input [7:0] mult_i;
3704 
  output [7:0] mult_o;
3705 
 
3706 
  // Declaration of Wires And Register are here
3707 
 
3708 
  // Combinational Logic Body
3709 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3710 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
3711 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
3712 
  assign mult_o[3] = mult_i[0];
3713 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3714 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3715 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3716 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
3717 
 
3718 
 
3719 
endmodule
3720 
 
3721 
// This is a verilog File Generated
3722 
// By The C++ program That Generates
3723 
// An Gallios Field Hardware Multiplier
3724 
 
3725 
module GF8Mult155(mult_i, mult_o);
3726 
  // Inputs are declared here
3727 
  input [7:0] mult_i;
3728 
  output [7:0] mult_o;
3729 
 
3730 
  // Declaration of Wires And Register are here
3731 
 
3732 
  // Combinational Logic Body
3733 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
3734 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3735 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3736 
  assign mult_o[3] = mult_i[7];
3737 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
3738 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3739 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3740 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3741 
 
3742 
 
3743 
endmodule
3744 
 
3745 
// This is a verilog File Generated
3746 
// By The C++ program That Generates
3747 
// An Gallios Field Hardware Multiplier
3748 
 
3749 
module GF8Mult156(mult_i, mult_o);
3750 
  // Inputs are declared here
3751 
  input [7:0] mult_i;
3752 
  output [7:0] mult_o;
3753 
 
3754 
  // Declaration of Wires And Register are here
3755 
 
3756 
  // Combinational Logic Body
3757 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3758 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
3759 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3760 
  assign mult_o[3] = mult_i[6];
3761 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3762 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
3763 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3764 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3765 
 
3766 
 
3767 
endmodule
3768 
 
3769 
// This is a verilog File Generated
3770 
// By The C++ program That Generates
3771 
// An Gallios Field Hardware Multiplier
3772 
 
3773 
module GF8Mult157(mult_i, mult_o);
3774 
  // Inputs are declared here
3775 
  input [7:0] mult_i;
3776 
  output [7:0] mult_o;
3777 
 
3778 
  // Declaration of Wires And Register are here
3779 
 
3780 
  // Combinational Logic Body
3781 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3782 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3783 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
3784 
  assign mult_o[3] = mult_i[5];
3785 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3786 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3787 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
3788 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3789 
 
3790 
 
3791 
endmodule
3792 
 
3793 
// This is a verilog File Generated
3794 
// By The C++ program That Generates
3795 
// An Gallios Field Hardware Multiplier
3796 
 
3797 
module GF8Mult158(mult_i, mult_o);
3798 
  // Inputs are declared here
3799 
  input [7:0] mult_i;
3800 
  output [7:0] mult_o;
3801 
 
3802 
  // Declaration of Wires And Register are here
3803 
 
3804 
  // Combinational Logic Body
3805 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3806 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3807 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
3808 
  assign mult_o[3] = mult_i[4];
3809 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3810 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3811 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3812 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
3813 
 
3814 
 
3815 
endmodule
3816 
 
3817 
// This is a verilog File Generated
3818 
// By The C++ program That Generates
3819 
// An Gallios Field Hardware Multiplier
3820 
 
3821 
module GF8Mult159(mult_i, mult_o);
3822 
  // Inputs are declared here
3823 
  input [7:0] mult_i;
3824 
  output [7:0] mult_o;
3825 
 
3826 
  // Declaration of Wires And Register are here
3827 
 
3828 
  // Combinational Logic Body
3829 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
3830 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3831 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
3832 
  assign mult_o[3] = mult_i[7]^mult_i[3];
3833 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
3834 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3835 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3836 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3837 
 
3838 
 
3839 
endmodule
3840 
 
3841 
// This is a verilog File Generated
3842 
// By The C++ program That Generates
3843 
// An Gallios Field Hardware Multiplier
3844 
 
3845 
module GF8Mult160(mult_i, mult_o);
3846 
  // Inputs are declared here
3847 
  input [7:0] mult_i;
3848 
  output [7:0] mult_o;
3849 
 
3850 
  // Declaration of Wires And Register are here
3851 
 
3852 
  // Combinational Logic Body
3853 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3854 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
3855 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
3856 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[2];
3857 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
3858 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
3859 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3860 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3861 
 
3862 
 
3863 
endmodule
3864 
 
3865 
// This is a verilog File Generated
3866 
// By The C++ program That Generates
3867 
// An Gallios Field Hardware Multiplier
3868 
 
3869 
module GF8Mult161(mult_i, mult_o);
3870 
  // Inputs are declared here
3871 
  input [7:0] mult_i;
3872 
  output [7:0] mult_o;
3873 
 
3874 
  // Declaration of Wires And Register are here
3875 
 
3876 
  // Combinational Logic Body
3877 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3878 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
3879 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
3880 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
3881 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
3882 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
3883 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
3884 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3885 
 
3886 
 
3887 
endmodule
3888 
 
3889 
// This is a verilog File Generated
3890 
// By The C++ program That Generates
3891 
// An Gallios Field Hardware Multiplier
3892 
 
3893 
module GF8Mult162(mult_i, mult_o);
3894 
  // Inputs are declared here
3895 
  input [7:0] mult_i;
3896 
  output [7:0] mult_o;
3897 
 
3898 
  // Declaration of Wires And Register are here
3899 
 
3900 
  // Combinational Logic Body
3901 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3902 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
3903 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
3904 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
3905 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3906 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
3907 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
3908 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
3909 
 
3910 
 
3911 
endmodule
3912 
 
3913 
// This is a verilog File Generated
3914 
// By The C++ program That Generates
3915 
// An Gallios Field Hardware Multiplier
3916 
 
3917 
module GF8Mult163(mult_i, mult_o);
3918 
  // Inputs are declared here
3919 
  input [7:0] mult_i;
3920 
  output [7:0] mult_o;
3921 
 
3922 
  // Declaration of Wires And Register are here
3923 
 
3924 
  // Combinational Logic Body
3925 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
3926 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
3927 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
3928 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3];
3929 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
3930 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3931 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
3932 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
3933 
 
3934 
 
3935 
endmodule
3936 
 
3937 
// This is a verilog File Generated
3938 
// By The C++ program That Generates
3939 
// An Gallios Field Hardware Multiplier
3940 
 
3941 
module GF8Mult164(mult_i, mult_o);
3942 
  // Inputs are declared here
3943 
  input [7:0] mult_i;
3944 
  output [7:0] mult_o;
3945 
 
3946 
  // Declaration of Wires And Register are here
3947 
 
3948 
  // Combinational Logic Body
3949 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
3950 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
3951 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
3952 
  assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[2];
3953 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
3954 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
3955 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3956 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
3957 
 
3958 
 
3959 
endmodule
3960 
 
3961 
// This is a verilog File Generated
3962 
// By The C++ program That Generates
3963 
// An Gallios Field Hardware Multiplier
3964 
 
3965 
module GF8Mult165(mult_i, mult_o);
3966 
  // Inputs are declared here
3967 
  input [7:0] mult_i;
3968 
  output [7:0] mult_o;
3969 
 
3970 
  // Declaration of Wires And Register are here
3971 
 
3972 
  // Combinational Logic Body
3973 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
3974 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
3975 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
3976 
  assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
3977 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
3978 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
3979 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
3980 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3981 
 
3982 
 
3983 
endmodule
3984 
 
3985 
// This is a verilog File Generated
3986 
// By The C++ program That Generates
3987 
// An Gallios Field Hardware Multiplier
3988 
 
3989 
module GF8Mult166(mult_i, mult_o);
3990 
  // Inputs are declared here
3991 
  input [7:0] mult_i;
3992 
  output [7:0] mult_o;
3993 
 
3994 
  // Declaration of Wires And Register are here
3995 
 
3996 
  // Combinational Logic Body
3997 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
3998 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
3999 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4000 
  assign mult_o[3] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
4001 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4002 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4003 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4004 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
4005 
 
4006 
 
4007 
endmodule
4008 
 
4009 
// This is a verilog File Generated
4010 
// By The C++ program That Generates
4011 
// An Gallios Field Hardware Multiplier
4012 
 
4013 
module GF8Mult167(mult_i, mult_o);
4014 
  // Inputs are declared here
4015 
  input [7:0] mult_i;
4016 
  output [7:0] mult_o;
4017 
 
4018 
  // Declaration of Wires And Register are here
4019 
 
4020 
  // Combinational Logic Body
4021 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
4022 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
4023 
  assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4024 
  assign mult_o[3] = mult_i[5]^mult_i[1]^mult_i[0];
4025 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
4026 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4027 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4028 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4029 
 
4030 
 
4031 
endmodule
4032 
 
4033 
// This is a verilog File Generated
4034 
// By The C++ program That Generates
4035 
// An Gallios Field Hardware Multiplier
4036 
 
4037 
module GF8Mult168(mult_i, mult_o);
4038 
  // Inputs are declared here
4039 
  input [7:0] mult_i;
4040 
  output [7:0] mult_o;
4041 
 
4042 
  // Declaration of Wires And Register are here
4043 
 
4044 
  // Combinational Logic Body
4045 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4046 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
4047 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
4048 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[0];
4049 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
4050 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
4051 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4052 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4053 
 
4054 
 
4055 
endmodule
4056 
 
4057 
// This is a verilog File Generated
4058 
// By The C++ program That Generates
4059 
// An Gallios Field Hardware Multiplier
4060 
 
4061 
module GF8Mult169(mult_i, mult_o);
4062 
  // Inputs are declared here
4063 
  input [7:0] mult_i;
4064 
  output [7:0] mult_o;
4065 
 
4066 
  // Declaration of Wires And Register are here
4067 
 
4068 
  // Combinational Logic Body
4069 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4070 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4071 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
4072 
  assign mult_o[3] = mult_i[6]^mult_i[3];
4073 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4074 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
4075 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
4076 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4077 
 
4078 
 
4079 
endmodule
4080 
 
4081 
// This is a verilog File Generated
4082 
// By The C++ program That Generates
4083 
// An Gallios Field Hardware Multiplier
4084 
 
4085 
module GF8Mult170(mult_i, mult_o);
4086 
  // Inputs are declared here
4087 
  input [7:0] mult_i;
4088 
  output [7:0] mult_o;
4089 
 
4090 
  // Declaration of Wires And Register are here
4091 
 
4092 
  // Combinational Logic Body
4093 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4094 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4095 
  assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[0];
4096 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[2];
4097 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4098 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4099 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
4100 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
4101 
 
4102 
 
4103 
endmodule
4104 
 
4105 
// This is a verilog File Generated
4106 
// By The C++ program That Generates
4107 
// An Gallios Field Hardware Multiplier
4108 
 
4109 
module GF8Mult171(mult_i, mult_o);
4110 
  // Inputs are declared here
4111 
  input [7:0] mult_i;
4112 
  output [7:0] mult_o;
4113 
 
4114 
  // Declaration of Wires And Register are here
4115 
 
4116 
  // Combinational Logic Body
4117 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
4118 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4119 
  assign mult_o[2] = mult_i[4]^mult_i[2];
4120 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
4121 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4122 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4123 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4124 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
4125 
 
4126 
 
4127 
endmodule
4128 
 
4129 
// This is a verilog File Generated
4130 
// By The C++ program That Generates
4131 
// An Gallios Field Hardware Multiplier
4132 
 
4133 
module GF8Mult172(mult_i, mult_o);
4134 
  // Inputs are declared here
4135 
  input [7:0] mult_i;
4136 
  output [7:0] mult_o;
4137 
 
4138 
  // Declaration of Wires And Register are here
4139 
 
4140 
  // Combinational Logic Body
4141 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
4142 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
4143 
  assign mult_o[2] = mult_i[3]^mult_i[1];
4144 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
4145 
  assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4146 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4147 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4148 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4149 
 
4150 
 
4151 
endmodule
4152 
 
4153 
// This is a verilog File Generated
4154 
// By The C++ program That Generates
4155 
// An Gallios Field Hardware Multiplier
4156 
 
4157 
module GF8Mult173(mult_i, mult_o);
4158 
  // Inputs are declared here
4159 
  input [7:0] mult_i;
4160 
  output [7:0] mult_o;
4161 
 
4162 
  // Declaration of Wires And Register are here
4163 
 
4164 
  // Combinational Logic Body
4165 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4166 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
4167 
  assign mult_o[2] = mult_i[7]^mult_i[2]^mult_i[0];
4168 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
4169 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4170 
  assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4171 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4172 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4173 
 
4174 
 
4175 
endmodule
4176 
 
4177 
// This is a verilog File Generated
4178 
// By The C++ program That Generates
4179 
// An Gallios Field Hardware Multiplier
4180 
 
4181 
module GF8Mult174(mult_i, mult_o);
4182 
  // Inputs are declared here
4183 
  input [7:0] mult_i;
4184 
  output [7:0] mult_o;
4185 
 
4186 
  // Declaration of Wires And Register are here
4187 
 
4188 
  // Combinational Logic Body
4189 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4190 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4191 
  assign mult_o[2] = mult_i[6]^mult_i[1];
4192 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
4193 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
4194 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4195 
  assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4196 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4197 
 
4198 
 
4199 
endmodule
4200 
 
4201 
// This is a verilog File Generated
4202 
// By The C++ program That Generates
4203 
// An Gallios Field Hardware Multiplier
4204 
 
4205 
module GF8Mult175(mult_i, mult_o);
4206 
  // Inputs are declared here
4207 
  input [7:0] mult_i;
4208 
  output [7:0] mult_o;
4209 
 
4210 
  // Declaration of Wires And Register are here
4211 
 
4212 
  // Combinational Logic Body
4213 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4214 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4215 
  assign mult_o[2] = mult_i[5]^mult_i[0];
4216 
  assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
4217 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
4218 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
4219 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4220 
  assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4221 
 
4222 
 
4223 
endmodule
4224 
 
4225 
// This is a verilog File Generated
4226 
// By The C++ program That Generates
4227 
// An Gallios Field Hardware Multiplier
4228 
 
4229 
module GF8Mult176(mult_i, mult_o);
4230 
  // Inputs are declared here
4231 
  input [7:0] mult_i;
4232 
  output [7:0] mult_o;
4233 
 
4234 
  // Declaration of Wires And Register are here
4235 
 
4236 
  // Combinational Logic Body
4237 
  assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4238 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4239 
  assign mult_o[2] = mult_i[7]^mult_i[4];
4240 
  assign mult_o[3] = mult_i[3]^mult_i[2]^mult_i[1];
4241 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[1];
4242 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
4243 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
4244 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4245 
 
4246 
 
4247 
endmodule
4248 
 
4249 
// This is a verilog File Generated
4250 
// By The C++ program That Generates
4251 
// An Gallios Field Hardware Multiplier
4252 
 
4253 
module GF8Mult177(mult_i, mult_o);
4254 
  // Inputs are declared here
4255 
  input [7:0] mult_i;
4256 
  output [7:0] mult_o;
4257 
 
4258 
  // Declaration of Wires And Register are here
4259 
 
4260 
  // Combinational Logic Body
4261 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4262 
  assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4263 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3];
4264 
  assign mult_o[3] = mult_i[2]^mult_i[1]^mult_i[0];
4265 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
4266 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[1];
4267 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
4268 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
4269 
 
4270 
 
4271 
endmodule
4272 
 
4273 
// This is a verilog File Generated
4274 
// By The C++ program That Generates
4275 
// An Gallios Field Hardware Multiplier
4276 
 
4277 
module GF8Mult178(mult_i, mult_o);
4278 
  // Inputs are declared here
4279 
  input [7:0] mult_i;
4280 
  output [7:0] mult_o;
4281 
 
4282 
  // Declaration of Wires And Register are here
4283 
 
4284 
  // Combinational Logic Body
4285 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
4286 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4287 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
4288 
  assign mult_o[3] = mult_i[1]^mult_i[0];
4289 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
4290 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
4291 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[1];
4292 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
4293 
 
4294 
 
4295 
endmodule
4296 
 
4297 
// This is a verilog File Generated
4298 
// By The C++ program That Generates
4299 
// An Gallios Field Hardware Multiplier
4300 
 
4301 
module GF8Mult179(mult_i, mult_o);
4302 
  // Inputs are declared here
4303 
  input [7:0] mult_i;
4304 
  output [7:0] mult_o;
4305 
 
4306 
  // Declaration of Wires And Register are here
4307 
 
4308 
  // Combinational Logic Body
4309 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
4310 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
4311 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
4312 
  assign mult_o[3] = mult_i[7]^mult_i[0];
4313 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
4314 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
4315 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
4316 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[1];
4317 
 
4318 
 
4319 
endmodule
4320 
 
4321 
// This is a verilog File Generated
4322 
// By The C++ program That Generates
4323 
// An Gallios Field Hardware Multiplier
4324 
 
4325 
module GF8Mult180(mult_i, mult_o);
4326 
  // Inputs are declared here
4327 
  input [7:0] mult_i;
4328 
  output [7:0] mult_o;
4329 
 
4330 
  // Declaration of Wires And Register are here
4331 
 
4332 
  // Combinational Logic Body
4333 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[1];
4334 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
4335 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
4336 
  assign mult_o[3] = mult_i[7]^mult_i[6];
4337 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
4338 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
4339 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
4340 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
4341 
 
4342 
 
4343 
endmodule
4344 
 
4345 
// This is a verilog File Generated
4346 
// By The C++ program That Generates
4347 
// An Gallios Field Hardware Multiplier
4348 
 
4349 
module GF8Mult181(mult_i, mult_o);
4350 
  // Inputs are declared here
4351 
  input [7:0] mult_i;
4352 
  output [7:0] mult_o;
4353 
 
4354 
  // Declaration of Wires And Register are here
4355 
 
4356 
  // Combinational Logic Body
4357 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
4358 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[1];
4359 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
4360 
  assign mult_o[3] = mult_i[6]^mult_i[5];
4361 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
4362 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
4363 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
4364 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
4365 
 
4366 
 
4367 
endmodule
4368 
 
4369 
// This is a verilog File Generated
4370 
// By The C++ program That Generates
4371 
// An Gallios Field Hardware Multiplier
4372 
 
4373 
module GF8Mult182(mult_i, mult_o);
4374 
  // Inputs are declared here
4375 
  input [7:0] mult_i;
4376 
  output [7:0] mult_o;
4377 
 
4378 
  // Declaration of Wires And Register are here
4379 
 
4380 
  // Combinational Logic Body
4381 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
4382 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
4383 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4384 
  assign mult_o[3] = mult_i[5]^mult_i[4];
4385 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
4386 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
4387 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
4388 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
4389 
 
4390 
 
4391 
endmodule
4392 
 
4393 
// This is a verilog File Generated
4394 
// By The C++ program That Generates
4395 
// An Gallios Field Hardware Multiplier
4396 
 
4397 
module GF8Mult183(mult_i, mult_o);
4398 
  // Inputs are declared here
4399 
  input [7:0] mult_i;
4400 
  output [7:0] mult_o;
4401 
 
4402 
  // Declaration of Wires And Register are here
4403 
 
4404 
  // Combinational Logic Body
4405 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
4406 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
4407 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4408 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3];
4409 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
4410 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
4411 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
4412 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
4413 
 
4414 
 
4415 
endmodule
4416 
 
4417 
// This is a verilog File Generated
4418 
// By The C++ program That Generates
4419 
// An Gallios Field Hardware Multiplier
4420 
 
4421 
module GF8Mult184(mult_i, mult_o);
4422 
  // Inputs are declared here
4423 
  input [7:0] mult_i;
4424 
  output [7:0] mult_o;
4425 
 
4426 
  // Declaration of Wires And Register are here
4427 
 
4428 
  // Combinational Logic Body
4429 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
4430 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
4431 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4432 
  assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[2];
4433 
  assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4434 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
4435 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
4436 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
4437 
 
4438 
 
4439 
endmodule
4440 
 
4441 
// This is a verilog File Generated
4442 
// By The C++ program That Generates
4443 
// An Gallios Field Hardware Multiplier
4444 
 
4445 
module GF8Mult185(mult_i, mult_o);
4446 
  // Inputs are declared here
4447 
  input [7:0] mult_i;
4448 
  output [7:0] mult_o;
4449 
 
4450 
  // Declaration of Wires And Register are here
4451 
 
4452 
  // Combinational Logic Body
4453 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
4454 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
4455 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4456 
  assign mult_o[3] = mult_i[5]^mult_i[2]^mult_i[1];
4457 
  assign mult_o[4] = mult_i[4]^mult_i[2]^mult_i[0];
4458 
  assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4459 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
4460 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
4461 
 
4462 
 
4463 
endmodule
4464 
 
4465 
// This is a verilog File Generated
4466 
// By The C++ program That Generates
4467 
// An Gallios Field Hardware Multiplier
4468 
 
4469 
module GF8Mult186(mult_i, mult_o);
4470 
  // Inputs are declared here
4471 
  input [7:0] mult_i;
4472 
  output [7:0] mult_o;
4473 
 
4474 
  // Declaration of Wires And Register are here
4475 
 
4476 
  // Combinational Logic Body
4477 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
4478 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
4479 
  assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4480 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
4481 
  assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[1];
4482 
  assign mult_o[5] = mult_i[4]^mult_i[2]^mult_i[0];
4483 
  assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4484 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
4485 
 
4486 
 
4487 
endmodule
4488 
 
4489 
// This is a verilog File Generated
4490 
// By The C++ program That Generates
4491 
// An Gallios Field Hardware Multiplier
4492 
 
4493 
module GF8Mult187(mult_i, mult_o);
4494 
  // Inputs are declared here
4495 
  input [7:0] mult_i;
4496 
  output [7:0] mult_o;
4497 
 
4498 
  // Declaration of Wires And Register are here
4499 
 
4500 
  // Combinational Logic Body
4501 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
4502 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
4503 
  assign mult_o[2] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4504 
  assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[0];
4505 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
4506 
  assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[1];
4507 
  assign mult_o[6] = mult_i[4]^mult_i[2]^mult_i[0];
4508 
  assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4509 
 
4510 
 
4511 
endmodule
4512 
 
4513 
// This is a verilog File Generated
4514 
// By The C++ program That Generates
4515 
// An Gallios Field Hardware Multiplier
4516 
 
4517 
module GF8Mult188(mult_i, mult_o);
4518 
  // Inputs are declared here
4519 
  input [7:0] mult_i;
4520 
  output [7:0] mult_o;
4521 
 
4522 
  // Declaration of Wires And Register are here
4523 
 
4524 
  // Combinational Logic Body
4525 
  assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4526 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
4527 
  assign mult_o[2] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
4528 
  assign mult_o[3] = mult_i[5]^mult_i[2];
4529 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[1];
4530 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
4531 
  assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[1];
4532 
  assign mult_o[7] = mult_i[4]^mult_i[2]^mult_i[0];
4533 
 
4534 
 
4535 
endmodule
4536 
 
4537 
// This is a verilog File Generated
4538 
// By The C++ program That Generates
4539 
// An Gallios Field Hardware Multiplier
4540 
 
4541 
module GF8Mult189(mult_i, mult_o);
4542 
  // Inputs are declared here
4543 
  input [7:0] mult_i;
4544 
  output [7:0] mult_o;
4545 
 
4546 
  // Declaration of Wires And Register are here
4547 
 
4548 
  // Combinational Logic Body
4549 
  assign mult_o[0] = mult_i[4]^mult_i[2]^mult_i[0];
4550 
  assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4551 
  assign mult_o[2] = mult_i[6]^mult_i[1]^mult_i[0];
4552 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[1];
4553 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[0];
4554 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[1];
4555 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
4556 
  assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[1];
4557 
 
4558 
 
4559 
endmodule
4560 
 
4561 
// This is a verilog File Generated
4562 
// By The C++ program That Generates
4563 
// An Gallios Field Hardware Multiplier
4564 
 
4565 
module GF8Mult190(mult_i, mult_o);
4566 
  // Inputs are declared here
4567 
  input [7:0] mult_i;
4568 
  output [7:0] mult_o;
4569 
 
4570 
  // Declaration of Wires And Register are here
4571 
 
4572 
  // Combinational Logic Body
4573 
  assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[1];
4574 
  assign mult_o[1] = mult_i[4]^mult_i[2]^mult_i[0];
4575 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[0];
4576 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
4577 
  assign mult_o[4] = mult_i[4]^mult_i[3];
4578 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[0];
4579 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[1];
4580 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
4581 
 
4582 
 
4583 
endmodule
4584 
 
4585 
// This is a verilog File Generated
4586 
// By The C++ program That Generates
4587 
// An Gallios Field Hardware Multiplier
4588 
 
4589 
module GF8Mult191(mult_i, mult_o);
4590 
  // Inputs are declared here
4591 
  input [7:0] mult_i;
4592 
  output [7:0] mult_o;
4593 
 
4594 
  // Declaration of Wires And Register are here
4595 
 
4596 
  // Combinational Logic Body
4597 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
4598 
  assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[1];
4599 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4];
4600 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[2];
4601 
  assign mult_o[4] = mult_i[3]^mult_i[2];
4602 
  assign mult_o[5] = mult_i[4]^mult_i[3];
4603 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[0];
4604 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[1];
4605 
 
4606 
 
4607 
endmodule
4608 
 
4609 
// This is a verilog File Generated
4610 
// By The C++ program That Generates
4611 
// An Gallios Field Hardware Multiplier
4612 
 
4613 
module GF8Mult192(mult_i, mult_o);
4614 
  // Inputs are declared here
4615 
  input [7:0] mult_i;
4616 
  output [7:0] mult_o;
4617 
 
4618 
  // Declaration of Wires And Register are here
4619 
 
4620 
  // Combinational Logic Body
4621 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[1];
4622 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
4623 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
4624 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
4625 
  assign mult_o[4] = mult_i[2]^mult_i[1];
4626 
  assign mult_o[5] = mult_i[3]^mult_i[2];
4627 
  assign mult_o[6] = mult_i[4]^mult_i[3];
4628 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[0];
4629 
 
4630 
 
4631 
endmodule
4632 
 
4633 
// This is a verilog File Generated
4634 
// By The C++ program That Generates
4635 
// An Gallios Field Hardware Multiplier
4636 
 
4637 
module GF8Mult193(mult_i, mult_o);
4638 
  // Inputs are declared here
4639 
  input [7:0] mult_i;
4640 
  output [7:0] mult_o;
4641 
 
4642 
  // Declaration of Wires And Register are here
4643 
 
4644 
  // Combinational Logic Body
4645 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[0];
4646 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[1];
4647 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
4648 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
4649 
  assign mult_o[4] = mult_i[7]^mult_i[1]^mult_i[0];
4650 
  assign mult_o[5] = mult_i[2]^mult_i[1];
4651 
  assign mult_o[6] = mult_i[3]^mult_i[2];
4652 
  assign mult_o[7] = mult_i[4]^mult_i[3];
4653 
 
4654 
 
4655 
endmodule
4656 
 
4657 
// This is a verilog File Generated
4658 
// By The C++ program That Generates
4659 
// An Gallios Field Hardware Multiplier
4660 
 
4661 
module GF8Mult194(mult_i, mult_o);
4662 
  // Inputs are declared here
4663 
  input [7:0] mult_i;
4664 
  output [7:0] mult_o;
4665 
 
4666 
  // Declaration of Wires And Register are here
4667 
 
4668 
  // Combinational Logic Body
4669 
  assign mult_o[0] = mult_i[4]^mult_i[3];
4670 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[0];
4671 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
4672 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
4673 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[0];
4674 
  assign mult_o[5] = mult_i[7]^mult_i[1]^mult_i[0];
4675 
  assign mult_o[6] = mult_i[2]^mult_i[1];
4676 
  assign mult_o[7] = mult_i[3]^mult_i[2];
4677 
 
4678 
 
4679 
endmodule
4680 
 
4681 
// This is a verilog File Generated
4682 
// By The C++ program That Generates
4683 
// An Gallios Field Hardware Multiplier
4684 
 
4685 
module GF8Mult195(mult_i, mult_o);
4686 
  // Inputs are declared here
4687 
  input [7:0] mult_i;
4688 
  output [7:0] mult_o;
4689 
 
4690 
  // Declaration of Wires And Register are here
4691 
 
4692 
  // Combinational Logic Body
4693 
  assign mult_o[0] = mult_i[3]^mult_i[2];
4694 
  assign mult_o[1] = mult_i[4]^mult_i[3];
4695 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
4696 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
4697 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5];
4698 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[0];
4699 
  assign mult_o[6] = mult_i[7]^mult_i[1]^mult_i[0];
4700 
  assign mult_o[7] = mult_i[2]^mult_i[1];
4701 
 
4702 
 
4703 
endmodule
4704 
 
4705 
// This is a verilog File Generated
4706 
// By The C++ program That Generates
4707 
// An Gallios Field Hardware Multiplier
4708 
 
4709 
module GF8Mult196(mult_i, mult_o);
4710 
  // Inputs are declared here
4711 
  input [7:0] mult_i;
4712 
  output [7:0] mult_o;
4713 
 
4714 
  // Declaration of Wires And Register are here
4715 
 
4716 
  // Combinational Logic Body
4717 
  assign mult_o[0] = mult_i[2]^mult_i[1];
4718 
  assign mult_o[1] = mult_i[3]^mult_i[2];
4719 
  assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
4720 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
4721 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4];
4722 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5];
4723 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[0];
4724 
  assign mult_o[7] = mult_i[7]^mult_i[1]^mult_i[0];
4725 
 
4726 
 
4727 
endmodule
4728 
 
4729 
// This is a verilog File Generated
4730 
// By The C++ program That Generates
4731 
// An Gallios Field Hardware Multiplier
4732 
 
4733 
module GF8Mult197(mult_i, mult_o);
4734 
  // Inputs are declared here
4735 
  input [7:0] mult_i;
4736 
  output [7:0] mult_o;
4737 
 
4738 
  // Declaration of Wires And Register are here
4739 
 
4740 
  // Combinational Logic Body
4741 
  assign mult_o[0] = mult_i[7]^mult_i[1]^mult_i[0];
4742 
  assign mult_o[1] = mult_i[2]^mult_i[1];
4743 
  assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
4744 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
4745 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
4746 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4];
4747 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5];
4748 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[0];
4749 
 
4750 
 
4751 
endmodule
4752 
 
4753 
// This is a verilog File Generated
4754 
// By The C++ program That Generates
4755 
// An Gallios Field Hardware Multiplier
4756 
 
4757 
module GF8Mult198(mult_i, mult_o);
4758 
  // Inputs are declared here
4759 
  input [7:0] mult_i;
4760 
  output [7:0] mult_o;
4761 
 
4762 
  // Declaration of Wires And Register are here
4763 
 
4764 
  // Combinational Logic Body
4765 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[0];
4766 
  assign mult_o[1] = mult_i[7]^mult_i[1]^mult_i[0];
4767 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
4768 
  assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
4769 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
4770 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
4771 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4];
4772 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5];
4773 
 
4774 
 
4775 
endmodule
4776 
 
4777 
// This is a verilog File Generated
4778 
// By The C++ program That Generates
4779 
// An Gallios Field Hardware Multiplier
4780 
 
4781 
module GF8Mult199(mult_i, mult_o);
4782 
  // Inputs are declared here
4783 
  input [7:0] mult_i;
4784 
  output [7:0] mult_o;
4785 
 
4786 
  // Declaration of Wires And Register are here
4787 
 
4788 
  // Combinational Logic Body
4789 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5];
4790 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[0];
4791 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
4792 
  assign mult_o[3] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
4793 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
4794 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
4795 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
4796 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4];
4797 
 
4798 
 
4799 
endmodule
4800 
 
4801 
// This is a verilog File Generated
4802 
// By The C++ program That Generates
4803 
// An Gallios Field Hardware Multiplier
4804 
 
4805 
module GF8Mult200(mult_i, mult_o);
4806 
  // Inputs are declared here
4807 
  input [7:0] mult_i;
4808 
  output [7:0] mult_o;
4809 
 
4810 
  // Declaration of Wires And Register are here
4811 
 
4812 
  // Combinational Logic Body
4813 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4];
4814 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5];
4815 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
4816 
  assign mult_o[3] = mult_i[4]^mult_i[1]^mult_i[0];
4817 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4818 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
4819 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
4820 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
4821 
 
4822 
 
4823 
endmodule
4824 
 
4825 
// This is a verilog File Generated
4826 
// By The C++ program That Generates
4827 
// An Gallios Field Hardware Multiplier
4828 
 
4829 
module GF8Mult201(mult_i, mult_o);
4830 
  // Inputs are declared here
4831 
  input [7:0] mult_i;
4832 
  output [7:0] mult_o;
4833 
 
4834 
  // Declaration of Wires And Register are here
4835 
 
4836 
  // Combinational Logic Body
4837 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
4838 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4];
4839 
  assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3];
4840 
  assign mult_o[3] = mult_i[3]^mult_i[0];
4841 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4842 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4843 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
4844 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
4845 
 
4846 
 
4847 
endmodule
4848 
 
4849 
// This is a verilog File Generated
4850 
// By The C++ program That Generates
4851 
// An Gallios Field Hardware Multiplier
4852 
 
4853 
module GF8Mult202(mult_i, mult_o);
4854 
  // Inputs are declared here
4855 
  input [7:0] mult_i;
4856 
  output [7:0] mult_o;
4857 
 
4858 
  // Declaration of Wires And Register are here
4859 
 
4860 
  // Combinational Logic Body
4861 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
4862 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
4863 
  assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[2];
4864 
  assign mult_o[3] = mult_i[2];
4865 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
4866 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4867 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4868 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
4869 
 
4870 
 
4871 
endmodule
4872 
 
4873 
// This is a verilog File Generated
4874 
// By The C++ program That Generates
4875 
// An Gallios Field Hardware Multiplier
4876 
 
4877 
module GF8Mult203(mult_i, mult_o);
4878 
  // Inputs are declared here
4879 
  input [7:0] mult_i;
4880 
  output [7:0] mult_o;
4881 
 
4882 
  // Declaration of Wires And Register are here
4883 
 
4884 
  // Combinational Logic Body
4885 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
4886 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
4887 
  assign mult_o[2] = mult_i[4]^mult_i[2]^mult_i[1];
4888 
  assign mult_o[3] = mult_i[7]^mult_i[1];
4889 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
4890 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
4891 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4892 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4893 
 
4894 
 
4895 
endmodule
4896 
 
4897 
// This is a verilog File Generated
4898 
// By The C++ program That Generates
4899 
// An Gallios Field Hardware Multiplier
4900 
 
4901 
module GF8Mult204(mult_i, mult_o);
4902 
  // Inputs are declared here
4903 
  input [7:0] mult_i;
4904 
  output [7:0] mult_o;
4905 
 
4906 
  // Declaration of Wires And Register are here
4907 
 
4908 
  // Combinational Logic Body
4909 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4910 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
4911 
  assign mult_o[2] = mult_i[3]^mult_i[1]^mult_i[0];
4912 
  assign mult_o[3] = mult_i[6]^mult_i[0];
4913 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
4914 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
4915 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
4916 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4917 
 
4918 
 
4919 
endmodule
4920 
 
4921 
// This is a verilog File Generated
4922 
// By The C++ program That Generates
4923 
// An Gallios Field Hardware Multiplier
4924 
 
4925 
module GF8Mult205(mult_i, mult_o);
4926 
  // Inputs are declared here
4927 
  input [7:0] mult_i;
4928 
  output [7:0] mult_o;
4929 
 
4930 
  // Declaration of Wires And Register are here
4931 
 
4932 
  // Combinational Logic Body
4933 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4934 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
4935 
  assign mult_o[2] = mult_i[2]^mult_i[0];
4936 
  assign mult_o[3] = mult_i[7]^mult_i[5];
4937 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
4938 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
4939 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
4940 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
4941 
 
4942 
 
4943 
endmodule
4944 
 
4945 
// This is a verilog File Generated
4946 
// By The C++ program That Generates
4947 
// An Gallios Field Hardware Multiplier
4948 
 
4949 
module GF8Mult206(mult_i, mult_o);
4950 
  // Inputs are declared here
4951 
  input [7:0] mult_i;
4952 
  output [7:0] mult_o;
4953 
 
4954 
  // Declaration of Wires And Register are here
4955 
 
4956 
  // Combinational Logic Body
4957 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
4958 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
4959 
  assign mult_o[2] = mult_i[1];
4960 
  assign mult_o[3] = mult_i[6]^mult_i[4];
4961 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
4962 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
4963 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
4964 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
4965 
 
4966 
 
4967 
endmodule
4968 
 
4969 
// This is a verilog File Generated
4970 
// By The C++ program That Generates
4971 
// An Gallios Field Hardware Multiplier
4972 
 
4973 
module GF8Mult207(mult_i, mult_o);
4974 
  // Inputs are declared here
4975 
  input [7:0] mult_i;
4976 
  output [7:0] mult_o;
4977 
 
4978 
  // Declaration of Wires And Register are here
4979 
 
4980 
  // Combinational Logic Body
4981 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
4982 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
4983 
  assign mult_o[2] = mult_i[0];
4984 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3];
4985 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
4986 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
4987 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
4988 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
4989 
 
4990 
 
4991 
endmodule
4992 
 
4993 
// This is a verilog File Generated
4994 
// By The C++ program That Generates
4995 
// An Gallios Field Hardware Multiplier
4996 
 
4997 
module GF8Mult208(mult_i, mult_o);
4998 
  // Inputs are declared here
4999 
  input [7:0] mult_i;
5000 
  output [7:0] mult_o;
5001 
 
5002 
  // Declaration of Wires And Register are here
5003 
 
5004 
  // Combinational Logic Body
5005 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
5006 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
5007 
  assign mult_o[2] = mult_i[7];
5008 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
5009 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5010 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5011 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
5012 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
5013 
 
5014 
 
5015 
endmodule
5016 
 
5017 
// This is a verilog File Generated
5018 
// By The C++ program That Generates
5019 
// An Gallios Field Hardware Multiplier
5020 
 
5021 
module GF8Mult209(mult_i, mult_o);
5022 
  // Inputs are declared here
5023 
  input [7:0] mult_i;
5024 
  output [7:0] mult_o;
5025 
 
5026 
  // Declaration of Wires And Register are here
5027 
 
5028 
  // Combinational Logic Body
5029 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
5030 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
5031 
  assign mult_o[2] = mult_i[6];
5032 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
5033 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5034 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5035 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5036 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
5037 
 
5038 
 
5039 
endmodule
5040 
 
5041 
// This is a verilog File Generated
5042 
// By The C++ program That Generates
5043 
// An Gallios Field Hardware Multiplier
5044 
 
5045 
module GF8Mult210(mult_i, mult_o);
5046 
  // Inputs are declared here
5047 
  input [7:0] mult_i;
5048 
  output [7:0] mult_o;
5049 
 
5050 
  // Declaration of Wires And Register are here
5051 
 
5052 
  // Combinational Logic Body
5053 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
5054 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
5055 
  assign mult_o[2] = mult_i[5];
5056 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
5057 
  assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5058 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5059 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5060 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5061 
 
5062 
 
5063 
endmodule
5064 
 
5065 
// This is a verilog File Generated
5066 
// By The C++ program That Generates
5067 
// An Gallios Field Hardware Multiplier
5068 
 
5069 
module GF8Mult211(mult_i, mult_o);
5070 
  // Inputs are declared here
5071 
  input [7:0] mult_i;
5072 
  output [7:0] mult_o;
5073 
 
5074 
  // Declaration of Wires And Register are here
5075 
 
5076 
  // Combinational Logic Body
5077 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5078 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
5079 
  assign mult_o[2] = mult_i[4];
5080 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
5081 
  assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5082 
  assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5083 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5084 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5085 
 
5086 
 
5087 
endmodule
5088 
 
5089 
// This is a verilog File Generated
5090 
// By The C++ program That Generates
5091 
// An Gallios Field Hardware Multiplier
5092 
 
5093 
module GF8Mult212(mult_i, mult_o);
5094 
  // Inputs are declared here
5095 
  input [7:0] mult_i;
5096 
  output [7:0] mult_o;
5097 
 
5098 
  // Declaration of Wires And Register are here
5099 
 
5100 
  // Combinational Logic Body
5101 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5102 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5103 
  assign mult_o[2] = mult_i[7]^mult_i[3];
5104 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
5105 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
5106 
  assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5107 
  assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5108 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5109 
 
5110 
 
5111 
endmodule
5112 
 
5113 
// This is a verilog File Generated
5114 
// By The C++ program That Generates
5115 
// An Gallios Field Hardware Multiplier
5116 
 
5117 
module GF8Mult213(mult_i, mult_o);
5118 
  // Inputs are declared here
5119 
  input [7:0] mult_i;
5120 
  output [7:0] mult_o;
5121 
 
5122 
  // Declaration of Wires And Register are here
5123 
 
5124 
  // Combinational Logic Body
5125 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5126 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5127 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[2];
5128 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
5129 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
5130 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
5131 
  assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5132 
  assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5133 
 
5134 
 
5135 
endmodule
5136 
 
5137 
// This is a verilog File Generated
5138 
// By The C++ program That Generates
5139 
// An Gallios Field Hardware Multiplier
5140 
 
5141 
module GF8Mult214(mult_i, mult_o);
5142 
  // Inputs are declared here
5143 
  input [7:0] mult_i;
5144 
  output [7:0] mult_o;
5145 
 
5146 
  // Declaration of Wires And Register are here
5147 
 
5148 
  // Combinational Logic Body
5149 
  assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5150 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5151 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
5152 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
5153 
  assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[0];
5154 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
5155 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
5156 
  assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5157 
 
5158 
 
5159 
endmodule
5160 
 
5161 
// This is a verilog File Generated
5162 
// By The C++ program That Generates
5163 
// An Gallios Field Hardware Multiplier
5164 
 
5165 
module GF8Mult215(mult_i, mult_o);
5166 
  // Inputs are declared here
5167 
  input [7:0] mult_i;
5168 
  output [7:0] mult_o;
5169 
 
5170 
  // Declaration of Wires And Register are here
5171 
 
5172 
  // Combinational Logic Body
5173 
  assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5174 
  assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5175 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
5176 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
5177 
  assign mult_o[4] = mult_i[4]^mult_i[2];
5178 
  assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[0];
5179 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
5180 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
5181 
 
5182 
 
5183 
endmodule
5184 
 
5185 
// This is a verilog File Generated
5186 
// By The C++ program That Generates
5187 
// An Gallios Field Hardware Multiplier
5188 
 
5189 
module GF8Mult216(mult_i, mult_o);
5190 
  // Inputs are declared here
5191 
  input [7:0] mult_i;
5192 
  output [7:0] mult_o;
5193 
 
5194 
  // Declaration of Wires And Register are here
5195 
 
5196 
  // Combinational Logic Body
5197 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
5198 
  assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5199 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3];
5200 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
5201 
  assign mult_o[4] = mult_i[3]^mult_i[1];
5202 
  assign mult_o[5] = mult_i[4]^mult_i[2];
5203 
  assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[0];
5204 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
5205 
 
5206 
 
5207 
endmodule
5208 
 
5209 
// This is a verilog File Generated
5210 
// By The C++ program That Generates
5211 
// An Gallios Field Hardware Multiplier
5212 
 
5213 
module GF8Mult217(mult_i, mult_o);
5214 
  // Inputs are declared here
5215 
  input [7:0] mult_i;
5216 
  output [7:0] mult_o;
5217 
 
5218 
  // Declaration of Wires And Register are here
5219 
 
5220 
  // Combinational Logic Body
5221 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
5222 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
5223 
  assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[2];
5224 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
5225 
  assign mult_o[4] = mult_i[7]^mult_i[2]^mult_i[0];
5226 
  assign mult_o[5] = mult_i[3]^mult_i[1];
5227 
  assign mult_o[6] = mult_i[4]^mult_i[2];
5228 
  assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[0];
5229 
 
5230 
 
5231 
endmodule
5232 
 
5233 
// This is a verilog File Generated
5234 
// By The C++ program That Generates
5235 
// An Gallios Field Hardware Multiplier
5236 
 
5237 
module GF8Mult218(mult_i, mult_o);
5238 
  // Inputs are declared here
5239 
  input [7:0] mult_i;
5240 
  output [7:0] mult_o;
5241 
 
5242 
  // Declaration of Wires And Register are here
5243 
 
5244 
  // Combinational Logic Body
5245 
  assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[0];
5246 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
5247 
  assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
5248 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
5249 
  assign mult_o[4] = mult_i[6]^mult_i[1];
5250 
  assign mult_o[5] = mult_i[7]^mult_i[2]^mult_i[0];
5251 
  assign mult_o[6] = mult_i[3]^mult_i[1];
5252 
  assign mult_o[7] = mult_i[4]^mult_i[2];
5253 
 
5254 
 
5255 
endmodule
5256 
 
5257 
// This is a verilog File Generated
5258 
// By The C++ program That Generates
5259 
// An Gallios Field Hardware Multiplier
5260 
 
5261 
module GF8Mult219(mult_i, mult_o);
5262 
  // Inputs are declared here
5263 
  input [7:0] mult_i;
5264 
  output [7:0] mult_o;
5265 
 
5266 
  // Declaration of Wires And Register are here
5267 
 
5268 
  // Combinational Logic Body
5269 
  assign mult_o[0] = mult_i[4]^mult_i[2];
5270 
  assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[0];
5271 
  assign mult_o[2] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
5272 
  assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
5273 
  assign mult_o[4] = mult_i[5]^mult_i[0];
5274 
  assign mult_o[5] = mult_i[6]^mult_i[1];
5275 
  assign mult_o[6] = mult_i[7]^mult_i[2]^mult_i[0];
5276 
  assign mult_o[7] = mult_i[3]^mult_i[1];
5277 
 
5278 
 
5279 
endmodule
5280 
 
5281 
// This is a verilog File Generated
5282 
// By The C++ program That Generates
5283 
// An Gallios Field Hardware Multiplier
5284 
 
5285 
module GF8Mult220(mult_i, mult_o);
5286 
  // Inputs are declared here
5287 
  input [7:0] mult_i;
5288 
  output [7:0] mult_o;
5289 
 
5290 
  // Declaration of Wires And Register are here
5291 
 
5292 
  // Combinational Logic Body
5293 
  assign mult_o[0] = mult_i[3]^mult_i[1];
5294 
  assign mult_o[1] = mult_i[4]^mult_i[2];
5295 
  assign mult_o[2] = mult_i[5]^mult_i[1]^mult_i[0];
5296 
  assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
5297 
  assign mult_o[4] = mult_i[7]^mult_i[4];
5298 
  assign mult_o[5] = mult_i[5]^mult_i[0];
5299 
  assign mult_o[6] = mult_i[6]^mult_i[1];
5300 
  assign mult_o[7] = mult_i[7]^mult_i[2]^mult_i[0];
5301 
 
5302 
 
5303 
endmodule
5304 
 
5305 
// This is a verilog File Generated
5306 
// By The C++ program That Generates
5307 
// An Gallios Field Hardware Multiplier
5308 
 
5309 
module GF8Mult221(mult_i, mult_o);
5310 
  // Inputs are declared here
5311 
  input [7:0] mult_i;
5312 
  output [7:0] mult_o;
5313 
 
5314 
  // Declaration of Wires And Register are here
5315 
 
5316 
  // Combinational Logic Body
5317 
  assign mult_o[0] = mult_i[7]^mult_i[2]^mult_i[0];
5318 
  assign mult_o[1] = mult_i[3]^mult_i[1];
5319 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[0];
5320 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
5321 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3];
5322 
  assign mult_o[5] = mult_i[7]^mult_i[4];
5323 
  assign mult_o[6] = mult_i[5]^mult_i[0];
5324 
  assign mult_o[7] = mult_i[6]^mult_i[1];
5325 
 
5326 
 
5327 
endmodule
5328 
 
5329 
// This is a verilog File Generated
5330 
// By The C++ program That Generates
5331 
// An Gallios Field Hardware Multiplier
5332 
 
5333 
module GF8Mult222(mult_i, mult_o);
5334 
  // Inputs are declared here
5335 
  input [7:0] mult_i;
5336 
  output [7:0] mult_o;
5337 
 
5338 
  // Declaration of Wires And Register are here
5339 
 
5340 
  // Combinational Logic Body
5341 
  assign mult_o[0] = mult_i[6]^mult_i[1];
5342 
  assign mult_o[1] = mult_i[7]^mult_i[2]^mult_i[0];
5343 
  assign mult_o[2] = mult_i[6]^mult_i[3];
5344 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
5345 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
5346 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3];
5347 
  assign mult_o[6] = mult_i[7]^mult_i[4];
5348 
  assign mult_o[7] = mult_i[5]^mult_i[0];
5349 
 
5350 
 
5351 
endmodule
5352 
 
5353 
// This is a verilog File Generated
5354 
// By The C++ program That Generates
5355 
// An Gallios Field Hardware Multiplier
5356 
 
5357 
module GF8Mult223(mult_i, mult_o);
5358 
  // Inputs are declared here
5359 
  input [7:0] mult_i;
5360 
  output [7:0] mult_o;
5361 
 
5362 
  // Declaration of Wires And Register are here
5363 
 
5364 
  // Combinational Logic Body
5365 
  assign mult_o[0] = mult_i[5]^mult_i[0];
5366 
  assign mult_o[1] = mult_i[6]^mult_i[1];
5367 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[2];
5368 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
5369 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
5370 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
5371 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3];
5372 
  assign mult_o[7] = mult_i[7]^mult_i[4];
5373 
 
5374 
 
5375 
endmodule
5376 
 
5377 
// This is a verilog File Generated
5378 
// By The C++ program That Generates
5379 
// An Gallios Field Hardware Multiplier
5380 
 
5381 
module GF8Mult224(mult_i, mult_o);
5382 
  // Inputs are declared here
5383 
  input [7:0] mult_i;
5384 
  output [7:0] mult_o;
5385 
 
5386 
  // Declaration of Wires And Register are here
5387 
 
5388 
  // Combinational Logic Body
5389 
  assign mult_o[0] = mult_i[7]^mult_i[4];
5390 
  assign mult_o[1] = mult_i[5]^mult_i[0];
5391 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
5392 
  assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[2];
5393 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
5394 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
5395 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
5396 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3];
5397 
 
5398 
 
5399 
endmodule
5400 
 
5401 
// This is a verilog File Generated
5402 
// By The C++ program That Generates
5403 
// An Gallios Field Hardware Multiplier
5404 
 
5405 
module GF8Mult225(mult_i, mult_o);
5406 
  // Inputs are declared here
5407 
  input [7:0] mult_i;
5408 
  output [7:0] mult_o;
5409 
 
5410 
  // Declaration of Wires And Register are here
5411 
 
5412 
  // Combinational Logic Body
5413 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3];
5414 
  assign mult_o[1] = mult_i[7]^mult_i[4];
5415 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
5416 
  assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[1];
5417 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
5418 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
5419 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
5420 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
5421 
 
5422 
 
5423 
endmodule
5424 
 
5425 
// This is a verilog File Generated
5426 
// By The C++ program That Generates
5427 
// An Gallios Field Hardware Multiplier
5428 
 
5429 
module GF8Mult226(mult_i, mult_o);
5430 
  // Inputs are declared here
5431 
  input [7:0] mult_i;
5432 
  output [7:0] mult_o;
5433 
 
5434 
  // Declaration of Wires And Register are here
5435 
 
5436 
  // Combinational Logic Body
5437 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
5438 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3];
5439 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
5440 
  assign mult_o[3] = mult_i[3]^mult_i[2]^mult_i[0];
5441 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5442 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
5443 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
5444 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
5445 
 
5446 
 
5447 
endmodule
5448 
 
5449 
// This is a verilog File Generated
5450 
// By The C++ program That Generates
5451 
// An Gallios Field Hardware Multiplier
5452 
 
5453 
module GF8Mult227(mult_i, mult_o);
5454 
  // Inputs are declared here
5455 
  input [7:0] mult_i;
5456 
  output [7:0] mult_o;
5457 
 
5458 
  // Declaration of Wires And Register are here
5459 
 
5460 
  // Combinational Logic Body
5461 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
5462 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
5463 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5464 
  assign mult_o[3] = mult_i[7]^mult_i[2]^mult_i[1];
5465 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5466 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5467 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
5468 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
5469 
 
5470 
 
5471 
endmodule
5472 
 
5473 
// This is a verilog File Generated
5474 
// By The C++ program That Generates
5475 
// An Gallios Field Hardware Multiplier
5476 
 
5477 
module GF8Mult228(mult_i, mult_o);
5478 
  // Inputs are declared here
5479 
  input [7:0] mult_i;
5480 
  output [7:0] mult_o;
5481 
 
5482 
  // Declaration of Wires And Register are here
5483 
 
5484 
  // Combinational Logic Body
5485 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
5486 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
5487 
  assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5488 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
5489 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5490 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5491 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5492 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
5493 
 
5494 
 
5495 
endmodule
5496 
 
5497 
// This is a verilog File Generated
5498 
// By The C++ program That Generates
5499 
// An Gallios Field Hardware Multiplier
5500 
 
5501 
module GF8Mult229(mult_i, mult_o);
5502 
  // Inputs are declared here
5503 
  input [7:0] mult_i;
5504 
  output [7:0] mult_o;
5505 
 
5506 
  // Declaration of Wires And Register are here
5507 
 
5508 
  // Combinational Logic Body
5509 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
5510 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
5511 
  assign mult_o[2] = mult_i[3]^mult_i[2]^mult_i[1];
5512 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
5513 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5514 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5515 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5516 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5517 
 
5518 
 
5519 
endmodule
5520 
 
5521 
// This is a verilog File Generated
5522 
// By The C++ program That Generates
5523 
// An Gallios Field Hardware Multiplier
5524 
 
5525 
module GF8Mult230(mult_i, mult_o);
5526 
  // Inputs are declared here
5527 
  input [7:0] mult_i;
5528 
  output [7:0] mult_o;
5529 
 
5530 
  // Declaration of Wires And Register are here
5531 
 
5532 
  // Combinational Logic Body
5533 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5534 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
5535 
  assign mult_o[2] = mult_i[2]^mult_i[1]^mult_i[0];
5536 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
5537 
  assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5538 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5539 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5540 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5541 
 
5542 
 
5543 
endmodule
5544 
 
5545 
// This is a verilog File Generated
5546 
// By The C++ program That Generates
5547 
// An Gallios Field Hardware Multiplier
5548 
 
5549 
module GF8Mult231(mult_i, mult_o);
5550 
  // Inputs are declared here
5551 
  input [7:0] mult_i;
5552 
  output [7:0] mult_o;
5553 
 
5554 
  // Declaration of Wires And Register are here
5555 
 
5556 
  // Combinational Logic Body
5557 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5558 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5559 
  assign mult_o[2] = mult_i[1]^mult_i[0];
5560 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
5561 
  assign mult_o[4] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5562 
  assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5563 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5564 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5565 
 
5566 
 
5567 
endmodule
5568 
 
5569 
// This is a verilog File Generated
5570 
// By The C++ program That Generates
5571 
// An Gallios Field Hardware Multiplier
5572 
 
5573 
module GF8Mult232(mult_i, mult_o);
5574 
  // Inputs are declared here
5575 
  input [7:0] mult_i;
5576 
  output [7:0] mult_o;
5577 
 
5578 
  // Declaration of Wires And Register are here
5579 
 
5580 
  // Combinational Logic Body
5581 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5582 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5583 
  assign mult_o[2] = mult_i[7]^mult_i[0];
5584 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
5585 
  assign mult_o[4] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
5586 
  assign mult_o[5] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5587 
  assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5588 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5589 
 
5590 
 
5591 
endmodule
5592 
 
5593 
// This is a verilog File Generated
5594 
// By The C++ program That Generates
5595 
// An Gallios Field Hardware Multiplier
5596 
 
5597 
module GF8Mult233(mult_i, mult_o);
5598 
  // Inputs are declared here
5599 
  input [7:0] mult_i;
5600 
  output [7:0] mult_o;
5601 
 
5602 
  // Declaration of Wires And Register are here
5603 
 
5604 
  // Combinational Logic Body
5605 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5606 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5607 
  assign mult_o[2] = mult_i[7]^mult_i[6];
5608 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5609 
  assign mult_o[4] = mult_i[6]^mult_i[1]^mult_i[0];
5610 
  assign mult_o[5] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
5611 
  assign mult_o[6] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5612 
  assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5613 
 
5614 
 
5615 
endmodule
5616 
 
5617 
// This is a verilog File Generated
5618 
// By The C++ program That Generates
5619 
// An Gallios Field Hardware Multiplier
5620 
 
5621 
module GF8Mult234(mult_i, mult_o);
5622 
  // Inputs are declared here
5623 
  input [7:0] mult_i;
5624 
  output [7:0] mult_o;
5625 
 
5626 
  // Declaration of Wires And Register are here
5627 
 
5628 
  // Combinational Logic Body
5629 
  assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5630 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5631 
  assign mult_o[2] = mult_i[6]^mult_i[5];
5632 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5633 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[0];
5634 
  assign mult_o[5] = mult_i[6]^mult_i[1]^mult_i[0];
5635 
  assign mult_o[6] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
5636 
  assign mult_o[7] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5637 
 
5638 
 
5639 
endmodule
5640 
 
5641 
// This is a verilog File Generated
5642 
// By The C++ program That Generates
5643 
// An Gallios Field Hardware Multiplier
5644 
 
5645 
module GF8Mult235(mult_i, mult_o);
5646 
  // Inputs are declared here
5647 
  input [7:0] mult_i;
5648 
  output [7:0] mult_o;
5649 
 
5650 
  // Declaration of Wires And Register are here
5651 
 
5652 
  // Combinational Logic Body
5653 
  assign mult_o[0] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5654 
  assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5655 
  assign mult_o[2] = mult_i[5]^mult_i[4];
5656 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5657 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4];
5658 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[0];
5659 
  assign mult_o[6] = mult_i[6]^mult_i[1]^mult_i[0];
5660 
  assign mult_o[7] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
5661 
 
5662 
 
5663 
endmodule
5664 
 
5665 
// This is a verilog File Generated
5666 
// By The C++ program That Generates
5667 
// An Gallios Field Hardware Multiplier
5668 
 
5669 
module GF8Mult236(mult_i, mult_o);
5670 
  // Inputs are declared here
5671 
  input [7:0] mult_i;
5672 
  output [7:0] mult_o;
5673 
 
5674 
  // Declaration of Wires And Register are here
5675 
 
5676 
  // Combinational Logic Body
5677 
  assign mult_o[0] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
5678 
  assign mult_o[1] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5679 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3];
5680 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
5681 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
5682 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4];
5683 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[0];
5684 
  assign mult_o[7] = mult_i[6]^mult_i[1]^mult_i[0];
5685 
 
5686 
 
5687 
endmodule
5688 
 
5689 
// This is a verilog File Generated
5690 
// By The C++ program That Generates
5691 
// An Gallios Field Hardware Multiplier
5692 
 
5693 
module GF8Mult237(mult_i, mult_o);
5694 
  // Inputs are declared here
5695 
  input [7:0] mult_i;
5696 
  output [7:0] mult_o;
5697 
 
5698 
  // Declaration of Wires And Register are here
5699 
 
5700 
  // Combinational Logic Body
5701 
  assign mult_o[0] = mult_i[6]^mult_i[1]^mult_i[0];
5702 
  assign mult_o[1] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
5703 
  assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[2];
5704 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
5705 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
5706 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
5707 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4];
5708 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[0];
5709 
 
5710 
 
5711 
endmodule
5712 
 
5713 
// This is a verilog File Generated
5714 
// By The C++ program That Generates
5715 
// An Gallios Field Hardware Multiplier
5716 
 
5717 
module GF8Mult238(mult_i, mult_o);
5718 
  // Inputs are declared here
5719 
  input [7:0] mult_i;
5720 
  output [7:0] mult_o;
5721 
 
5722 
  // Declaration of Wires And Register are here
5723 
 
5724 
  // Combinational Logic Body
5725 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[0];
5726 
  assign mult_o[1] = mult_i[6]^mult_i[1]^mult_i[0];
5727 
  assign mult_o[2] = mult_i[5]^mult_i[2]^mult_i[1];
5728 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
5729 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5730 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
5731 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
5732 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4];
5733 
 
5734 
 
5735 
endmodule
5736 
 
5737 
// This is a verilog File Generated
5738 
// By The C++ program That Generates
5739 
// An Gallios Field Hardware Multiplier
5740 
 
5741 
module GF8Mult239(mult_i, mult_o);
5742 
  // Inputs are declared here
5743 
  input [7:0] mult_i;
5744 
  output [7:0] mult_o;
5745 
 
5746 
  // Declaration of Wires And Register are here
5747 
 
5748 
  // Combinational Logic Body
5749 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4];
5750 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[0];
5751 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
5752 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
5753 
  assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5754 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5755 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
5756 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
5757 
 
5758 
 
5759 
endmodule
5760 
 
5761 
// This is a verilog File Generated
5762 
// By The C++ program That Generates
5763 
// An Gallios Field Hardware Multiplier
5764 
 
5765 
module GF8Mult240(mult_i, mult_o);
5766 
  // Inputs are declared here
5767 
  input [7:0] mult_i;
5768 
  output [7:0] mult_o;
5769 
 
5770 
  // Declaration of Wires And Register are here
5771 
 
5772 
  // Combinational Logic Body
5773 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
5774 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4];
5775 
  assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[0];
5776 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
5777 
  assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5778 
  assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5779 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5780 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
5781 
 
5782 
 
5783 
endmodule
5784 
 
5785 
// This is a verilog File Generated
5786 
// By The C++ program That Generates
5787 
// An Gallios Field Hardware Multiplier
5788 
 
5789 
module GF8Mult241(mult_i, mult_o);
5790 
  // Inputs are declared here
5791 
  input [7:0] mult_i;
5792 
  output [7:0] mult_o;
5793 
 
5794 
  // Declaration of Wires And Register are here
5795 
 
5796 
  // Combinational Logic Body
5797 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
5798 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
5799 
  assign mult_o[2] = mult_i[5]^mult_i[2];
5800 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5801 
  assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5802 
  assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5803 
  assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5804 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5805 
 
5806 
 
5807 
endmodule
5808 
 
5809 
// This is a verilog File Generated
5810 
// By The C++ program That Generates
5811 
// An Gallios Field Hardware Multiplier
5812 
 
5813 
module GF8Mult242(mult_i, mult_o);
5814 
  // Inputs are declared here
5815 
  input [7:0] mult_i;
5816 
  output [7:0] mult_o;
5817 
 
5818 
  // Declaration of Wires And Register are here
5819 
 
5820 
  // Combinational Logic Body
5821 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5822 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
5823 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[1];
5824 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5825 
  assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
5826 
  assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5827 
  assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5828 
  assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5829 
 
5830 
 
5831 
endmodule
5832 
 
5833 
// This is a verilog File Generated
5834 
// By The C++ program That Generates
5835 
// An Gallios Field Hardware Multiplier
5836 
 
5837 
module GF8Mult243(mult_i, mult_o);
5838 
  // Inputs are declared here
5839 
  input [7:0] mult_i;
5840 
  output [7:0] mult_o;
5841 
 
5842 
  // Declaration of Wires And Register are here
5843 
 
5844 
  // Combinational Logic Body
5845 
  assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5846 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5847 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
5848 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5849 
  assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
5850 
  assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
5851 
  assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5852 
  assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5853 
 
5854 
 
5855 
endmodule
5856 
 
5857 
// This is a verilog File Generated
5858 
// By The C++ program That Generates
5859 
// An Gallios Field Hardware Multiplier
5860 
 
5861 
module GF8Mult244(mult_i, mult_o);
5862 
  // Inputs are declared here
5863 
  input [7:0] mult_i;
5864 
  output [7:0] mult_o;
5865 
 
5866 
  // Declaration of Wires And Register are here
5867 
 
5868 
  // Combinational Logic Body
5869 
  assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5870 
  assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5871 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[2];
5872 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
5873 
  assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
5874 
  assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
5875 
  assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
5876 
  assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5877 
 
5878 
 
5879 
endmodule
5880 
 
5881 
// This is a verilog File Generated
5882 
// By The C++ program That Generates
5883 
// An Gallios Field Hardware Multiplier
5884 
 
5885 
module GF8Mult245(mult_i, mult_o);
5886 
  // Inputs are declared here
5887 
  input [7:0] mult_i;
5888 
  output [7:0] mult_o;
5889 
 
5890 
  // Declaration of Wires And Register are here
5891 
 
5892 
  // Combinational Logic Body
5893 
  assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5894 
  assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
5895 
  assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
5896 
  assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
5897 
  assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3];
5898 
  assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
5899 
  assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
5900 
  assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
5901 
 
5902 
 
5903 
endmodule
5904 
 
5905 
// This is a verilog File Generated
5906 
// By The C++ program That Generates
5907 
// An Gallios Field Hardware Multiplier
5908 
 
5909 
module GF8Mult246(mult_i, mult_o);
5910 
  // Inputs are declared here
5911 
  input [7:0] mult_i;
5912 
  output [7:0] mult_o;
5913 
 
5914 
  // Declaration of Wires And Register are here
5915 
 
5916 
  // Combinational Logic Body
5917 
  assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
5918 
  assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
5919 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
5920 
  assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
5921 
  assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[2];
5922 
  assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3];
5923 
  assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
5924 
  assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
5925 
 
5926 
 
5927 
endmodule
5928 
 
5929 
// This is a verilog File Generated
5930 
// By The C++ program That Generates
5931 
// An Gallios Field Hardware Multiplier
5932 
 
5933 
module GF8Mult247(mult_i, mult_o);
5934 
  // Inputs are declared here
5935 
  input [7:0] mult_i;
5936 
  output [7:0] mult_o;
5937 
 
5938 
  // Declaration of Wires And Register are here
5939 
 
5940 
  // Combinational Logic Body
5941 
  assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
5942 
  assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
5943 
  assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
5944 
  assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
5945 
  assign mult_o[4] = mult_i[4]^mult_i[2]^mult_i[1];
5946 
  assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[2];
5947 
  assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3];
5948 
  assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
5949 
 
5950 
 
5951 
endmodule
5952 
 
5953 
// This is a verilog File Generated
5954 
// By The C++ program That Generates
5955 
// An Gallios Field Hardware Multiplier
5956 
 
5957 
module GF8Mult248(mult_i, mult_o);
5958 
  // Inputs are declared here
5959 
  input [7:0] mult_i;
5960 
  output [7:0] mult_o;
5961 
 
5962 
  // Declaration of Wires And Register are here
5963 
 
5964 
  // Combinational Logic Body
5965 
  assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
5966 
  assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
5967 
  assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
5968 
  assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
5969 
  assign mult_o[4] = mult_i[3]^mult_i[1]^mult_i[0];
5970 
  assign mult_o[5] = mult_i[4]^mult_i[2]^mult_i[1];
5971 
  assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[2];
5972 
  assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3];
5973 
 
5974 
 
5975 
endmodule
5976 
 
5977 
// This is a verilog File Generated
5978 
// By The C++ program That Generates
5979 
// An Gallios Field Hardware Multiplier
5980 
 
5981 
module GF8Mult249(mult_i, mult_o);
5982 
  // Inputs are declared here
5983 
  input [7:0] mult_i;
5984 
  output [7:0] mult_o;
5985 
 
5986 
  // Declaration of Wires And Register are here
5987 
 
5988 
  // Combinational Logic Body
5989 
  assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3];
5990 
  assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
5991 
  assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
5992 
  assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
5993 
  assign mult_o[4] = mult_i[2]^mult_i[0];
5994 
  assign mult_o[5] = mult_i[3]^mult_i[1]^mult_i[0];
5995 
  assign mult_o[6] = mult_i[4]^mult_i[2]^mult_i[1];
5996 
  assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[2];
5997 
 
5998 
 
5999 
endmodule
6000 
 
6001 
// This is a verilog File Generated
6002 
// By The C++ program That Generates
6003 
// An Gallios Field Hardware Multiplier
6004 
 
6005 
module GF8Mult250(mult_i, mult_o);
6006 
  // Inputs are declared here
6007 
  input [7:0] mult_i;
6008 
  output [7:0] mult_o;
6009 
 
6010 
  // Declaration of Wires And Register are here
6011 
 
6012 
  // Combinational Logic Body
6013 
  assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[2];
6014 
  assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3];
6015 
  assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
6016 
  assign mult_o[3] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
6017 
  assign mult_o[4] = mult_i[1];
6018 
  assign mult_o[5] = mult_i[2]^mult_i[0];
6019 
  assign mult_o[6] = mult_i[3]^mult_i[1]^mult_i[0];
6020 
  assign mult_o[7] = mult_i[4]^mult_i[2]^mult_i[1];
6021 
 
6022 
 
6023 
endmodule
6024 
 
6025 
// This is a verilog File Generated
6026 
// By The C++ program That Generates
6027 
// An Gallios Field Hardware Multiplier
6028 
 
6029 
module GF8Mult251(mult_i, mult_o);
6030 
  // Inputs are declared here
6031 
  input [7:0] mult_i;
6032 
  output [7:0] mult_o;
6033 
 
6034 
  // Declaration of Wires And Register are here
6035 
 
6036 
  // Combinational Logic Body
6037 
  assign mult_o[0] = mult_i[4]^mult_i[2]^mult_i[1];
6038 
  assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[2];
6039 
  assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
6040 
  assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
6041 
  assign mult_o[4] = mult_i[0];
6042 
  assign mult_o[5] = mult_i[1];
6043 
  assign mult_o[6] = mult_i[2]^mult_i[0];
6044 
  assign mult_o[7] = mult_i[3]^mult_i[1]^mult_i[0];
6045 
 
6046 
 
6047 
endmodule
6048 
 
6049 
// This is a verilog File Generated
6050 
// By The C++ program That Generates
6051 
// An Gallios Field Hardware Multiplier
6052 
 
6053 
module GF8Mult252(mult_i, mult_o);
6054 
  // Inputs are declared here
6055 
  input [7:0] mult_i;
6056 
  output [7:0] mult_o;
6057 
 
6058 
  // Declaration of Wires And Register are here
6059 
 
6060 
  // Combinational Logic Body
6061 
  assign mult_o[0] = mult_i[3]^mult_i[1]^mult_i[0];
6062 
  assign mult_o[1] = mult_i[4]^mult_i[2]^mult_i[1];
6063 
  assign mult_o[2] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
6064 
  assign mult_o[3] = mult_i[6]^mult_i[2]^mult_i[0];
6065 
  assign mult_o[4] = mult_i[7];
6066 
  assign mult_o[5] = mult_i[0];
6067 
  assign mult_o[6] = mult_i[1];
6068 
  assign mult_o[7] = mult_i[2]^mult_i[0];
6069 
 
6070 
 
6071 
endmodule
6072 
 
6073 
// This is a verilog File Generated
6074 
// By The C++ program That Generates
6075 
// An Gallios Field Hardware Multiplier
6076 
 
6077 
module GF8Mult253(mult_i, mult_o);
6078 
  // Inputs are declared here
6079 
  input [7:0] mult_i;
6080 
  output [7:0] mult_o;
6081 
 
6082 
  // Declaration of Wires And Register are here
6083 
 
6084 
  // Combinational Logic Body
6085 
  assign mult_o[0] = mult_i[2]^mult_i[0];
6086 
  assign mult_o[1] = mult_i[3]^mult_i[1]^mult_i[0];
6087 
  assign mult_o[2] = mult_i[4]^mult_i[1]^mult_i[0];
6088 
  assign mult_o[3] = mult_i[5]^mult_i[1];
6089 
  assign mult_o[4] = mult_i[6];
6090 
  assign mult_o[5] = mult_i[7];
6091 
  assign mult_o[6] = mult_i[0];
6092 
  assign mult_o[7] = mult_i[1];
6093 
 
6094 
 
6095 
endmodule
6096 
 
6097 
// This is a verilog File Generated
6098 
// By The C++ program That Generates
6099 
// An Gallios Field Hardware Multiplier
6100 
 
6101 
module GF8Mult254(mult_i, mult_o);
6102 
  // Inputs are declared here
6103 
  input [7:0] mult_i;
6104 
  output [7:0] mult_o;
6105 
 
6106 
  // Declaration of Wires And Register are here
6107 
 
6108 
  // Combinational Logic Body
6109 
  assign mult_o[0] = mult_i[1];
6110 
  assign mult_o[1] = mult_i[2]^mult_i[0];
6111 
  assign mult_o[2] = mult_i[3]^mult_i[0];
6112 
  assign mult_o[3] = mult_i[4]^mult_i[0];
6113 
  assign mult_o[4] = mult_i[5];
6114 
  assign mult_o[5] = mult_i[6];
6115 
  assign mult_o[6] = mult_i[7];
6116 
  assign mult_o[7] = mult_i[0];
6117 
 
6118 
 
6119 
endmodule
6120 
 

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