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-------------------------------------------------------------------------------- 
-- Company:  
-- Engineer: 
-- 
-- Create Date:   17:40:28 12/13/2009 
-- Design Name:    
-- Module Name:   
-- Project Name:  ciosspartan 
-- Target Device:   
-- Tool versions:   
-- Description:    
--  
-- VHDL Test Bench Created by ISE for module: rsa_top 
--  
-- Dependencies: 
--  
-- Revision: 
-- Revision 0.01 - File Created 
-- Additional Comments: 
-- 
-- Notes:  
-- This testbench has been automatically generated using types std_logic and 
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation  
-- simulation model. 
-------------------------------------------------------------------------------- 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity test_rsa_512 is
end test_rsa_512;
 
architecture behavior of test_rsa_512 is
 
  -- Component Declaration for the Unit Under Test (UUT) 
 
  component rsa_top
    port(
      clk       : in  std_logic;
      reset     : in  std_logic;
      valid_in  : in  std_logic;
      start_in  : in  std_logic;
      x         : in  std_logic_vector(15 downto 0);
      y         : in  std_logic_vector(15 downto 0);
      m         : in  std_logic_vector(15 downto 0);
      r_c       : in  std_logic_vector(15 downto 0);
      s         : out std_logic_vector(15 downto 0);
      valid_out : out std_logic;
      bit_size  : in  std_logic_vector(15 downto 0)
      );
  end component;
 
 
  --Inputs 
  signal clk       : std_logic                     := '0';
  signal reset     : std_logic                     := '0';
  signal valid_in  : std_logic                     := '0';
  signal start_in  : std_logic;
  signal x         : std_logic_vector(15 downto 0) := (others => '0');
  signal y         : std_logic_vector(15 downto 0) := (others => '0');
  signal m         : std_logic_vector(15 downto 0) := (others => '0');
  signal r_c       : std_logic_vector(15 downto 0) := (others => '0');
  signal n_c       : std_logic_vector(15 downto 0) := (others => '0');
  signal bit_size  : std_logic_vector(15 downto 0) := x"0200";
  --Outputs 
  signal s         : std_logic_vector(15 downto 0);
  signal valid_out : std_logic;
 
  -- Clock period definitions 
  constant clk_period : time := 1ns;
 
begin
 
  -- Instantiate the Unit Under Test (UUT) 
  uut : rsa_top port map (
    clk       => clk,
    reset     => reset,
    valid_in  => valid_in,
    start_in  => start_in,
    x         => x,
    y         => y,
    m         => m,
    r_c       => r_c,
    s         => s,
    valid_out => valid_out,
    bit_size  => bit_size
    );
 
  -- Clock process definitions 
  clk_process : process
  begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;
 
 
  -- Stimulus process 
  stim_proc : process
  begin
    start_in <= '0';
    valid_in <= '0';
    -- hold reset state for 100ms. 
    reset    <= '1';
    wait for 10ns;
    reset    <= '0';
    wait for clk_period*10;
 
    -- insert stimulus here  
 
--n_c and valid signal and the r_c constant are also required
    --n_c      <= x"738f";
    m        <= x"b491";
    --Start_in to begin n_c calculation
    start_in <= '1';
    wait for clk_period;
    start_in <= '0';
    wait for clk_period*6;
    --Start data flow
    x        <= x"f3ad";
    y        <= x"42b1";
    m        <= x"b491";
    r_c      <= x"f579";
    valid_in <= '1';
    wait for clk_period;
    x        <= x"8e40";
    y        <= x"1ad3";
    m        <= x"1417";
    r_c      <= x"6ee9";
    wait for clk_period;
    x        <= x"6af9";
    y        <= x"a827";
    m        <= x"b498";
    r_c      <= x"972d";
    wait for clk_period;
    x        <= x"4e63";
    y        <= x"0d64";
    m        <= x"e1b7";
    r_c      <= x"5052";
    wait for clk_period;
    x        <= x"9600";
    y        <= x"3f76";
    m        <= x"e47c";
    r_c      <= x"1dca";
    wait for clk_period;
    x        <= x"68f4";
    y        <= x"6670";
    m        <= x"b186";
    r_c      <= x"bc81";
    wait for clk_period;
    x        <= x"5a12";
    y        <= x"5a1c";
    m        <= x"93f0";
    r_c      <= x"377e";
    wait for clk_period;
    x        <= x"d62e";
    y        <= x"4844";
    m        <= x"b183";
    r_c      <= x"04ef";
    wait for clk_period;
    x        <= x"8fc1";
    y        <= x"d5f2";
    m        <= x"f8f1";
    r_c      <= x"3a2a";
    wait for clk_period;
    x        <= x"031d";
    y        <= x"b65a";
    m        <= x"eed1";
    r_c      <= x"291b";
    wait for clk_period;
    x        <= x"f496";
    y        <= x"034f";
    m        <= x"0083";
    r_c      <= x"c159";
    wait for clk_period;
    x        <= x"1268";
    y        <= x"9635";
    m        <= x"981c";
    r_c      <= x"9336";
    wait for clk_period;
    x        <= x"2e5a";
    y        <= x"386e";
    m        <= x"6441";
    r_c      <= x"1bd0";
    wait for clk_period;
    x        <= x"c1d6";
    y        <= x"fb73";
    m        <= x"fcd8";
    r_c      <= x"317d";
    wait for clk_period;
    x        <= x"cd8f";
    y        <= x"5623";
    m        <= x"cbf0";
    r_c      <= x"64b4";
    wait for clk_period;
    x        <= x"e4d2";
    y        <= x"9041";
    m        <= x"e3ca";
    r_c      <= x"8793";
    wait for clk_period;
    x        <= x"36c6";
    y        <= x"99da";
    m        <= x"41d9";
    r_c      <= x"85f5";
    wait for clk_period;
    x        <= x"df4a";
    y        <= x"cd68";
    m        <= x"b7a0";
    r_c      <= x"7c8d";
    wait for clk_period;
    x        <= x"8e40";
    y        <= x"9a94";
    m        <= x"146e";
    r_c      <= x"64d9";
    wait for clk_period;
    x        <= x"6af9";
    y        <= x"ccc8";
    m        <= x"4776";
    r_c      <= x"c7f6";
    wait for clk_period;
    x        <= x"4e63";
    y        <= x"ed49";
    m        <= x"ec50";
    r_c      <= x"fba0";
    wait for clk_period;
    x        <= x"9600";
    y        <= x"4d25";
    m        <= x"c07c";
    r_c      <= x"e3e0";
    wait for clk_period;
    x        <= x"68f4";
    y        <= x"3b8e";
    m        <= x"e698";
    r_c      <= x"b567";
    wait for clk_period;
    x        <= x"5a12";
    y        <= x"36d5";
    m        <= x"d85f";
    r_c      <= x"3172";
    wait for clk_period;
    x        <= x"d62e";
    y        <= x"3a75";
    m        <= x"729c";
    r_c      <= x"111a";
    wait for clk_period;
    x        <= x"8fc1";
    y        <= x"77a3";
    m        <= x"19b6";
    r_c      <= x"1971";
    wait for clk_period;
    x        <= x"d2cd";
    y        <= x"367f";
    m        <= x"05d3";
    r_c      <= x"9f9b";
    wait for clk_period;
    x        <= x"c6e4";
    y        <= x"68de";
    m        <= x"cacd";
    r_c      <= x"b574";
    wait for clk_period;
    x        <= x"4a36";
    y        <= x"59a4";
    m        <= x"e16f";
    r_c      <= x"4a50";
    wait for clk_period;
    x        <= x"f6df";
    y        <= x"9f89";
    m        <= x"f67b";
    r_c      <= x"6d56";
    wait for clk_period;
    x        <= x"061c";
    y        <= x"ed71";
    m        <= x"7066";
    r_c      <= x"bdc6";
    wait for clk_period;
    x        <= x"06c8";
    y        <= x"059f";
    m        <= x"08de";
    r_c      <= x"0400";
    wait for clk_period;
    valid_in <= '0';
 
--valid_in <='0';
    wait for clk_period*200000;
 
    --Now with the public key x"10001"; 
 
    bit_size <= x"0011";
    valid_in <= '1';
    x        <= x"f3ad";
    y        <= x"0001";
    m        <= x"b491";
    r_c      <= x"f579";
    wait for clk_period;
    x        <= x"8e40";
    y        <= x"0001";
    m        <= x"1417";
    r_c      <= x"6ee9";
    wait for clk_period;
    x        <= x"6af9";
    y        <= x"0000";
    m        <= x"b498";
    r_c      <= x"972d";
    wait for clk_period;
    x        <= x"4e63";
    m        <= x"e1b7";
    r_c      <= x"5052";
    wait for clk_period;
    x        <= x"9600";
    m        <= x"e47c";
    r_c      <= x"1dca";
    wait for clk_period;
    x        <= x"68f4";
    m        <= x"b186";
    r_c      <= x"bc81";
    wait for clk_period;
    x        <= x"5a12";
    m        <= x"93f0";
    r_c      <= x"377e";
    wait for clk_period;
    x        <= x"d62e";
    m        <= x"b183";
    r_c      <= x"04ef";
    wait for clk_period;
    x        <= x"8fc1";
    m        <= x"f8f1";
    r_c      <= x"3a2a";
    wait for clk_period;
    x        <= x"031d";
    m        <= x"eed1";
    r_c      <= x"291b";
    wait for clk_period;
    x        <= x"f496";
    m        <= x"0083";
    r_c      <= x"c159";
    wait for clk_period;
    x        <= x"1268";
 
    m   <= x"981c";
    r_c <= x"9336";
    wait for clk_period;
    x   <= x"2e5a";
 
    m   <= x"6441";
    r_c <= x"1bd0";
    wait for clk_period;
    x   <= x"c1d6";
 
    m   <= x"fcd8";
    r_c <= x"317d";
    wait for clk_period;
    x   <= x"cd8f";
 
    m   <= x"cbf0";
    r_c <= x"64b4";
    wait for clk_period;
    x   <= x"e4d2";
 
    m   <= x"e3ca";
    r_c <= x"8793";
    wait for clk_period;
    x   <= x"36c6";
 
    m   <= x"41d9";
    r_c <= x"85f5";
    wait for clk_period;
    x   <= x"df4a";
 
    m   <= x"b7a0";
    r_c <= x"7c8d";
    wait for clk_period;
    x   <= x"8e40";
 
    m   <= x"146e";
    r_c <= x"64d9";
    wait for clk_period;
    x   <= x"6af9";
 
    m   <= x"4776";
    r_c <= x"c7f6";
    wait for clk_period;
    x   <= x"4e63";
 
    m   <= x"ec50";
    r_c <= x"fba0";
    wait for clk_period;
    x   <= x"9600";
 
    m   <= x"c07c";
    r_c <= x"e3e0";
    wait for clk_period;
    x   <= x"68f4";
 
    m   <= x"e698";
    r_c <= x"b567";
    wait for clk_period;
    x   <= x"5a12";
 
    m   <= x"d85f";
    r_c <= x"3172";
    wait for clk_period;
    x   <= x"d62e";
 
    m   <= x"729c";
    r_c <= x"111a";
    wait for clk_period;
    x   <= x"8fc1";
 
    m   <= x"19b6";
    r_c <= x"1971";
    wait for clk_period;
    x   <= x"d2cd";
 
    m   <= x"05d3";
    r_c <= x"9f9b";
    wait for clk_period;
    x   <= x"c6e4";
 
    m   <= x"cacd";
    r_c <= x"b574";
    wait for clk_period;
    x   <= x"4a36";
 
    m   <= x"e16f";
    r_c <= x"4a50";
    wait for clk_period;
    x   <= x"f6df";
 
    m   <= x"f67b";
    r_c <= x"6d56";
    wait for clk_period;
    x   <= x"061c";
 
    m   <= x"7066";
    r_c <= x"bdc6";
    wait for clk_period;
    x   <= x"06c8";
 
    m        <= x"08de";
    r_c      <= x"0400";
    wait for clk_period;
    valid_in <= '0';
 
    wait;
  end process;
 
end;

Line No.	Rev	Author	Line
1	3	jcastillo	`--------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 17:40:28 12/13/2009`
6			`-- Design Name:`
7			`-- Module Name:`
8			`-- Project Name: ciosspartan`
9			`-- Target Device:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- VHDL Test Bench Created by ISE for module: rsa_top`
14			`--`
15			`-- Dependencies:`
16			`--`
17			`-- Revision:`
18			`-- Revision 0.01 - File Created`
19			`-- Additional Comments:`
20			`--`
21			`-- Notes:`
22			`-- This testbench has been automatically generated using types std_logic and`
23			`-- std_logic_vector for the ports of the unit under test. Xilinx recommends`
24			`-- that these types always be used for the top-level I/O of a design in order`
25			`-- to guarantee that the testbench will bind correctly to the post-implementation`
26			`-- simulation model.`
27			`--------------------------------------------------------------------------------`
28			`library ieee;`
29			`use ieee.std_logic_1164.all;`
30			`use ieee.std_logic_unsigned.all;`
31			`use ieee.numeric_std.all;`
32
33			`entity test_rsa_512 is`
34			`end test_rsa_512;`
35
36			`architecture behavior of test_rsa_512 is`
37
38			`-- Component Declaration for the Unit Under Test (UUT)`
39
40			`component rsa_top`
41			`port(`
42			`clk : in std_logic;`
43			`reset : in std_logic;`
44			`valid_in : in std_logic;`
45	11	jcastillo	`start_in : in std_logic;`
46	3	jcastillo	`x : in std_logic_vector(15 downto 0);`
47			`y : in std_logic_vector(15 downto 0);`
48			`m : in std_logic_vector(15 downto 0);`
49			`r_c : in std_logic_vector(15 downto 0);`
50			`s : out std_logic_vector(15 downto 0);`
51			`valid_out : out std_logic;`
52			`bit_size : in std_logic_vector(15 downto 0)`
53			`);`
54			`end component;`
55
56
57			`--Inputs`
58			`signal clk : std_logic := '0';`
59			`signal reset : std_logic := '0';`
60			`signal valid_in : std_logic := '0';`
61	11	jcastillo	`signal start_in : std_logic;`
62	3	jcastillo	`signal x : std_logic_vector(15 downto 0) := (others => '0');`
63			`signal y : std_logic_vector(15 downto 0) := (others => '0');`
64			`signal m : std_logic_vector(15 downto 0) := (others => '0');`
65			`signal r_c : std_logic_vector(15 downto 0) := (others => '0');`
66			`signal n_c : std_logic_vector(15 downto 0) := (others => '0');`
67			`signal bit_size : std_logic_vector(15 downto 0) := x"0200";`
68			`--Outputs`
69			`signal s : std_logic_vector(15 downto 0);`
70			`signal valid_out : std_logic;`
71
72			`-- Clock period definitions`
73			`constant clk_period : time := 1ns;`
74
75			`begin`
76
77			`-- Instantiate the Unit Under Test (UUT)`
78			`uut : rsa_top port map (`
79			`clk => clk,`
80			`reset => reset,`
81			`valid_in => valid_in,`
82	11	jcastillo	`start_in => start_in,`
83	3	jcastillo	`x => x,`
84			`y => y,`
85			`m => m,`
86			`r_c => r_c,`
87			`s => s,`
88			`valid_out => valid_out,`
89			`bit_size => bit_size`
90			`);`
91
92			`-- Clock process definitions`
93			`clk_process : process`
94			`begin`
95			`clk <= '0';`
96			`wait for clk_period/2;`
97			`clk <= '1';`
98			`wait for clk_period/2;`
99			`end process;`
100
101
102			`-- Stimulus process`
103			`stim_proc : process`
104			`begin`
105	11	jcastillo	`start_in <= '0';`
106	3	jcastillo	`valid_in <= '0';`
107			`-- hold reset state for 100ms.`
108			`reset <= '1';`
109			`wait for 10ns;`
110			`reset <= '0';`
111			`wait for clk_period*10;`
112
113			`-- insert stimulus here`
114
115			`--n_c and valid signal and the r_c constant are also required`
116	11	jcastillo	`--n_c <= x"738f";`
117			`m <= x"b491";`
118			`--Start_in to begin n_c calculation`
119			`start_in <= '1';`
120			`wait for clk_period;`
121			`start_in <= '0';`
122			`wait for clk_period*6;`
123			`--Start data flow`
124	3	jcastillo	`x <= x"f3ad";`
125			`y <= x"42b1";`
126			`m <= x"b491";`
127			`r_c <= x"f579";`
128	11	jcastillo	`valid_in <= '1';`
129	3	jcastillo	`wait for clk_period;`
130			`x <= x"8e40";`
131			`y <= x"1ad3";`
132			`m <= x"1417";`
133			`r_c <= x"6ee9";`
134			`wait for clk_period;`
135			`x <= x"6af9";`
136			`y <= x"a827";`
137			`m <= x"b498";`
138			`r_c <= x"972d";`
139			`wait for clk_period;`
140			`x <= x"4e63";`
141			`y <= x"0d64";`
142			`m <= x"e1b7";`
143			`r_c <= x"5052";`
144			`wait for clk_period;`
145			`x <= x"9600";`
146			`y <= x"3f76";`
147			`m <= x"e47c";`
148			`r_c <= x"1dca";`
149			`wait for clk_period;`
150			`x <= x"68f4";`
151			`y <= x"6670";`
152			`m <= x"b186";`
153			`r_c <= x"bc81";`
154			`wait for clk_period;`
155			`x <= x"5a12";`
156			`y <= x"5a1c";`
157			`m <= x"93f0";`
158			`r_c <= x"377e";`
159			`wait for clk_period;`
160			`x <= x"d62e";`
161			`y <= x"4844";`
162			`m <= x"b183";`
163			`r_c <= x"04ef";`
164			`wait for clk_period;`
165			`x <= x"8fc1";`
166			`y <= x"d5f2";`
167			`m <= x"f8f1";`
168			`r_c <= x"3a2a";`
169			`wait for clk_period;`
170			`x <= x"031d";`
171			`y <= x"b65a";`
172			`m <= x"eed1";`
173			`r_c <= x"291b";`
174			`wait for clk_period;`
175			`x <= x"f496";`
176			`y <= x"034f";`
177			`m <= x"0083";`
178			`r_c <= x"c159";`
179			`wait for clk_period;`
180			`x <= x"1268";`
181			`y <= x"9635";`
182			`m <= x"981c";`
183			`r_c <= x"9336";`
184			`wait for clk_period;`
185			`x <= x"2e5a";`
186			`y <= x"386e";`
187			`m <= x"6441";`
188			`r_c <= x"1bd0";`
189			`wait for clk_period;`
190			`x <= x"c1d6";`
191			`y <= x"fb73";`
192			`m <= x"fcd8";`
193			`r_c <= x"317d";`
194			`wait for clk_period;`
195			`x <= x"cd8f";`
196			`y <= x"5623";`
197			`m <= x"cbf0";`
198			`r_c <= x"64b4";`
199			`wait for clk_period;`
200			`x <= x"e4d2";`
201			`y <= x"9041";`
202			`m <= x"e3ca";`
203			`r_c <= x"8793";`
204			`wait for clk_period;`
205			`x <= x"36c6";`
206			`y <= x"99da";`
207			`m <= x"41d9";`
208			`r_c <= x"85f5";`
209			`wait for clk_period;`
210			`x <= x"df4a";`
211			`y <= x"cd68";`
212			`m <= x"b7a0";`
213			`r_c <= x"7c8d";`
214			`wait for clk_period;`
215			`x <= x"8e40";`
216			`y <= x"9a94";`
217			`m <= x"146e";`
218			`r_c <= x"64d9";`
219			`wait for clk_period;`
220			`x <= x"6af9";`
221			`y <= x"ccc8";`
222			`m <= x"4776";`
223			`r_c <= x"c7f6";`
224			`wait for clk_period;`
225			`x <= x"4e63";`
226			`y <= x"ed49";`
227			`m <= x"ec50";`
228			`r_c <= x"fba0";`
229			`wait for clk_period;`
230			`x <= x"9600";`
231			`y <= x"4d25";`
232			`m <= x"c07c";`
233			`r_c <= x"e3e0";`
234			`wait for clk_period;`
235			`x <= x"68f4";`
236			`y <= x"3b8e";`
237			`m <= x"e698";`
238			`r_c <= x"b567";`
239			`wait for clk_period;`
240			`x <= x"5a12";`
241			`y <= x"36d5";`
242			`m <= x"d85f";`
243			`r_c <= x"3172";`
244			`wait for clk_period;`
245			`x <= x"d62e";`
246			`y <= x"3a75";`
247			`m <= x"729c";`
248			`r_c <= x"111a";`
249			`wait for clk_period;`
250			`x <= x"8fc1";`
251			`y <= x"77a3";`
252			`m <= x"19b6";`
253			`r_c <= x"1971";`
254			`wait for clk_period;`
255			`x <= x"d2cd";`
256			`y <= x"367f";`
257			`m <= x"05d3";`
258			`r_c <= x"9f9b";`
259			`wait for clk_period;`
260			`x <= x"c6e4";`
261			`y <= x"68de";`
262			`m <= x"cacd";`
263			`r_c <= x"b574";`
264			`wait for clk_period;`
265			`x <= x"4a36";`
266			`y <= x"59a4";`
267			`m <= x"e16f";`
268			`r_c <= x"4a50";`
269			`wait for clk_period;`
270			`x <= x"f6df";`
271			`y <= x"9f89";`
272			`m <= x"f67b";`
273			`r_c <= x"6d56";`
274			`wait for clk_period;`
275			`x <= x"061c";`
276			`y <= x"ed71";`
277			`m <= x"7066";`
278			`r_c <= x"bdc6";`
279			`wait for clk_period;`
280			`x <= x"06c8";`
281			`y <= x"059f";`
282			`m <= x"08de";`
283			`r_c <= x"0400";`
284			`wait for clk_period;`
285			`valid_in <= '0';`
286
287			`--valid_in <='0';`
288			`wait for clk_period*200000;`
289
290			`--Now with the public key x"10001";`
291
292			`bit_size <= x"0011";`
293			`valid_in <= '1';`
294			`x <= x"f3ad";`
295			`y <= x"0001";`
296			`m <= x"b491";`
297			`r_c <= x"f579";`
298			`wait for clk_period;`
299			`x <= x"8e40";`
300			`y <= x"0001";`
301			`m <= x"1417";`
302			`r_c <= x"6ee9";`
303			`wait for clk_period;`
304			`x <= x"6af9";`
305			`y <= x"0000";`
306			`m <= x"b498";`
307			`r_c <= x"972d";`
308			`wait for clk_period;`
309			`x <= x"4e63";`
310			`m <= x"e1b7";`
311			`r_c <= x"5052";`
312			`wait for clk_period;`
313			`x <= x"9600";`
314			`m <= x"e47c";`
315			`r_c <= x"1dca";`
316			`wait for clk_period;`
317			`x <= x"68f4";`
318			`m <= x"b186";`
319			`r_c <= x"bc81";`
320			`wait for clk_period;`
321			`x <= x"5a12";`
322			`m <= x"93f0";`
323			`r_c <= x"377e";`
324			`wait for clk_period;`
325			`x <= x"d62e";`
326			`m <= x"b183";`
327			`r_c <= x"04ef";`
328			`wait for clk_period;`
329			`x <= x"8fc1";`
330			`m <= x"f8f1";`
331			`r_c <= x"3a2a";`
332			`wait for clk_period;`
333			`x <= x"031d";`
334			`m <= x"eed1";`
335			`r_c <= x"291b";`
336			`wait for clk_period;`
337			`x <= x"f496";`
338			`m <= x"0083";`
339			`r_c <= x"c159";`
340			`wait for clk_period;`
341			`x <= x"1268";`
342
343			`m <= x"981c";`
344			`r_c <= x"9336";`
345			`wait for clk_period;`
346			`x <= x"2e5a";`
347
348			`m <= x"6441";`
349			`r_c <= x"1bd0";`
350			`wait for clk_period;`
351			`x <= x"c1d6";`
352
353			`m <= x"fcd8";`
354			`r_c <= x"317d";`
355			`wait for clk_period;`
356			`x <= x"cd8f";`
357
358			`m <= x"cbf0";`
359			`r_c <= x"64b4";`
360			`wait for clk_period;`
361			`x <= x"e4d2";`
362
363			`m <= x"e3ca";`
364			`r_c <= x"8793";`
365			`wait for clk_period;`
366			`x <= x"36c6";`
367
368			`m <= x"41d9";`
369			`r_c <= x"85f5";`
370			`wait for clk_period;`
371			`x <= x"df4a";`
372
373			`m <= x"b7a0";`
374			`r_c <= x"7c8d";`
375			`wait for clk_period;`
376			`x <= x"8e40";`
377
378			`m <= x"146e";`
379			`r_c <= x"64d9";`
380			`wait for clk_period;`
381			`x <= x"6af9";`
382
383			`m <= x"4776";`
384			`r_c <= x"c7f6";`
385			`wait for clk_period;`
386			`x <= x"4e63";`
387
388			`m <= x"ec50";`
389			`r_c <= x"fba0";`
390			`wait for clk_period;`
391			`x <= x"9600";`
392
393			`m <= x"c07c";`
394			`r_c <= x"e3e0";`
395			`wait for clk_period;`
396			`x <= x"68f4";`
397
398			`m <= x"e698";`
399			`r_c <= x"b567";`
400			`wait for clk_period;`
401			`x <= x"5a12";`
402
403			`m <= x"d85f";`
404			`r_c <= x"3172";`
405			`wait for clk_period;`
406			`x <= x"d62e";`
407
408			`m <= x"729c";`
409			`r_c <= x"111a";`
410			`wait for clk_period;`
411			`x <= x"8fc1";`
412
413			`m <= x"19b6";`
414			`r_c <= x"1971";`
415			`wait for clk_period;`
416			`x <= x"d2cd";`
417
418			`m <= x"05d3";`
419			`r_c <= x"9f9b";`
420			`wait for clk_period;`
421	11	jcastillo	`x <= x"c6e4";`
422
423			`m <= x"cacd";`
424	3	jcastillo	`r_c <= x"b574";`
425			`wait for clk_period;`
426	11	jcastillo	`x <= x"4a36";`
427
428			`m <= x"e16f";`
429	3	jcastillo	`r_c <= x"4a50";`
430			`wait for clk_period;`
431	11	jcastillo	`x <= x"f6df";`
432
433			`m <= x"f67b";`
434	3	jcastillo	`r_c <= x"6d56";`
435			`wait for clk_period;`
436	11	jcastillo	`x <= x"061c";`
437
438			`m <= x"7066";`
439	3	jcastillo	`r_c <= x"bdc6";`
440			`wait for clk_period;`
441	11	jcastillo	`x <= x"06c8";`
442
443			`m <= x"08de";`
444			`r_c <= x"0400";`
445	3	jcastillo	`wait for clk_period;`
446	11	jcastillo	`valid_in <= '0';`
447
448			`wait;`
449			`end process;`
450
451			`end;`

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[/] [rsa_512/] [trunk/] [bench/] [test_512.vhd] - Blame information for rev 11