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///////////////////////////////////////////////////////////////////////////
//
// Filename:    rtcclock.v
//              
// Project:     A Wishbone Controlled Real--time Clock Core
//
// Purpose:     Implement a real time clock, including alarm, count--down
//              timer, stopwatch, variable time frequency, and more.
//
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
module  rtcclock(i_clk,
                // Wishbone interface
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                //      o_wb_ack, o_wb_stb, o_wb_data, // no reads here
                // // Button inputs
                // i_btn,
                // Output registers
                o_data, // multiplexed based upon i_wb_addr
                // Output controls
                o_sseg, o_led, o_interrupt,
                //
                o_ppd,
                // Time setting hack(s)
                i_hack);
        input   i_clk;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input   [2:0]    i_wb_addr;
        input   [31:0]   i_wb_data;
        // input                i_btn;
        output  reg     [31:0]   o_data;
        output  reg     [31:0]   o_sseg;
        output  wire    [15:0]   o_led;
        output  wire            o_interrupt, o_ppd;
        input                   i_hack;
 
        reg     [31:0]   clock, stopwatch, ckspeed;
        reg     [25:0]   timer;
 
        wire    ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
        assign  ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
        assign  tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
        assign  sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
        assign  al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
        assign  sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
 
        reg     [39:0]   ck_counter;
        reg             ck_carry;
        always @(posedge i_clk)
                { ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
 
        wire            ck_pps;
        reg             ck_prepps, ck_ppm, ck_pph, ck_ppd;
        reg     [7:0]    ck_sub;
        initial clock = 32'h00000000;
        assign  ck_pps = (ck_carry)&&(ck_prepps);
        always @(posedge i_clk)
        begin
                if (ck_carry)
                        ck_sub <= ck_sub + 1;
                ck_prepps <= (ck_sub == 8'hff);
 
                if (ck_pps)
                begin // advance the seconds
                        if (clock[3:0] >= 4'h9)
                                clock[3:0] <= 4'h0;
                        else
                                clock[3:0] <= clock[3:0] + 4'h1;
                        if (clock[7:0] >= 8'h59)
                                clock[7:4] <= 4'h0;
                        else if (clock[3:0] >= 4'h9)
                                clock[7:4] <= clock[7:4] + 4'h1;
                end
                ck_ppm <= (clock[7:0] == 8'h59);
 
                if ((ck_pps)&&(ck_ppm))
                begin // advance the minutes
                        if (clock[11:8] >= 4'h9)
                                clock[11:8] <= 4'h0;
                        else
                                clock[11:8] <= clock[11:8] + 4'h1;
                        if (clock[15:8] >= 8'h59)
                                clock[15:12] <= 4'h0;
                        else if (clock[11:8] >= 4'h9)
                                clock[15:12] <= clock[15:12] + 4'h1;
                end
                ck_pph <= (clock[15:0] == 16'h5959);
 
                if ((ck_pps)&&(ck_pph))
                begin // advance the hours
                        if (clock[21:16] >= 6'h23)
                        begin
                                clock[19:16] <= 4'h0;
                                clock[21:20] <= 2'h0;
                        end else if (clock[19:16] >= 4'h9)
                        begin
                                clock[19:16] <= 4'h0;
                                clock[21:20] <= clock[21:20] + 2'h1;
                        end else begin
                                clock[19:16] <= clock[19:16] + 4'h1;
                        end
                end
                ck_ppd <= (clock[21:0] == 22'h235959);
 
 
                if ((ck_sel)&&(i_wb_we))
                begin
                        if (8'hff != i_wb_data[7:0])
                        begin
                                clock[7:0] <= i_wb_data[7:0];
                                ck_ppm <= (i_wb_data[7:0] == 8'h59);
                        end
                        if (8'hff != i_wb_data[15:8])
                        begin
                                clock[15:8] <= i_wb_data[15:8];
                                ck_pph <= (i_wb_data[15:8] == 8'h59);
                        end
                        if (6'h3f != i_wb_data[21:16])
                                clock[21:16] <= i_wb_data[21:16];
                        clock[31:22] <= i_wb_data[31:22];
                        if (8'h00 == i_wb_data[7:0])
                                ck_sub <= 8'h00;
                end
        end
 
        // Clock updates take several clocks, so let's make sure we
        // are only looking at a valid clock value before testing it.
        reg     [21:0]           ck_last_clock;
        always @(posedge i_clk)
                ck_last_clock <= clock[21:0];
 
 
        reg     tm_pps, tm_ppm, tm_int;
        wire    tm_stopped, tm_running, tm_alarm;
        assign  tm_stopped = ~timer[24];
        assign  tm_running =  timer[24];
        assign  tm_alarm   =  timer[25];
        reg     [23:0]           tm_start;
        reg     [7:0]            tm_sub;
        initial tm_start = 24'h00;
        initial timer    = 26'h00;
        initial tm_int   = 1'b0;
        initial tm_pps   = 1'b0;
        always @(posedge i_clk)
        begin
                if (ck_carry)
                begin
                        tm_sub <= tm_sub + 1;
                        tm_pps <= (tm_sub == 8'hff);
                end else
                        tm_pps <= 1'b0;
 
                if ((~tm_alarm)&&(tm_running)&&(tm_pps))
                begin // If we are running ...
                        timer[25] <= 1'b0;
                        if (timer[23:0] == 24'h00)
                                timer[25] <= 1'b1;
                        else if (timer[3:0] != 4'h0)
                                timer[3:0] <= timer[3:0]-4'h1;
                        else begin // last digit is a zero
                                timer[3:0] <= 4'h9;
                                if (timer[7:4] != 4'h0)
                                        timer[7:4] <= timer[7:4]-4'h1;
                                else begin // last two digits are zero
                                        timer[7:4] <= 4'h5;
                                        if (timer[11:8] != 4'h0)
                                                timer[11:8] <= timer[11:8]-4'h1;
                                        else begin // last three digits are zero
                                                timer[11:8] <= 4'h9;
                                                if (timer[15:12] != 4'h0)
                                                        timer[15:12] <= timer[15:12]-4'h1;
                                                else begin
                                                        timer[15:12] <= 4'h5;
                                                        if (timer[19:16] != 4'h0)
                                                                timer[19:16] <= timer[19:16]-4'h1;
                                                        else begin
                                                        //
                                                                timer[19:16] <= 4'h9;
                                                                timer[23:20] <= timer[23:20]-4'h1;
                                                        end
                                                end
                                        end
                                end
                        end
                end
 
                if((~tm_alarm)&&(tm_running))
                begin
                        timer[25] <= (timer[23:0] == 24'h00);
                        tm_int <= (timer[23:0] == 24'h00);
                end else tm_int <= 1'b0;
                if (tm_alarm)
                        timer[24] <= 1'b0;
 
                if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running
                        // Only allowed to stop the timer, nothing more
                        timer[24] <= i_wb_data[24];
                else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off
                begin
                        timer[24] <= i_wb_data[24];
                        if ((timer[24])||(i_wb_data[24]))
                                timer[25] <= 1'b0;
                        if (i_wb_data[23:0] != 24'h0000)
                        begin
                                timer[23:0] <= i_wb_data[23:0];
                                tm_start <= i_wb_data[23:0];
                                tm_sub <= 8'h00;
                        end else if (timer[23:0] == 24'h00)
                        begin // Resetting timer to last valid timer start val
                                timer[23:0] <= tm_start;
                                tm_sub <= 8'h00;
                        end
                        // Any write clears the alarm
                        timer[25] <= 1'b0;
                end
        end
 
        //
        // Stopwatch functionality
        //
        // Setting bit '0' starts the stop watch, clearing it stops it.
        // Writing to the register with bit '1' high will clear the stopwatch,
        // and return it to zero provided that the stopwatch is stopped either
        // before or after the write.  Hence, writing a '2' to the device
        // will always stop and clear it, whereas writing a '3' to the device
        // will only clear it if it was already stopped.
        reg             sw_pps, sw_ppm, sw_pph;
        reg     [7:0]    sw_sub;
        wire    sw_running;
        assign  sw_running = stopwatch[0];
        initial stopwatch = 32'h00000;
        always @(posedge i_clk)
        begin
                sw_pps <= 1'b0;
                if (sw_running)
                begin
                        if (ck_carry)
                        begin
                                sw_sub <= sw_sub + 1;
                                sw_pps <= (sw_sub == 8'hff);
                        end
                end
 
                stopwatch[7:1] <= sw_sub[7:1];
 
                if (sw_pps)
                begin // Second hand
                        if (stopwatch[11:8] >= 4'h9)
                                stopwatch[11:8] <= 4'h0;
                        else
                                stopwatch[11:8] <= stopwatch[11:8] + 4'h1;
 
                        if (stopwatch[15:8] >= 8'h59)
                                stopwatch[15:12] <= 4'h0;
                        else if (stopwatch[11:8] >= 4'h9)
                                stopwatch[15:12] <= stopwatch[15:12] + 4'h1;
                        sw_ppm <= (stopwatch[15:8] == 8'h59);
                end else sw_ppm <= 1'b0;
 
                if (sw_ppm)
                begin // Minutes
                        if (stopwatch[19:16] >= 4'h9)
                                stopwatch[19:16] <= 4'h0;
                        else
                                stopwatch[19:16] <= stopwatch[19:16]+4'h1;
 
                        if (stopwatch[23:16] >= 8'h59)
                                stopwatch[23:20] <= 4'h0;
                        else if (stopwatch[19:16] >= 4'h9)
                                stopwatch[23:20] <= stopwatch[23:20]+4'h1;
                        sw_pph <= (stopwatch[23:16] == 8'h59);
                end else sw_pph <= 1'b0;
 
                if (sw_pph)
                begin // And hours
                        if (stopwatch[27:24] >= 4'h9)
                                stopwatch[27:24] <= 4'h0;
                        else
                                stopwatch[27:24] <= stopwatch[27:24]+4'h1;
 
                        if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))
                                stopwatch[31:28] <= stopwatch[27:24]+4'h1;
                end
 
                if ((sw_sel)&&(i_wb_we))
                begin
                        stopwatch[0] <= i_wb_data[0];
                        if((i_wb_data[1])&&((~stopwatch[0])||(~i_wb_data[0])))
                        begin
                                stopwatch[31:1] <= 31'h00;
                                sw_sub <= 8'h00;
                                sw_pps <= 1'b0;
                                sw_ppm <= 1'b0;
                                sw_pph <= 1'b0;
                        end
                end
        end
 
        //
        // The alarm code
        //
        // Set the alarm register to the time you wish the board to "alarm".
        // The "alarm" will take place once per day at that time.  At that
        // time, the RTC code will generate a clock interrupt, and the CPU/host
        // can come and see that the alarm tripped.
        //
        // 
        reg     [21:0]           alarm_time;
        reg                     al_int,         // The alarm interrupt line
                                al_enabled,     // Whether the alarm is enabled
                                al_tripped;     // Whether the alarm has tripped
        initial al_enabled= 1'b0;
        initial al_tripped= 1'b0;
        always @(posedge i_clk)
        begin
                if ((al_sel)&&(i_wb_we))
                begin
                        // Only adjust the alarm hours if the requested hours
                        // are valid.  This allows writes to the register,
                        // without a prior read, to leave these configuration
                        // bits alone.
                        if (i_wb_data[21:16] != 6'h3f)
                                alarm_time[21:16] <= i_wb_data[21:16];
                        // Here's the same thing for the minutes: only adjust
                        // the alarm minutes if the new bits are not all 1's. 
                        if (i_wb_data[15:8] != 8'hff)
                                alarm_time[15:8] <= i_wb_data[15:8];
                        // Here's the same thing for the seconds: only adjust
                        // the alarm minutes if the new bits are not all 1's. 
                        if (i_wb_data[7:0] != 8'hff)
                                alarm_time[7:0] <= i_wb_data[7:0];
                        al_enabled <= i_wb_data[24];
                        // Reset the alarm if a '1' is written to the tripped
                        // register, or if the alarm is disabled.
                        if ((i_wb_data[25])||(~i_wb_data[24]))
                                al_tripped <= 1'b0;
                end
 
                al_int <= 1'b0;
                if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)
                        &&(al_enabled))
                begin
                        al_tripped <= 1'b1;
                        al_int <= 1'b1;
                end
        end
 
        //
        // The ckspeed register is equal to 2^48 divded by the number of
        // clock ticks you expect per second.  Adjust high for a slower
        // clock, lower for a faster clock.  In this fashion, a single
        // real time clock RTL file can handle tracking the clock in any
        // device.  Further, because this is only the lower 32 bits of a 
        // 48 bit counter per seconds, the clock jitter is kept below
        // 1 part in 65 thousand.
        //
        initial ckspeed = 32'd2814750; // 2af31e = 2^48 / 100e6 MHz
        // In the case of verilator, comment the above and uncomment the line
        // below.  The clock constant below is "close" to simulation time,
        // meaning that my verilator simulation is running about 300x slower
        // than board time.
        // initial      ckspeed = 32'd786432000;
        always @(posedge i_clk)
                if ((sp_sel)&&(i_wb_we))
                        ckspeed <= i_wb_data;
 
        // 
        // If you want very fine precision control over your clock, you need
        // to be able to transfer time from one location to another.  This
        // is the beginning of that means: by setting a wire, i_hack, high
        // on a particular input, you can then read (later) what the clock
        // time was on that input.
        //
        // What's missing from this high precision adjustment mechanism is a
        // means of actually adjusting this time based upon the time 
        // difference you measure here between the hack time and some time
        // on another clock, but we'll get there.
        //
        reg             r_hack_carry;
        reg     [29:0]   hack_time;
        reg     [39:0]   hack_counter;
        initial hack_time    = 30'h0000;
        initial hack_counter = 40'h0000;
        always @(posedge i_clk)
                if (i_hack)
                begin
                        hack_time <= { clock[21:0], ck_sub };
                        hack_counter <= ck_counter;
                        r_hack_carry <= ck_carry;
                        // if ck_carry is set, the clock register is in the
                        // middle of a two clock update.  In that case ....
                end else if (r_hack_carry)
                begin // update again on the next clock to get the correct
                        // hack time.
                        hack_time <= { clock[21:0], ck_sub };
                        r_hack_carry <= 1'b0;
                end
 
        reg     [15:0]   h_sseg;
        reg     [3:0]    dmask;
        always @(posedge i_clk)
                case(clock[27:24])
                4'h1: begin h_sseg <= timer[15:0];
                        if (tm_alarm) dmask <= 4'hf;
                        else begin
                                dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]
                                dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]
                                dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]
                                dmask[0] <= 1'b1; // Always on
                        end end
                4'h2: begin h_sseg <= stopwatch[19:4];
                                dmask[3] <= (12'h00  != stopwatch[27:16]);
                                dmask[2] <= (16'h000 != stopwatch[27:12]);
                                dmask[1] <= 1'b1; // Always on, stopwatch[11:8]
                                dmask[0] <= 1'b1; // Always on, stopwatch[7:4]
                        end
                4'h3: begin h_sseg <= ck_last_clock[15:0];
                                dmask[3:0] <= 4'hf;
                        end
                default: begin // 4'h0
                        h_sseg <= { 2'b00, ck_last_clock[21:8] };
                        dmask[2:0] <= 3'hf;
                        dmask[3] <= (2'b00 != ck_last_clock[21:20]);
                        end
                endcase
 
        wire    [31:0]   w_sseg;
        assign  w_sseg[ 0] =  (~ck_sub[7]);
        assign  w_sseg[ 8] =  (clock[27:24] == 4'h2);
        assign  w_sseg[16] = ((clock[27:24] == 4'h0)&&(~ck_sub[7]))||(clock[27:24] == 4'h3);
        assign  w_sseg[24] = 1'b0;
        hexmap  ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);
        hexmap  hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);
        hexmap  hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);
        hexmap  hd(i_clk, h_sseg[15:12], w_sseg[31:25]);
 
        always @(posedge i_clk)
                if ((tm_alarm || al_tripped)&&(ck_sub[7]))
                        o_sseg <= 32'h0000;
                else
                        o_sseg <= {
                                (dmask[3])?w_sseg[31:24]:8'h00,
                                (dmask[2])?w_sseg[23:16]:8'h00,
                                (dmask[1])?w_sseg[15: 8]:8'h00,
                                (dmask[0])?w_sseg[ 7: 0]:8'h00 };
 
        reg     [17:0]   ledreg;
        always @(posedge i_clk)
                if ((ck_pps)&&(ck_ppm))
                        ledreg <= 18'h00;
                else if (ck_carry)
                        ledreg <= ledreg + 18'h11;
        assign  o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}:
                                { ledreg[17:10],
                                ledreg[10], ledreg[11], ledreg[12], ledreg[13],
                                ledreg[14], ledreg[15], ledreg[16], ledreg[17] };
 
        assign  o_interrupt = tm_int || al_int;
 
        // A once-per day strobe, on the last second of the day so that the
        // the next clock is the first clock of the day.  This is useful for
        // connecting this module to a year/month/date date/calendar module.
        assign  o_ppd = (ck_ppd)&&(ck_pps);
 
        always @(posedge i_clk)
                case(i_wb_addr[2:0])
                3'b000: o_data <= { clock[31:22], ck_last_clock };
                3'b001: o_data <= { 6'h00, timer };
                3'b010: o_data <= stopwatch;
                3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
                3'b100: o_data <= ckspeed;
                3'b101: o_data <= { 2'b00, hack_time };
                3'b110: o_data <= hack_counter[39:8];
                3'b111: o_data <= { hack_counter[7:0], 24'h00 };
                endcase
 
endmodule

Line No.	Rev	Author	Line
1	2	dgisselq	`///////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: rtcclock.v`
4			`//`
5			`// Project: A Wishbone Controlled Real--time Clock Core`
6			`//`
7			`// Purpose: Implement a real time clock, including alarm, count--down`
8			`// timer, stopwatch, variable time frequency, and more.`
9			`//`
10			`//`
11			`// Creator: Dan Gisselquist, Ph.D.`
12			`// Gisselquist Tecnology, LLC`
13			`//`
14			`///////////////////////////////////////////////////////////////////////////`
15			`//`
16			`// Copyright (C) 2015, Gisselquist Technology, LLC`
17			`//`
18			`// This program is free software (firmware): you can redistribute it and/or`
19			`// modify it under the terms of the GNU General Public License as published`
20			`// by the Free Software Foundation, either version 3 of the License, or (at`
21			`// your option) any later version.`
22			`//`
23			`// This program is distributed in the hope that it will be useful, but WITHOUT`
24			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
25			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
26			`// for more details.`
27			`//`
28			`// You should have received a copy of the GNU General Public License along`
29			`// with this program. (It's in the $(ROOT)/doc directory. Run make with no`
30			`// target there if the PDF file isn't present.) If not, see`
31			`// <http://www.gnu.org/licenses/> for a copy.`
32			`//`
33			`// License: GPL, v3, as defined and found on www.gnu.org,`
34			`// http://www.gnu.org/licenses/gpl.html`
35			`//`
36			`//`
37			`///////////////////////////////////////////////////////////////////////////`
38			`module rtcclock(i_clk,`
39			`// Wishbone interface`
40			`i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,`
41			`// o_wb_ack, o_wb_stb, o_wb_data, // no reads here`
42			`// // Button inputs`
43			`// i_btn,`
44			`// Output registers`
45			`o_data, // multiplexed based upon i_wb_addr`
46			`// Output controls`
47			`o_sseg, o_led, o_interrupt,`
48	5	dgisselq	`//`
49			`o_ppd,`
50	2	dgisselq	`// Time setting hack(s)`
51			`i_hack);`
52			`input i_clk;`
53			`input i_wb_cyc, i_wb_stb, i_wb_we;`
54			`input [2:0] i_wb_addr;`
55			`input [31:0] i_wb_data;`
56			`// input i_btn;`
57			`output reg [31:0] o_data;`
58			`output reg [31:0] o_sseg;`
59			`output wire [15:0] o_led;`
60	5	dgisselq	`output wire o_interrupt, o_ppd;`
61	2	dgisselq	`input i_hack;`
62
63			`reg [31:0] clock, stopwatch, ckspeed;`
64	3	dgisselq	`reg [25:0] timer;`
65	2	dgisselq
66			`wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;`
67			`assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));`
68			`assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));`
69			`assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));`
70			`assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));`
71			`assign sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));`
72
73			`reg [39:0] ck_counter;`
74			`reg ck_carry;`
75			`always @(posedge i_clk)`
76			`{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };`
77
78			`wire ck_pps;`
79			`reg ck_prepps, ck_ppm, ck_pph, ck_ppd;`
80			`reg [7:0] ck_sub;`
81			`initial clock = 32'h00000000;`
82			`assign ck_pps = (ck_carry)&&(ck_prepps);`
83			`always @(posedge i_clk)`
84			`begin`
85			`if (ck_carry)`
86			`ck_sub <= ck_sub + 1;`
87			`ck_prepps <= (ck_sub == 8'hff);`
88
89			`if (ck_pps)`
90			`begin // advance the seconds`
91			`if (clock[3:0] >= 4'h9)`
92			`clock[3:0] <= 4'h0;`
93			`else`
94			`clock[3:0] <= clock[3:0] + 4'h1;`
95			`if (clock[7:0] >= 8'h59)`
96			`clock[7:4] <= 4'h0;`
97			`else if (clock[3:0] >= 4'h9)`
98			`clock[7:4] <= clock[7:4] + 4'h1;`
99			`end`
100			`ck_ppm <= (clock[7:0] == 8'h59);`
101
102			`if ((ck_pps)&&(ck_ppm))`
103			`begin // advance the minutes`
104			`if (clock[11:8] >= 4'h9)`
105			`clock[11:8] <= 4'h0;`
106			`else`
107			`clock[11:8] <= clock[11:8] + 4'h1;`
108			`if (clock[15:8] >= 8'h59)`
109			`clock[15:12] <= 4'h0;`
110			`else if (clock[11:8] >= 4'h9)`
111			`clock[15:12] <= clock[15:12] + 4'h1;`
112			`end`
113			`ck_pph <= (clock[15:0] == 16'h5959);`
114
115			`if ((ck_pps)&&(ck_pph))`
116			`begin // advance the hours`
117			`if (clock[21:16] >= 6'h23)`
118			`begin`
119			`clock[19:16] <= 4'h0;`
120			`clock[21:20] <= 2'h0;`
121			`end else if (clock[19:16] >= 4'h9)`
122			`begin`
123			`clock[19:16] <= 4'h0;`
124			`clock[21:20] <= clock[21:20] + 2'h1;`
125			`end else begin`
126			`clock[19:16] <= clock[19:16] + 4'h1;`
127			`end`
128			`end`
129	5	dgisselq	`ck_ppd <= (clock[21:0] == 22'h235959);`
130	2	dgisselq
131	5	dgisselq
132	2	dgisselq	`if ((ck_sel)&&(i_wb_we))`
133			`begin`
134			`if (8'hff != i_wb_data[7:0])`
135			`begin`
136			`clock[7:0] <= i_wb_data[7:0];`
137			`ck_ppm <= (i_wb_data[7:0] == 8'h59);`
138			`end`
139			`if (8'hff != i_wb_data[15:8])`
140			`begin`
141			`clock[15:8] <= i_wb_data[15:8];`
142			`ck_pph <= (i_wb_data[15:8] == 8'h59);`
143			`end`
144			`if (6'h3f != i_wb_data[21:16])`
145			`clock[21:16] <= i_wb_data[21:16];`
146			`clock[31:22] <= i_wb_data[31:22];`
147			`if (8'h00 == i_wb_data[7:0])`
148			`ck_sub <= 8'h00;`
149			`end`
150			`end`
151
152			`// Clock updates take several clocks, so let's make sure we`
153			`// are only looking at a valid clock value before testing it.`
154			`reg [21:0] ck_last_clock;`
155			`always @(posedge i_clk)`
156			`ck_last_clock <= clock[21:0];`
157
158
159			`reg tm_pps, tm_ppm, tm_int;`
160			`wire tm_stopped, tm_running, tm_alarm;`
161			`assign tm_stopped = ~timer[24];`
162			`assign tm_running = timer[24];`
163			`assign tm_alarm = timer[25];`
164			`reg [23:0] tm_start;`
165			`reg [7:0] tm_sub;`
166	4	dgisselq	`initial tm_start = 24'h00;`
167			`initial timer = 26'h00;`
168	2	dgisselq	`initial tm_int = 1'b0;`
169			`initial tm_pps = 1'b0;`
170			`always @(posedge i_clk)`
171			`begin`
172			`if (ck_carry)`
173			`begin`
174			`tm_sub <= tm_sub + 1;`
175			`tm_pps <= (tm_sub == 8'hff);`
176			`end else`
177			`tm_pps <= 1'b0;`
178
179			`if ((~tm_alarm)&&(tm_running)&&(tm_pps))`
180			`begin // If we are running ...`
181			`timer[25] <= 1'b0;`
182			`if (timer[23:0] == 24'h00)`
183			`timer[25] <= 1'b1;`
184			`else if (timer[3:0] != 4'h0)`
185			`timer[3:0] <= timer[3:0]-4'h1;`
186			`else begin // last digit is a zero`
187			`timer[3:0] <= 4'h9;`
188			`if (timer[7:4] != 4'h0)`
189			`timer[7:4] <= timer[7:4]-4'h1;`
190			`else begin // last two digits are zero`
191			`timer[7:4] <= 4'h5;`
192			`if (timer[11:8] != 4'h0)`
193			`timer[11:8] <= timer[11:8]-4'h1;`
194			`else begin // last three digits are zero`
195			`timer[11:8] <= 4'h9;`
196			`if (timer[15:12] != 4'h0)`
197			`timer[15:12] <= timer[15:12]-4'h1;`
198			`else begin`
199			`timer[15:12] <= 4'h5;`
200			`if (timer[19:16] != 4'h0)`
201			`timer[19:16] <= timer[19:16]-4'h1;`
202			`else begin`
203			`//`
204			`timer[19:16] <= 4'h9;`
205			`timer[23:20] <= timer[23:20]-4'h1;`
206			`end`
207			`end`
208			`end`
209			`end`
210			`end`
211			`end`
212
213			`if((~tm_alarm)&&(tm_running))`
214			`begin`
215			`timer[25] <= (timer[23:0] == 24'h00);`
216			`tm_int <= (timer[23:0] == 24'h00);`
217			`end else tm_int <= 1'b0;`
218			`if (tm_alarm)`
219			`timer[24] <= 1'b0;`
220
221			`if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running`
222			`// Only allowed to stop the timer, nothing more`
223			`timer[24] <= i_wb_data[24];`
224			`else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off`
225			`begin`
226			`timer[24] <= i_wb_data[24];`
227			`if ((timer[24])\|\|(i_wb_data[24]))`
228			`timer[25] <= 1'b0;`
229			`if (i_wb_data[23:0] != 24'h0000)`
230			`begin`
231			`timer[23:0] <= i_wb_data[23:0];`
232			`tm_start <= i_wb_data[23:0];`
233			`tm_sub <= 8'h00;`
234			`end else if (timer[23:0] == 24'h00)`
235			`begin // Resetting timer to last valid timer start val`
236			`timer[23:0] <= tm_start;`
237			`tm_sub <= 8'h00;`
238			`end`
239			`// Any write clears the alarm`
240			`timer[25] <= 1'b0;`
241			`end`
242			`end`
243
244			`//`
245			`// Stopwatch functionality`
246			`//`
247			`// Setting bit '0' starts the stop watch, clearing it stops it.`
248			`// Writing to the register with bit '1' high will clear the stopwatch,`
249			`// and return it to zero provided that the stopwatch is stopped either`
250			`// before or after the write. Hence, writing a '2' to the device`
251			`// will always stop and clear it, whereas writing a '3' to the device`
252			`// will only clear it if it was already stopped.`
253			`reg sw_pps, sw_ppm, sw_pph;`
254			`reg [7:0] sw_sub;`
255			`wire sw_running;`
256			`assign sw_running = stopwatch[0];`
257	4	dgisselq	`initial stopwatch = 32'h00000;`
258	2	dgisselq	`always @(posedge i_clk)`
259			`begin`
260			`sw_pps <= 1'b0;`
261			`if (sw_running)`
262			`begin`
263			`if (ck_carry)`
264			`begin`
265			`sw_sub <= sw_sub + 1;`
266			`sw_pps <= (sw_sub == 8'hff);`
267			`end`
268			`end`
269
270			`stopwatch[7:1] <= sw_sub[7:1];`
271
272			`if (sw_pps)`
273			`begin // Second hand`
274			`if (stopwatch[11:8] >= 4'h9)`
275			`stopwatch[11:8] <= 4'h0;`
276			`else`
277			`stopwatch[11:8] <= stopwatch[11:8] + 4'h1;`
278
279			`if (stopwatch[15:8] >= 8'h59)`
280			`stopwatch[15:12] <= 4'h0;`
281			`else if (stopwatch[11:8] >= 4'h9)`
282			`stopwatch[15:12] <= stopwatch[15:12] + 4'h1;`
283			`sw_ppm <= (stopwatch[15:8] == 8'h59);`
284			`end else sw_ppm <= 1'b0;`
285
286			`if (sw_ppm)`
287			`begin // Minutes`
288			`if (stopwatch[19:16] >= 4'h9)`
289			`stopwatch[19:16] <= 4'h0;`
290			`else`
291			`stopwatch[19:16] <= stopwatch[19:16]+4'h1;`
292
293			`if (stopwatch[23:16] >= 8'h59)`
294			`stopwatch[23:20] <= 4'h0;`
295			`else if (stopwatch[19:16] >= 4'h9)`
296			`stopwatch[23:20] <= stopwatch[23:20]+4'h1;`
297			`sw_pph <= (stopwatch[23:16] == 8'h59);`
298			`end else sw_pph <= 1'b0;`
299
300			`if (sw_pph)`
301			`begin // And hours`
302			`if (stopwatch[27:24] >= 4'h9)`
303			`stopwatch[27:24] <= 4'h0;`
304			`else`
305			`stopwatch[27:24] <= stopwatch[27:24]+4'h1;`
306
307			`if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))`
308			`stopwatch[31:28] <= stopwatch[27:24]+4'h1;`
309			`end`
310
311			`if ((sw_sel)&&(i_wb_we))`
312			`begin`
313			`stopwatch[0] <= i_wb_data[0];`
314			`if((i_wb_data[1])&&((~stopwatch[0])\|\|(~i_wb_data[0])))`
315			`begin`
316			`stopwatch[31:1] <= 31'h00;`
317			`sw_sub <= 8'h00;`
318			`sw_pps <= 1'b0;`
319			`sw_ppm <= 1'b0;`
320			`sw_pph <= 1'b0;`
321			`end`
322			`end`
323			`end`
324
325			`//`
326			`// The alarm code`
327			`//`
328			`// Set the alarm register to the time you wish the board to "alarm".`
329			`// The "alarm" will take place once per day at that time. At that`
330			`// time, the RTC code will generate a clock interrupt, and the CPU/host`
331			`// can come and see that the alarm tripped.`
332			`//`
333			`//`
334			`reg [21:0] alarm_time;`
335			`reg al_int, // The alarm interrupt line`
336			`al_enabled, // Whether the alarm is enabled`
337			`al_tripped; // Whether the alarm has tripped`
338			`initial al_enabled= 1'b0;`
339			`initial al_tripped= 1'b0;`
340			`always @(posedge i_clk)`
341			`begin`
342			`if ((al_sel)&&(i_wb_we))`
343			`begin`
344			`// Only adjust the alarm hours if the requested hours`
345			`// are valid. This allows writes to the register,`
346			`// without a prior read, to leave these configuration`
347			`// bits alone.`
348			`if (i_wb_data[21:16] != 6'h3f)`
349			`alarm_time[21:16] <= i_wb_data[21:16];`
350			`// Here's the same thing for the minutes: only adjust`
351			`// the alarm minutes if the new bits are not all 1's.`
352			`if (i_wb_data[15:8] != 8'hff)`
353			`alarm_time[15:8] <= i_wb_data[15:8];`
354			`// Here's the same thing for the seconds: only adjust`
355			`// the alarm minutes if the new bits are not all 1's.`
356			`if (i_wb_data[7:0] != 8'hff)`
357			`alarm_time[7:0] <= i_wb_data[7:0];`
358			`al_enabled <= i_wb_data[24];`
359			`// Reset the alarm if a '1' is written to the tripped`
360			`// register, or if the alarm is disabled.`
361			`if ((i_wb_data[25])\|\|(~i_wb_data[24]))`
362			`al_tripped <= 1'b0;`
363			`end`
364
365			`al_int <= 1'b0;`
366			`if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)`
367			`&&(al_enabled))`
368			`begin`
369			`al_tripped <= 1'b1;`
370			`al_int <= 1'b1;`
371			`end`
372			`end`
373
374			`//`
375			`// The ckspeed register is equal to 2^48 divded by the number of`
376			`// clock ticks you expect per second. Adjust high for a slower`
377			`// clock, lower for a faster clock. In this fashion, a single`
378			`// real time clock RTL file can handle tracking the clock in any`
379			`// device. Further, because this is only the lower 32 bits of a`
380			`// 48 bit counter per seconds, the clock jitter is kept below`
381			`// 1 part in 65 thousand.`
382			`//`
383			`initial ckspeed = 32'd2814750; // 2af31e = 2^48 / 100e6 MHz`
384			`// In the case of verilator, comment the above and uncomment the line`
385			`// below. The clock constant below is "close" to simulation time,`
386			`// meaning that my verilator simulation is running about 300x slower`
387			`// than board time.`
388			`// initial ckspeed = 32'd786432000;`
389			`always @(posedge i_clk)`
390			`if ((sp_sel)&&(i_wb_we))`
391			`ckspeed <= i_wb_data;`
392
393			`//`
394			`// If you want very fine precision control over your clock, you need`
395			`// to be able to transfer time from one location to another. This`
396			`// is the beginning of that means: by setting a wire, i_hack, high`
397			`// on a particular input, you can then read (later) what the clock`
398			`// time was on that input.`
399			`//`
400			`// What's missing from this high precision adjustment mechanism is a`
401			`// means of actually adjusting this time based upon the time`
402			`// difference you measure here between the hack time and some time`
403			`// on another clock, but we'll get there.`
404			`//`
405			`reg r_hack_carry;`
406			`reg [29:0] hack_time;`
407			`reg [39:0] hack_counter;`
408	4	dgisselq	`initial hack_time = 30'h0000;`
409			`initial hack_counter = 40'h0000;`
410	2	dgisselq	`always @(posedge i_clk)`
411			`if (i_hack)`
412			`begin`
413			`hack_time <= { clock[21:0], ck_sub };`
414			`hack_counter <= ck_counter;`
415			`r_hack_carry <= ck_carry;`
416			`// if ck_carry is set, the clock register is in the`
417			`// middle of a two clock update. In that case ....`
418			`end else if (r_hack_carry)`
419			`begin // update again on the next clock to get the correct`
420			`// hack time.`
421			`hack_time <= { clock[21:0], ck_sub };`
422			`r_hack_carry <= 1'b0;`
423			`end`
424
425			`reg [15:0] h_sseg;`
426	4	dgisselq	`reg [3:0] dmask;`
427	2	dgisselq	`always @(posedge i_clk)`
428			`case(clock[27:24])`
429	4	dgisselq	`4'h1: begin h_sseg <= timer[15:0];`
430			`if (tm_alarm) dmask <= 4'hf;`
431			`else begin`
432			`dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]`
433			`dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]`
434			`dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]`
435			`dmask[0] <= 1'b1; // Always on`
436			`end end`
437			`4'h2: begin h_sseg <= stopwatch[19:4];`
438			`dmask[3] <= (12'h00 != stopwatch[27:16]);`
439			`dmask[2] <= (16'h000 != stopwatch[27:12]);`
440			`dmask[1] <= 1'b1; // Always on, stopwatch[11:8]`
441			`dmask[0] <= 1'b1; // Always on, stopwatch[7:4]`
442			`end`
443			`4'h3: begin h_sseg <= ck_last_clock[15:0];`
444			`dmask[3:0] <= 4'hf;`
445			`end`
446			`default: begin // 4'h0`
447			`h_sseg <= { 2'b00, ck_last_clock[21:8] };`
448			`dmask[2:0] <= 3'hf;`
449			`dmask[3] <= (2'b00 != ck_last_clock[21:20]);`
450			`end`
451	2	dgisselq	`endcase`
452
453			`wire [31:0] w_sseg;`
454	4	dgisselq	`assign w_sseg[ 0] = (~ck_sub[7]);`
455			`assign w_sseg[ 8] = (clock[27:24] == 4'h2);`
456			`assign w_sseg[16] = ((clock[27:24] == 4'h0)&&(~ck_sub[7]))\|\|(clock[27:24] == 4'h3);`
457	2	dgisselq	`assign w_sseg[24] = 1'b0;`
458			`hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);`
459			`hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);`
460			`hexmap hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);`
461			`hexmap hd(i_clk, h_sseg[15:12], w_sseg[31:25]);`
462
463			`always @(posedge i_clk)`
464			`if ((tm_alarm \|\| al_tripped)&&(ck_sub[7]))`
465			`o_sseg <= 32'h0000;`
466			`else`
467	4	dgisselq	`o_sseg <= {`
468			`(dmask[3])?w_sseg[31:24]:8'h00,`
469			`(dmask[2])?w_sseg[23:16]:8'h00,`
470			`(dmask[1])?w_sseg[15: 8]:8'h00,`
471			`(dmask[0])?w_sseg[ 7: 0]:8'h00 };`
472	2	dgisselq
473			`reg [17:0] ledreg;`
474			`always @(posedge i_clk)`
475			`if ((ck_pps)&&(ck_ppm))`
476			`ledreg <= 18'h00;`
477			`else if (ck_carry)`
478			`ledreg <= ledreg + 18'h11;`
479	4	dgisselq	`assign o_led = (tm_alarm\|\|al_tripped)?{ (16){ck_sub[7]}}:`
480			`{ ledreg[17:10],`
481			`ledreg[10], ledreg[11], ledreg[12], ledreg[13],`
482			`ledreg[14], ledreg[15], ledreg[16], ledreg[17] };`
483	2	dgisselq
484			`assign o_interrupt = tm_int \|\| al_int;`
485
486	5	dgisselq	`// A once-per day strobe, on the last second of the day so that the`
487			`// the next clock is the first clock of the day. This is useful for`
488			`// connecting this module to a year/month/date date/calendar module.`
489			`assign o_ppd = (ck_ppd)&&(ck_pps);`
490
491	2	dgisselq	`always @(posedge i_clk)`
492			`case(i_wb_addr[2:0])`
493			`3'b000: o_data <= { clock[31:22], ck_last_clock };`
494	4	dgisselq	`3'b001: o_data <= { 6'h00, timer };`
495	2	dgisselq	`3'b010: o_data <= stopwatch;`
496			`3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };`
497			`3'b100: o_data <= ckspeed;`
498			`3'b101: o_data <= { 2'b00, hack_time };`
499			`3'b110: o_data <= hack_counter[39:8];`
500			`3'b111: o_data <= { hack_counter[7:0], 24'h00 };`

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