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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// Byte mode decode/execute state
// ============================================================================
//
BYTE_DECODE:
        begin
                first_ifetch <= `TRUE;
                state <= BYTE_IFETCH;
                pc <= pc + pc_inc8;
                case(ir[7:0])
                `STP:   begin clk_en <= 1'b0; end
                `NAT:   begin em <= 1'b0; state <= IFETCH; end
                `NOP:   ;
                `CLC:   begin cf <= 1'b0; end
                `SEC:   begin cf <= 1'b1; end
                `CLV:   begin vf <= 1'b0; end
                `CLI:   begin im <= 1'b0; end
                `SEI:   begin im <= 1'b1; end
                `CLD:   begin df <= 1'b0; end
                `SED:   begin df <= 1'b1; end
                `WAI:   begin wai <= 1'b1; end
                `DEX:   begin res8 <= x[7:0] - 8'd1; end
                `INX:   begin res8 <= x[7:0] + 8'd1; end
                `DEY:   begin res8 <= y[7:0] - 8'd1; end
                `INY:   begin res8 <= y[7:0] + 8'd1; end
                `DEA:   begin res8 <= acc[7:0] - 8'd1; end
                `INA:   begin res8 <= acc[7:0] + 8'd1; end
                `TSX,`TSA:      begin res8 <= sp[7:0]; end
                `TXS,`TXA,`TXY: begin res8 <= x[7:0]; end
                `TAX,`TAY,`TAS: begin res8 <= acc[7:0]; end
                `TYA,`TYX:      begin res8 <= y[7:0]; end
                `ASL_ACC:       begin res8 <= {acc8,1'b0}; end
                `ROL_ACC:       begin res8 <= {acc8,cf}; end
                `LSR_ACC:       begin res8 <= {acc8[0],1'b0,acc8[7:1]}; end
                `ROR_ACC:       begin res8 <= {acc8[0],cf,acc8[7:1]}; end
                // Handle # mode
                `LDA_IMM,`LDX_IMM,`LDY_IMM:
                        begin
                                pc <= pc + 32'd2;
                                res8 <= ir[15:8];
                        end
                `ADC_IMM:
                        begin
                                res8 <= acc8 + ir[15:8] + {7'b0,cf};
                                b8 <= ir[15:8];         // for overflow calc
                        end
                `SBC_IMM:
                        begin
//                              res8 <= acc8 - ir[15:8] - ~cf;
                                res8 <= acc8 - ir[15:8] - {7'b0,~cf};
                                $display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);
                                b8 <= ir[15:8];         // for overflow calc
                        end
                `AND_IMM,`BIT_IMM:
                        begin
                                res8 <= acc8 & ir[15:8];
                                b8 <= ir[15:8]; // for bit flags
                        end
                `ORA_IMM:       res8 <= acc8 | ir[15:8];
                `EOR_IMM:       res8 <= acc8 ^ ir[15:8];
                `CMP_IMM:       res8 <= acc8 - ir[15:8];
                `CPX_IMM:       res8 <= x8 - ir[15:8];
                `CPY_IMM:       res8 <= y8 - ir[15:8];
                // Handle zp mode
                `LDX_ZP,`LDY_ZP,`LDA_ZP:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
                `BIT_ZP,`CPX_ZP,`CPY_ZP,
                `ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ZP:
                        begin
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                store_what <= `STW_ACC8;
                                state <= STORE1;
                        end
                `STX_ZP:
                        begin
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                store_what <= `STW_X8;
                                state <= STORE1;
                        end
                `STY_ZP:
                        begin
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                store_what <= `STW_Y8;
                                state <= STORE1;
                        end
                `STZ_ZP:
                        begin
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                store_what <= `STW_Z8;
                                state <= STORE1;
                        end
                // Handle zp,x mode
                `LDY_ZPX,`LDA_ZPX:
                        begin
                                radr <= zpx_address[31:2];
                                radr2LSB <= zpx_address[1:0];
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
                `BIT_ZPX,
                `ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
                        begin
                                radr <= zpx_address[31:2];
                                radr2LSB <= zpx_address[1:0];
                                load_what <= `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ZPX:
                        begin
                                wadr <= zpx_address[31:2];
                                wadr2LSB <= zpx_address[1:0];
                                store_what <= `STW_ACC8;
                                state <= STORE1;
                        end
                `STY_ZPX:
                        begin
                                wadr <= zpx_address[31:2];
                                wadr2LSB <= zpx_address[1:0];
                                store_what <= `STW_Y8;
                                state <= STORE1;
                        end
                `STZ_ZPX:
                        begin
                                wadr <= zpx_address[31:2];
                                wadr2LSB <= zpx_address[1:0];
                                store_what <= `STW_Z8;
                                state <= STORE1;
                        end
                // Handle zp,y
                `LDX_ZPY:
                        begin
                                radr <= zpy_address[31:2];
                                radr2LSB <= zpy_address[1:0];
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `STX_ZPY:
                        begin
                                wadr <= zpy_address[31:2];
                                wadr2LSB <= zpy_address[1:0];
                                store_what <= `STW_X8;
                                state <= STORE1;
                        end
                // Handle (zp,x)
                `ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
                        begin
                                radr <= zpx_address[31:2];
                                radr2LSB <= zpx_address[1:0];
                                load_what <= `IA_70;
                                store_what <= `STW_ACC8;
                                state <= LOAD_MAC1;
                        end
                // Handle (zp),y
                `ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                isIY <= `TRUE;
                                load_what <= `IA_70;
                                store_what <= `STW_ACC8;
                                state <= LOAD_MAC1;
                        end
                // Handle abs
                `LDA_ABS,`LDX_ABS,`LDY_ABS:
                        begin
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
                `ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
                `CPX_ABS,`CPY_ABS,
                `BIT_ABS:
                        begin
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                load_what <= `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ABS:
                        begin
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                store_what <= `STW_ACC8;
                                state <= STORE1;
                        end
                `STX_ABS:
                        begin
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                store_what <= `STW_X8;
                                state <= STORE1;
                        end
                `STY_ABS:
                        begin
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                store_what <= `STW_Y8;
                                state <= STORE1;
                        end
                `STZ_ABS:
                        begin
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                store_what <= `STW_Z8;
                                state <= STORE1;
                        end
                // Handle abs,x
                `ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
                `ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
                `LDY_ABSX:
                        begin
                                radr <= absx_address[31:2];
                                radr2LSB <= absx_address[1:0];
                                load_what <= `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ABSX:
                        begin
                                wadr <= absx_address[31:2];
                                wadr2LSB <= absx_address[1:0];
                                store_what <= `STW_ACC8;
                                state <= STORE1;
                        end
                `STZ_ABSX:
                        begin
                                wadr <= absx_address[31:2];
                                wadr2LSB <= absx_address[1:0];
                                store_what <= `STW_Z8;
                                state <= STORE1;
                        end
                // Handle abs,y
                `ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY,`LDA_ABSY,
                `LDX_ABSY:
                        begin
                                radr <= absy_address[31:2];
                                radr2LSB <= absy_address[1:0];
                                load_what <= `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ABSY:
                        begin
                                wadr <= absy_address[31:2];
                                wadr2LSB <= absy_address[1:0];
                                store_what <= `STW_ACC8;
                                state <= STORE1;
                        end
                // Handle (zp)
                `ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= `IA_70;
                                store_what <= `STW_ACC8;
                                state <= LOAD_MAC1;
                        end
                `BRK:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr <= {spage[31:8],sp[7:2]};
                                wadr2LSB <= sp[1:0];
                                sp <= sp_dec;
                                store_what <= `STW_PC3124;
                                state <= STORE1;
                                bf <= !hwi;
                        end
                `JMP:
                        begin
                                pc[15:0] <= abs_address[15:0];
                        end
                `JML:
                        begin
                                pc <= ir[39:8];
                        end
                `JMP_IND:
                        begin
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                load_what <= `PC_70;
                                state <= LOAD_MAC1;
                        end
                `JMP_INDX:
                        begin
                                radr <= absx_address[31:2];
                                radr2LSB <= absx_address[1:0];
                                load_what <= `PC_70;
                                state <= LOAD_MAC1;
                        end
                `JSR:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                store_what <= `STW_PC158;
                                sp <= sp_dec;
                                state <= STORE1;
                        end
                `JSL:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                store_what <= `STW_PC3124;
                                sp <= sp_dec;
                                state <= STORE1;
                        end
                `JSR_INDX:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                sp <= sp_dec;
                                store_what <= `STW_PC158;
                                state <= STORE1;
                        end
                `RTS,`RTL:
                        begin
                                radr <= {spage[31:8],sp_inc[7:2]};
                                radr2LSB <= sp_inc[1:0];
                                sp <= sp_inc;
                                load_what <= `PC_70;
                                state <= LOAD_MAC1;
                        end
                `RTI:   begin
                                radr <= {spage[31:8],sp_inc[7:2]};
                                radr2LSB <= sp_inc[1:0];
                                sp <= sp_inc;
                                load_what <= `SR_70;
                                state <= LOAD_MAC1;
                                end
                `BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
                        begin
                                if (ir[15:8]==8'hFF) begin
                                        if (takb)
                                                pc <= pc + {{16{ir[31]}},ir[31:16]};
                                        else
                                                pc <= pc + 32'd4;
                                end
                                else
                                begin
                                        if (takb)
                                                pc <= pc + {{24{ir[15]}},ir[15:8]} + 32'd2;
                                        else
                                                pc <= pc + 32'd2;
                                end
                        end
                `PHP:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr <= {spage[31:8],sp[7:2]};
                                wadr2LSB <= sp[1:0];
                                sp <= sp_dec;
                                store_what <= `STW_SR70;
                                state <= STORE1;
                        end
                `PHA:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr <= {spage[31:8],sp[7:2]};
                                wadr2LSB <= sp[1:0];
                                store_what <= `STW_ACC8;
                                sp <= sp_dec;
                                state <= STORE1;
                        end
                `PHX:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr <= {spage[31:8],sp[7:2]};
                                wadr2LSB <= sp[1:0];
                                store_what <= `STW_X8;
                                sp <= sp_dec;
                                state <= STORE1;
                        end
                `PHY:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr <= {spage[31:8],sp[7:2]};
                                wadr2LSB <= sp[1:0];
                                store_what <= `STW_Y8;
                                sp <= sp_dec;
                                state <= STORE1;
                        end
                `PLP:
                        begin
                                radr <= {spage[31:8],sp_inc[7:2]};
                                radr2LSB <= sp_inc[1:0];
                                sp <= sp_inc;
                                load_what <= `SR_70;
                                state <= LOAD_MAC1;
                        end
                `PLA,`PLX,`PLY:
                        begin
                                radr <= {spage[31:8],sp_inc[7:2]};
                                radr2LSB <= sp_inc[1:0];
                                sp <= sp_inc;
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                default:        // unimplemented opcode
                        pc <= pc + 32'd1;
                endcase
        end
 

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// Byte mode decode/execute state`
22			`// ============================================================================`
23			`//`
24			`BYTE_DECODE:`
25			`begin`
26			first_ifetch <= `TRUE;
27	32	robfinch	`state <= BYTE_IFETCH;`
28			`pc <= pc + pc_inc8;`
29	20	robfinch	`case(ir[7:0])`
30	32	robfinch	`STP: begin clk_en <= 1'b0; end
31			`NAT: begin em <= 1'b0; state <= IFETCH; end
32			`NOP: ;
33			`CLC: begin cf <= 1'b0; end
34			`SEC: begin cf <= 1'b1; end
35			`CLV: begin vf <= 1'b0; end
36			`CLI: begin im <= 1'b0; end
37			`SEI: begin im <= 1'b1; end
38			`CLD: begin df <= 1'b0; end
39			`SED: begin df <= 1'b1; end
40			`WAI: begin wai <= 1'b1; end
41			`DEX: begin res8 <= x[7:0] - 8'd1; end
42			`INX: begin res8 <= x[7:0] + 8'd1; end
43			`DEY: begin res8 <= y[7:0] - 8'd1; end
44			`INY: begin res8 <= y[7:0] + 8'd1; end
45			`DEA: begin res8 <= acc[7:0] - 8'd1; end
46			`INA: begin res8 <= acc[7:0] + 8'd1; end
47			`TSX,`TSA: begin res8 <= sp[7:0]; end
48			`TXS,`TXA,`TXY: begin res8 <= x[7:0]; end
49			`TAX,`TAY,`TAS: begin res8 <= acc[7:0]; end
50			`TYA,`TYX: begin res8 <= y[7:0]; end
51			`ASL_ACC: begin res8 <= {acc8,1'b0}; end
52			`ROL_ACC: begin res8 <= {acc8,cf}; end
53			`LSR_ACC: begin res8 <= {acc8[0],1'b0,acc8[7:1]}; end
54			`ROR_ACC: begin res8 <= {acc8[0],cf,acc8[7:1]}; end
55	20	robfinch	`// Handle # mode`
56			`LDA_IMM,`LDX_IMM,`LDY_IMM:
57			`begin`
58			`pc <= pc + 32'd2;`
59			`res8 <= ir[15:8];`
60			`end`
61			`ADC_IMM:
62			`begin`
63			`res8 <= acc8 + ir[15:8] + {7'b0,cf};`
64			`b8 <= ir[15:8]; // for overflow calc`
65			`end`
66			`SBC_IMM:
67			`begin`
68			`// res8 <= acc8 - ir[15:8] - ~cf;`
69			`res8 <= acc8 - ir[15:8] - {7'b0,~cf};`
70			`$display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);`
71			`b8 <= ir[15:8]; // for overflow calc`
72			`end`
73			`AND_IMM,`BIT_IMM:
74			`begin`
75			`res8 <= acc8 & ir[15:8];`
76			`b8 <= ir[15:8]; // for bit flags`
77			`end`
78	32	robfinch	`ORA_IMM: res8 <= acc8 \| ir[15:8];
79			`EOR_IMM: res8 <= acc8 ^ ir[15:8];
80			`CMP_IMM: res8 <= acc8 - ir[15:8];
81			`CPX_IMM: res8 <= x8 - ir[15:8];
82			`CPY_IMM: res8 <= y8 - ir[15:8];
83	20	robfinch	`// Handle zp mode`
84	21	robfinch	`LDX_ZP,`LDY_ZP,`LDA_ZP:
85			`begin`
86			`radr <= zp_address[31:2];`
87			`radr2LSB <= zp_address[1:0];`
88			load_what <= `BYTE_71;
89			`state <= LOAD_MAC1;`
90			`end`
91			`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
92			`BIT_ZP,`CPX_ZP,`CPY_ZP,
93	20	robfinch	`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
94			`begin`
95			`radr <= zp_address[31:2];`
96			`radr2LSB <= zp_address[1:0];`
97	21	robfinch	load_what <= `BYTE_70;
98			`state <= LOAD_MAC1;`
99	20	robfinch	`end`
100			`STA_ZP:
101			`begin`
102			`wadr <= zp_address[31:2];`
103			`wadr2LSB <= zp_address[1:0];`
104	32	robfinch	store_what <= `STW_ACC8;
105	20	robfinch	`state <= STORE1;`
106			`end`
107			`STX_ZP:
108			`begin`
109			`wadr <= zp_address[31:2];`
110			`wadr2LSB <= zp_address[1:0];`
111	32	robfinch	store_what <= `STW_X8;
112	20	robfinch	`state <= STORE1;`
113			`end`
114			`STY_ZP:
115			`begin`
116			`wadr <= zp_address[31:2];`
117			`wadr2LSB <= zp_address[1:0];`
118	32	robfinch	store_what <= `STW_Y8;
119	20	robfinch	`state <= STORE1;`
120			`end`
121			`STZ_ZP:
122			`begin`
123			`wadr <= zp_address[31:2];`
124			`wadr2LSB <= zp_address[1:0];`
125	32	robfinch	store_what <= `STW_Z8;
126	20	robfinch	`state <= STORE1;`
127			`end`
128			`// Handle zp,x mode`
129	21	robfinch	`LDY_ZPX,`LDA_ZPX:
130			`begin`
131			`radr <= zpx_address[31:2];`
132			`radr2LSB <= zpx_address[1:0];`
133			load_what <= `BYTE_71;
134			`state <= LOAD_MAC1;`
135			`end`
136			`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
137			`BIT_ZPX,
138	20	robfinch	`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
139			`begin`
140			`radr <= zpx_address[31:2];`
141			`radr2LSB <= zpx_address[1:0];`
142	21	robfinch	load_what <= `BYTE_70;
143			`state <= LOAD_MAC1;`
144	20	robfinch	`end`
145			`STA_ZPX:
146			`begin`
147			`wadr <= zpx_address[31:2];`
148			`wadr2LSB <= zpx_address[1:0];`
149	32	robfinch	store_what <= `STW_ACC8;
150	20	robfinch	`state <= STORE1;`
151			`end`
152			`STY_ZPX:
153			`begin`
154			`wadr <= zpx_address[31:2];`
155			`wadr2LSB <= zpx_address[1:0];`
156	32	robfinch	store_what <= `STW_Y8;
157	20	robfinch	`state <= STORE1;`
158			`end`
159			`STZ_ZPX:
160			`begin`
161			`wadr <= zpx_address[31:2];`
162			`wadr2LSB <= zpx_address[1:0];`
163	32	robfinch	store_what <= `STW_Z8;
164	20	robfinch	`state <= STORE1;`
165			`end`
166			`// Handle zp,y`
167			`LDX_ZPY:
168			`begin`
169			`radr <= zpy_address[31:2];`
170			`radr2LSB <= zpy_address[1:0];`
171	21	robfinch	load_what <= `BYTE_71;
172			`state <= LOAD_MAC1;`
173	20	robfinch	`end`
174			`STX_ZPY:
175			`begin`
176			`wadr <= zpy_address[31:2];`
177			`wadr2LSB <= zpy_address[1:0];`
178	32	robfinch	store_what <= `STW_X8;
179	20	robfinch	`state <= STORE1;`
180			`end`
181			`// Handle (zp,x)`
182			`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
183			`begin`
184			`radr <= zpx_address[31:2];`
185			`radr2LSB <= zpx_address[1:0];`
186	21	robfinch	load_what <= `IA_70;
187	32	robfinch	store_what <= `STW_ACC8;
188	21	robfinch	`state <= LOAD_MAC1;`
189	20	robfinch	`end`
190			`// Handle (zp),y`
191			`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
192			`begin`
193			`radr <= zp_address[31:2];`
194			`radr2LSB <= zp_address[1:0];`
195	21	robfinch	isIY <= `TRUE;
196			load_what <= `IA_70;
197	32	robfinch	store_what <= `STW_ACC8;
198	21	robfinch	`state <= LOAD_MAC1;`
199	20	robfinch	`end`
200			`// Handle abs`
201	21	robfinch	`LDA_ABS,`LDX_ABS,`LDY_ABS:
202			`begin`
203			`radr <= abs_address[31:2];`
204			`radr2LSB <= abs_address[1:0];`
205			load_what <= `BYTE_71;
206			`state <= LOAD_MAC1;`
207			`end`
208			`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
209	20	robfinch	`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
210			`CPX_ABS,`CPY_ABS,
211			`BIT_ABS:
212			`begin`
213			`radr <= abs_address[31:2];`
214			`radr2LSB <= abs_address[1:0];`
215	21	robfinch	load_what <= `BYTE_70;
216			`state <= LOAD_MAC1;`
217	20	robfinch	`end`
218			`STA_ABS:
219			`begin`
220			`wadr <= abs_address[31:2];`
221			`wadr2LSB <= abs_address[1:0];`
222	32	robfinch	store_what <= `STW_ACC8;
223	20	robfinch	`state <= STORE1;`
224			`end`
225			`STX_ABS:
226			`begin`
227			`wadr <= abs_address[31:2];`
228			`wadr2LSB <= abs_address[1:0];`
229	32	robfinch	store_what <= `STW_X8;
230	20	robfinch	`state <= STORE1;`
231			`end`
232			`STY_ABS:
233			`begin`
234			`wadr <= abs_address[31:2];`
235			`wadr2LSB <= abs_address[1:0];`
236	32	robfinch	store_what <= `STW_Y8;
237	20	robfinch	`state <= STORE1;`
238			`end`
239			`STZ_ABS:
240			`begin`
241			`wadr <= abs_address[31:2];`
242			`wadr2LSB <= abs_address[1:0];`
243	32	robfinch	store_what <= `STW_Z8;
244	20	robfinch	`state <= STORE1;`
245			`end`
246			`// Handle abs,x`
247			`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
248			`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
249			`LDY_ABSX:
250			`begin`
251			`radr <= absx_address[31:2];`
252			`radr2LSB <= absx_address[1:0];`
253	21	robfinch	load_what <= `BYTE_70;
254			`state <= LOAD_MAC1;`
255	20	robfinch	`end`
256			`STA_ABSX:
257			`begin`
258			`wadr <= absx_address[31:2];`
259			`wadr2LSB <= absx_address[1:0];`
260	32	robfinch	store_what <= `STW_ACC8;
261	20	robfinch	`state <= STORE1;`
262			`end`
263			`STZ_ABSX:
264			`begin`
265			`wadr <= absx_address[31:2];`
266			`wadr2LSB <= absx_address[1:0];`
267	32	robfinch	store_what <= `STW_Z8;
268	20	robfinch	`state <= STORE1;`
269			`end`
270			`// Handle abs,y`
271			`ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY,`LDA_ABSY,
272			`LDX_ABSY:
273			`begin`
274			`radr <= absy_address[31:2];`
275			`radr2LSB <= absy_address[1:0];`
276	21	robfinch	load_what <= `BYTE_70;
277			`state <= LOAD_MAC1;`
278	20	robfinch	`end`
279			`STA_ABSY:
280			`begin`
281			`wadr <= absy_address[31:2];`
282			`wadr2LSB <= absy_address[1:0];`
283	32	robfinch	store_what <= `STW_ACC8;
284	20	robfinch	`state <= STORE1;`
285			`end`
286			`// Handle (zp)`
287			`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
288			`begin`
289			`radr <= zp_address[31:2];`
290			`radr2LSB <= zp_address[1:0];`
291	21	robfinch	load_what <= `IA_70;
292	32	robfinch	store_what <= `STW_ACC8;
293	21	robfinch	`state <= LOAD_MAC1;`
294	20	robfinch	`end`
295			`BRK:
296			`begin`
297			`radr <= {spage[31:8],sp[7:2]};`
298			`radr2LSB <= sp[1:0];`
299			`wadr <= {spage[31:8],sp[7:2]};`
300			`wadr2LSB <= sp[1:0];`
301			`sp <= sp_dec;`
302	32	robfinch	store_what <= `STW_PC3124;
303			`state <= STORE1;`
304			`bf <= !hwi;`
305	20	robfinch	`end`
306			`JMP:
307			`begin`
308			`pc[15:0] <= abs_address[15:0];`
309			`end`
310			`JML:
311			`begin`
312			`pc <= ir[39:8];`
313			`end`
314			`JMP_IND:
315			`begin`
316			`radr <= abs_address[31:2];`
317			`radr2LSB <= abs_address[1:0];`
318	21	robfinch	load_what <= `PC_70;
319			`state <= LOAD_MAC1;`
320	20	robfinch	`end`
321			`JMP_INDX:
322			`begin`
323			`radr <= absx_address[31:2];`
324			`radr2LSB <= absx_address[1:0];`
325	21	robfinch	load_what <= `PC_70;
326			`state <= LOAD_MAC1;`
327	20	robfinch	`end`
328			`JSR:
329			`begin`
330			`radr <= {spage[31:8],sp[7:2]};`
331			`wadr <= {spage[31:8],sp[7:2]};`
332			`radr2LSB <= sp[1:0];`
333			`wadr2LSB <= sp[1:0];`
334	32	robfinch	store_what <= `STW_PC158;
335	20	robfinch	`sp <= sp_dec;`
336	32	robfinch	`state <= STORE1;`
337	20	robfinch	`end`
338			`JSL:
339			`begin`
340			`radr <= {spage[31:8],sp[7:2]};`
341			`wadr <= {spage[31:8],sp[7:2]};`
342			`radr2LSB <= sp[1:0];`
343			`wadr2LSB <= sp[1:0];`
344	32	robfinch	store_what <= `STW_PC3124;
345	20	robfinch	`sp <= sp_dec;`
346	32	robfinch	`state <= STORE1;`
347	20	robfinch	`end`
348			`JSR_INDX:
349			`begin`
350			`radr <= {spage[31:8],sp[7:2]};`
351			`wadr <= {spage[31:8],sp[7:2]};`
352			`radr2LSB <= sp[1:0];`
353			`wadr2LSB <= sp[1:0];`
354			`sp <= sp_dec;`
355	32	robfinch	store_what <= `STW_PC158;
356			`state <= STORE1;`
357	20	robfinch	`end`
358			`RTS,`RTL:
359			`begin`
360			`radr <= {spage[31:8],sp_inc[7:2]};`
361			`radr2LSB <= sp_inc[1:0];`
362			`sp <= sp_inc;`
363	21	robfinch	load_what <= `PC_70;
364			`state <= LOAD_MAC1;`
365	20	robfinch	`end`
366			`RTI: begin
367			`radr <= {spage[31:8],sp_inc[7:2]};`
368			`radr2LSB <= sp_inc[1:0];`
369			`sp <= sp_inc;`
370	21	robfinch	load_what <= `SR_70;
371			`state <= LOAD_MAC1;`
372	20	robfinch	`end`
373			`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
374			`begin`
375			`if (ir[15:8]==8'hFF) begin`
376			`if (takb)`
377			`pc <= pc + {{16{ir[31]}},ir[31:16]};`
378			`else`
379			`pc <= pc + 32'd4;`
380			`end`
381	32	robfinch	`else`
382			`begin`
383	20	robfinch	`if (takb)`
384			`pc <= pc + {{24{ir[15]}},ir[15:8]} + 32'd2;`
385			`else`
386			`pc <= pc + 32'd2;`
387			`end`
388			`end`
389			`PHP:
390			`begin`
391			`radr <= {spage[31:8],sp[7:2]};`
392			`radr2LSB <= sp[1:0];`
393			`wadr <= {spage[31:8],sp[7:2]};`
394			`wadr2LSB <= sp[1:0];`
395			`sp <= sp_dec;`
396	32	robfinch	store_what <= `STW_SR70;
397			`state <= STORE1;`
398	20	robfinch	`end`
399			`PHA:
400			`begin`
401			`radr <= {spage[31:8],sp[7:2]};`
402			`radr2LSB <= sp[1:0];`
403			`wadr <= {spage[31:8],sp[7:2]};`
404			`wadr2LSB <= sp[1:0];`
405	32	robfinch	store_what <= `STW_ACC8;
406	20	robfinch	`sp <= sp_dec;`
407	32	robfinch	`state <= STORE1;`
408	20	robfinch	`end`
409			`PHX:
410			`begin`
411			`radr <= {spage[31:8],sp[7:2]};`
412			`radr2LSB <= sp[1:0];`
413			`wadr <= {spage[31:8],sp[7:2]};`
414			`wadr2LSB <= sp[1:0];`
415	32	robfinch	store_what <= `STW_X8;
416	20	robfinch	`sp <= sp_dec;`
417	32	robfinch	`state <= STORE1;`
418	20	robfinch	`end`
419			`PHY:
420			`begin`
421			`radr <= {spage[31:8],sp[7:2]};`
422			`radr2LSB <= sp[1:0];`
423			`wadr <= {spage[31:8],sp[7:2]};`
424			`wadr2LSB <= sp[1:0];`
425	32	robfinch	store_what <= `STW_Y8;
426	20	robfinch	`sp <= sp_dec;`
427	32	robfinch	`state <= STORE1;`
428	20	robfinch	`end`
429			`PLP:
430			`begin`
431			`radr <= {spage[31:8],sp_inc[7:2]};`
432			`radr2LSB <= sp_inc[1:0];`
433			`sp <= sp_inc;`
434	21	robfinch	load_what <= `SR_70;
435			`state <= LOAD_MAC1;`
436	20	robfinch	`end`
437			`PLA,`PLX,`PLY:
438			`begin`
439			`radr <= {spage[31:8],sp_inc[7:2]};`
440			`radr2LSB <= sp_inc[1:0];`
441			`sp <= sp_inc;`
442	21	robfinch	load_what <= `BYTE_71;
443			`state <= LOAD_MAC1;`
444	20	robfinch	`end`
445			`default: // unimplemented opcode`
446			`pc <= pc + 32'd1;`
447			`endcase`
448			`end`
449

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