OpenCores
URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_irq.v] - Blame information for rev 30

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 robfinch 
// ============================================================================
2 
//        __
3 
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
4 
//    \  __ /    All rights reserved.
5 
//     \/_//     robfinch<remove>@opencores.org
6 
//       ||
7 
//
8 
// This source file is free software: you can redistribute it and/or modify
9 
// it under the terms of the GNU Lesser General Public License as published
10 
// by the Free Software Foundation, either version 3 of the License, or
11 
// (at your option) any later version.
12 
//
13 
// This source file is distributed in the hope that it will be useful,
14 
// but WITHOUT ANY WARRANTY; without even the implied warranty of
15 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 
// GNU General Public License for more details.
17 
//
18 
// You should have received a copy of the GNU General Public License
19 
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 
//
21 
// ============================================================================
22 
//
23 
// IRQ processing states for 65C02 emulation mode
24 5 robfinch 
// The high order PC[31:16] is set to zero, forcing the IRQ routine to be in bank zero.
25 
//
26 
BYTE_IRQ1:
27 
        if (ack_i) begin
28 10 robfinch 
                state <= BYTE_IRQ2;
29 
                retstate <= BYTE_IRQ2;
30 5 robfinch 
                cyc_o <= 1'b0;
31 
                stb_o <= 1'b0;
32 
                we_o <= 1'b0;
33 
                sel_o <= 4'h0;
34 
                sp <= sp_dec;
35 
                if (dhit) begin
36 
                        wrsel <= sel_o;
37 
                        wr <= 1'b1;
38 
                end
39 10 robfinch 
                else if (write_allocate) begin
40 
                        state <= WAIT_DHIT;
41 
                        dmiss <= `TRUE;
42 
                end
43 5 robfinch 
        end
44 
BYTE_IRQ2:
45 
        begin
46 13 robfinch 
                radr <= {spage[31:8],sp[7:2]};
47 5 robfinch 
                radr2LSB <= sp[1:0];
48 13 robfinch 
                wadr <= {spage[31:8],sp[7:2]};
49 5 robfinch 
                wadr2LSB <= sp[1:0];
50 
                wdat <= {4{pc[23:16]}};
51 
                cyc_o <= 1'b1;
52 
                stb_o <= 1'b1;
53 
                we_o <= 1'b1;
54 
                case(sp[1:0])
55 
                2'd0:   sel_o <= 4'b0001;
56 
                2'd1:   sel_o <= 4'b0010;
57 
                2'd2:   sel_o <= 4'b0100;
58 
                2'd3:   sel_o <= 4'b1000;
59 
                endcase
60 13 robfinch 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
61 5 robfinch 
                dat_o <= {4{pc[23:16]}};
62 
                state <= BYTE_IRQ3;
63 
        end
64 
BYTE_IRQ3:
65 
        if (ack_i) begin
66 10 robfinch 
                state <= BYTE_IRQ4;
67 
                retstate <= BYTE_IRQ4;
68 5 robfinch 
                cyc_o <= 1'b0;
69 
                stb_o <= 1'b0;
70 
                we_o <= 1'b0;
71 
                sel_o <= 4'h0;
72 
                sp <= sp_dec;
73 
                if (dhit) begin
74 
                        wrsel <= sel_o;
75 
                        wr <= 1'b1;
76 
                end
77 10 robfinch 
                else if (write_allocate) begin
78 
                        state <= WAIT_DHIT;
79 
                        dmiss <= `TRUE;
80 
                end
81 5 robfinch 
        end
82 
BYTE_IRQ4:
83 
        begin
84 13 robfinch 
                radr <= {spage[31:8],sp[7:2]};
85 5 robfinch 
                radr2LSB <= sp[1:0];
86 13 robfinch 
                wadr <= {spage[31:8],sp[7:2]};
87 5 robfinch 
                wadr2LSB <= sp[1:0];
88 
                wdat <= {4{pc[15:8]}};
89 
                cyc_o <= 1'b1;
90 
                stb_o <= 1'b1;
91 
                we_o <= 1'b1;
92 
                case(sp[1:0])
93 
                2'd0:   sel_o <= 4'b0001;
94 
                2'd1:   sel_o <= 4'b0010;
95 
                2'd2:   sel_o <= 4'b0100;
96 
                2'd3:   sel_o <= 4'b1000;
97 
                endcase
98 13 robfinch 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
99 5 robfinch 
                dat_o <= {4{pc[15:8]}};
100 
                state <= BYTE_IRQ5;
101 
        end
102 
BYTE_IRQ5:
103 
        if (ack_i) begin
104 10 robfinch 
                state <= BYTE_IRQ6;
105 
                retstate <= BYTE_IRQ6;
106 5 robfinch 
                cyc_o <= 1'b0;
107 
                stb_o <= 1'b0;
108 
                we_o <= 1'b0;
109 
                sel_o <= 4'h0;
110 
                sp <= sp_dec;
111 
                if (dhit) begin
112 
                        wrsel <= sel_o;
113 
                        wr <= 1'b1;
114 
                end
115 10 robfinch 
                else if (write_allocate) begin
116 
                        state <= WAIT_DHIT;
117 
                        dmiss <= `TRUE;
118 
                end
119 5 robfinch 
        end
120 
BYTE_IRQ6:
121 
        begin
122 13 robfinch 
                radr <= {spage[31:8],sp[7:2]};
123 5 robfinch 
                radr2LSB <= sp[1:0];
124 13 robfinch 
                wadr <= {spage[31:8],sp[7:2]};
125 5 robfinch 
                wadr2LSB <= sp[1:0];
126 
                wdat <= {4{pc[7:0]}};
127 
                cyc_o <= 1'b1;
128 
                stb_o <= 1'b1;
129 
                we_o <= 1'b1;
130 
                case(sp[1:0])
131 
                2'd0:   sel_o <= 4'b0001;
132 
                2'd1:   sel_o <= 4'b0010;
133 
                2'd2:   sel_o <= 4'b0100;
134 
                2'd3:   sel_o <= 4'b1000;
135 
                endcase
136 13 robfinch 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
137 5 robfinch 
                dat_o <= {4{pc[7:0]}};
138 
                state <= BYTE_IRQ7;
139 
        end
140 
BYTE_IRQ7:
141 
        if (ack_i) begin
142 10 robfinch 
                state <= BYTE_IRQ8;
143 
                retstate <= BYTE_IRQ8;
144 5 robfinch 
                cyc_o <= 1'b0;
145 
                stb_o <= 1'b0;
146 
                we_o <= 1'b0;
147 
                sel_o <= 4'h0;
148 
                sp <= sp_dec;
149 
                if (dhit) begin
150 
                        wrsel <= sel_o;
151 
                        wr <= 1'b1;
152 
                end
153 10 robfinch 
                else if (write_allocate) begin
154 
                        state <= WAIT_DHIT;
155 
                        dmiss <= `TRUE;
156 
                end
157 5 robfinch 
        end
158 
BYTE_IRQ8:
159 
        begin
160 13 robfinch 
                radr <= {spage[31:8],sp[7:2]};
161 5 robfinch 
                radr2LSB <= sp[1:0];
162 13 robfinch 
                wadr <= {spage[31:8],sp[7:2]};
163 5 robfinch 
                wadr2LSB <= sp[1:0];
164 
                wdat <= {4{sr8[7:0]}};
165 
                cyc_o <= 1'b1;
166 
                stb_o <= 1'b1;
167 
                we_o <= 1'b1;
168 
                case(sp[1:0])
169 
                2'd0:   sel_o <= 4'b0001;
170 
                2'd1:   sel_o <= 4'b0010;
171 
                2'd2:   sel_o <= 4'b0100;
172 
                2'd3:   sel_o <= 4'b1000;
173 
                endcase
174 13 robfinch 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
175 5 robfinch 
                dat_o <= {4{sr8[7:0]}};
176 
                state <= BYTE_IRQ9;
177 
        end
178 
BYTE_IRQ9:
179 
        if (ack_i) begin
180 30 robfinch 
                load_what <= `PC_70;
181 
                state <= LOAD_MAC1;
182 
                retstate <= LOAD_MAC1;
183 5 robfinch 
                cyc_o <= 1'b0;
184 
                stb_o <= 1'b0;
185 
                we_o <= 1'b0;
186 
                sel_o <= 4'h0;
187 
                sp <= sp_dec;
188 
                if (dhit) begin
189 
                        wrsel <= sel_o;
190 
                        wr <= 1'b1;
191 
                end
192 10 robfinch 
                else if (write_allocate) begin
193 
                        state <= WAIT_DHIT;
194 
                        dmiss <= `TRUE;
195 
                end
196 5 robfinch 
                pc[31:16] <= 16'h0000;
197 
                radr <= vect[31:2];
198 
                radr2LSB <= vect[1:0];
199 
        end
200 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.