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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Blame information for rev 30

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
// Cache controller
// Also takes care of loading the instruction buffer for non-cached access
//
case(cstate)
IDLE:
        begin
                if (!cyc_o) begin
`ifdef SUPPORT_DCACHE
                        // A write to a cacheable address does not cause a cache load
                        if (dmiss) begin
                                isDataCacheLoad <= `TRUE;
                                if (isRMW)
                                        lock_o <= 1'b1;
                                cti_o <= 3'b001;
                                bl_o <= 6'd3;
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                sel_o <= 4'hF;
                                adr_o <= {radr[31:2],4'h0};
                                cstate <= LOAD_DCACHE;
                        end
                        else
`endif
`ifdef SUPPORT_ICACHE
                        if (!unCachedInsn && imiss && !hit0) begin
                                isInsnCacheLoad <= `TRUE;
                                bte_o <= 2'b00;
                                cti_o <= 3'd001;
                                bl_o <= 6'd3;
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                sel_o <= 4'hF;
                                adr_o <= {pc[31:4],4'h0};
                                cstate <= LOAD_ICACHE;
                        end
                        else if (!unCachedInsn && imiss && !hit1) begin
                                isInsnCacheLoad <= `TRUE;
                                bte_o <= 2'b00;
                                cti_o <= 3'd001;
                                bl_o <= 6'd3;
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                sel_o <= 4'hF;
                                adr_o <= {pcp8[31:4],4'h0};
                                cstate <= LOAD_ICACHE;
                        end
                        else
`endif
                        if (unCachedInsn && imiss) begin
                                bte_o <= 2'b00;
                                cti_o <= 3'b001;
                                bl_o <= 6'd2;
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                sel_o <= 4'hf;
                                adr_o <= {pc[31:2],2'b00};
                                cstate <= LOAD_IBUF1;
                        end
                end
        end
`ifdef SUPPORT_DCACHE
LOAD_DCACHE:
        if (ack_i) begin
                if (adr_o[3:2]==2'b11) begin
                        dmiss <= `FALSE;
                        isDataCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'h0;
                        cstate <= IDLE;
                end
                adr_o <= adr_o + 34'd4;
        end
        // What to do here
`ifdef SUPPORT_BERR
        else if (err_i) begin
                if (adr_o[3:2]==2'b11) begin
                        dmiss <= `FALSE;
                        isDataCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'h0;
                        cstate <= IDLE;
                        // The state machine will be waiting for a dhit.
                        // Override the next state and send the processor to the bus error state.
                        state <= BUS_ERROR;
                end
                adr_o <= adr_o + 34'd4;
        end
`endif
`endif
`ifdef SUPPORT_ICACHE
LOAD_ICACHE:
        if (ack_i) begin
                if (adr_o[3:2]==2'b11) begin
                        imiss <= `FALSE;
                        isInsnCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'd0;
                        cstate <= IDLE;
                end
                adr_o <= adr_o + 34'd4;
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                if (adr_o[3:2]==2'b11) begin
                        imiss <= `FALSE;
                        isInsnCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'd0;
                        state <= INSN_BUS_ERROR;
                        cstate <= IDLE;
                end
                adr_o <= adr_o + 34'd4;
        end
`endif
`endif
LOAD_IBUF1:
        if (ack_i|err_i) begin
                case(pc[1:0])
                2'd0:   ibuf <= dat_i;
                2'd1:   ibuf <= dat_i[31:8];
                2'd2:   ibuf <= dat_i[31:16];
                2'd3:   ibuf <= dat_i[31:24];
                endcase
                cstate <= LOAD_IBUF2;
                adr_o <= adr_o + 34'd4;
        end
LOAD_IBUF2:
        if (ack_i|err_i) begin
                case(pc[1:0])
                2'd0:   ibuf[55:32] <= dat_i[23:0];
                2'd1:   ibuf[55:24] <= dat_i;
                2'd2:   ibuf[47:16] <= dat_i;
                2'd3:   ibuf[39:8] <= dat_i;
                endcase
                cstate <= LOAD_IBUF3;
                adr_o <= adr_o + 34'd4;
        end
LOAD_IBUF3:
        if (ack_i) begin
                case(pc[1:0])
                2'd0:   ;
                2'd1:   ;
                2'd2:   ibuf[55:48] <= dat_i[7:0];
                2'd3:   ibuf[55:40] <= dat_i[15:0];
                endcase
                cti_o <= 3'd0;
                bl_o <= 6'd0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'd0;
                cstate <= IDLE;
                imiss <= `FALSE;
                bufadr <= pc;   // clears the miss
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                case(pc[1:0])
                2'd0:   ;
                2'd1:   ;
                2'd2:   ibuf[55:48] <= dat_i[7:0];
                2'd3:   ibuf[55:40] <= dat_i[15:0];
                endcase
                cti_o <= 3'd0;
                bl_o <= 6'd0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'd0;
                cstate <= IDLE;
                state <= INSN_BUS_ERROR;
                imiss <= `FALSE;
                bufadr <= pc;   // clears the miss
        end
`endif
 
endcase

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`// Cache controller`
24			`// Also takes care of loading the instruction buffer for non-cached access`
25			`//`
26			`case(cstate)`
27			`IDLE:`
28			`begin`
29			`if (!cyc_o) begin`
30	30	robfinch	`ifdef SUPPORT_DCACHE
31	5	robfinch	`// A write to a cacheable address does not cause a cache load`
32			`if (dmiss) begin`
33			isDataCacheLoad <= `TRUE;
34			`if (isRMW)`
35			`lock_o <= 1'b1;`
36			`cti_o <= 3'b001;`
37			`bl_o <= 6'd3;`
38			`cyc_o <= 1'b1;`
39			`stb_o <= 1'b1;`
40			`sel_o <= 4'hF;`
41			`adr_o <= {radr[31:2],4'h0};`
42			`cstate <= LOAD_DCACHE;`
43			`end`
44	30	robfinch	`else`
45			`endif
46			`ifdef SUPPORT_ICACHE
47			`if (!unCachedInsn && imiss && !hit0) begin`
48	5	robfinch	isInsnCacheLoad <= `TRUE;
49			`bte_o <= 2'b00;`
50			`cti_o <= 3'd001;`
51			`bl_o <= 6'd3;`
52			`cyc_o <= 1'b1;`
53			`stb_o <= 1'b1;`
54			`sel_o <= 4'hF;`
55			`adr_o <= {pc[31:4],4'h0};`
56			`cstate <= LOAD_ICACHE;`
57			`end`
58			`else if (!unCachedInsn && imiss && !hit1) begin`
59			isInsnCacheLoad <= `TRUE;
60			`bte_o <= 2'b00;`
61			`cti_o <= 3'd001;`
62			`bl_o <= 6'd3;`
63			`cyc_o <= 1'b1;`
64			`stb_o <= 1'b1;`
65			`sel_o <= 4'hF;`
66			`adr_o <= {pcp8[31:4],4'h0};`
67			`cstate <= LOAD_ICACHE;`
68			`end`
69	30	robfinch	`else`
70			`endif
71			`if (unCachedInsn && imiss) begin`
72	5	robfinch	`bte_o <= 2'b00;`
73			`cti_o <= 3'b001;`
74			`bl_o <= 6'd2;`
75			`cyc_o <= 1'b1;`
76			`stb_o <= 1'b1;`
77			`sel_o <= 4'hf;`
78			`adr_o <= {pc[31:2],2'b00};`
79			`cstate <= LOAD_IBUF1;`
80			`end`
81			`end`
82			`end`
83	30	robfinch	`ifdef SUPPORT_DCACHE
84	5	robfinch	`LOAD_DCACHE:`
85			`if (ack_i) begin`
86			`if (adr_o[3:2]==2'b11) begin`
87			dmiss <= `FALSE;
88			isDataCacheLoad <= `FALSE;
89			`cti_o <= 3'b000;`
90			`bl_o <= 6'd0;`
91			`cyc_o <= 1'b0;`
92			`stb_o <= 1'b0;`
93			`sel_o <= 4'h0;`
94			`adr_o <= 34'h0;`
95			`cstate <= IDLE;`
96			`end`
97			`adr_o <= adr_o + 34'd4;`
98			`end`
99	21	robfinch	`// What to do here`
100	30	robfinch	`ifdef SUPPORT_BERR
101	21	robfinch	`else if (err_i) begin`
102			`if (adr_o[3:2]==2'b11) begin`
103			dmiss <= `FALSE;
104			isDataCacheLoad <= `FALSE;
105			`cti_o <= 3'b000;`
106			`bl_o <= 6'd0;`
107			`cyc_o <= 1'b0;`
108			`stb_o <= 1'b0;`
109			`sel_o <= 4'h0;`
110			`adr_o <= 34'h0;`
111			`cstate <= IDLE;`
112			`// The state machine will be waiting for a dhit.`
113			`// Override the next state and send the processor to the bus error state.`
114			`state <= BUS_ERROR;`
115			`end`
116			`adr_o <= adr_o + 34'd4;`
117			`end`
118	30	robfinch	`endif
119			`endif
120			`ifdef SUPPORT_ICACHE
121	5	robfinch	`LOAD_ICACHE:`
122			`if (ack_i) begin`
123			`if (adr_o[3:2]==2'b11) begin`
124			imiss <= `FALSE;
125			isInsnCacheLoad <= `FALSE;
126			`cti_o <= 3'b000;`
127			`bl_o <= 6'd0;`
128			`cyc_o <= 1'b0;`
129			`stb_o <= 1'b0;`
130			`sel_o <= 4'h0;`
131			`adr_o <= 34'd0;`
132			`cstate <= IDLE;`
133			`end`
134			`adr_o <= adr_o + 34'd4;`
135			`end`
136	30	robfinch	`ifdef SUPPORT_BERR
137	21	robfinch	`else if (err_i) begin`
138			`if (adr_o[3:2]==2'b11) begin`
139			imiss <= `FALSE;
140			isInsnCacheLoad <= `FALSE;
141			`cti_o <= 3'b000;`
142			`bl_o <= 6'd0;`
143			`cyc_o <= 1'b0;`
144			`stb_o <= 1'b0;`
145			`sel_o <= 4'h0;`
146			`adr_o <= 34'd0;`
147			`state <= INSN_BUS_ERROR;`
148			`cstate <= IDLE;`
149			`end`
150			`adr_o <= adr_o + 34'd4;`
151			`end`
152	30	robfinch	`endif
153			`endif
154	5	robfinch	`LOAD_IBUF1:`
155	21	robfinch	`if (ack_i\|err_i) begin`
156	5	robfinch	`case(pc[1:0])`
157			`2'd0: ibuf <= dat_i;`
158			`2'd1: ibuf <= dat_i[31:8];`
159			`2'd2: ibuf <= dat_i[31:16];`
160			`2'd3: ibuf <= dat_i[31:24];`
161			`endcase`
162			`cstate <= LOAD_IBUF2;`
163			`adr_o <= adr_o + 34'd4;`
164			`end`
165			`LOAD_IBUF2:`
166	21	robfinch	`if (ack_i\|err_i) begin`
167	5	robfinch	`case(pc[1:0])`
168			`2'd0: ibuf[55:32] <= dat_i[23:0];`
169	20	robfinch	`2'd1: ibuf[55:24] <= dat_i;`
170			`2'd2: ibuf[47:16] <= dat_i;`
171	5	robfinch	`2'd3: ibuf[39:8] <= dat_i;`
172			`endcase`
173			`cstate <= LOAD_IBUF3;`
174			`adr_o <= adr_o + 34'd4;`
175			`end`
176			`LOAD_IBUF3:`
177			`if (ack_i) begin`
178			`case(pc[1:0])`
179			`2'd0: ;`
180			`2'd1: ;`
181			`2'd2: ibuf[55:48] <= dat_i[7:0];`
182			`2'd3: ibuf[55:40] <= dat_i[15:0];`
183			`endcase`
184			`cti_o <= 3'd0;`
185			`bl_o <= 6'd0;`
186			`cyc_o <= 1'b0;`
187			`stb_o <= 1'b0;`
188			`sel_o <= 4'h0;`
189			`adr_o <= 34'd0;`
190			`cstate <= IDLE;`
191			imiss <= `FALSE;
192			`bufadr <= pc; // clears the miss`
193			`end`
194	30	robfinch	`ifdef SUPPORT_BERR
195	21	robfinch	`else if (err_i) begin`
196			`case(pc[1:0])`
197			`2'd0: ;`
198			`2'd1: ;`
199			`2'd2: ibuf[55:48] <= dat_i[7:0];`
200			`2'd3: ibuf[55:40] <= dat_i[15:0];`
201			`endcase`
202			`cti_o <= 3'd0;`
203			`bl_o <= 6'd0;`
204			`cyc_o <= 1'b0;`
205			`stb_o <= 1'b0;`
206			`sel_o <= 4'h0;`
207			`adr_o <= 34'd0;`
208			`cstate <= IDLE;`
209			`state <= INSN_BUS_ERROR;`
210			imiss <= `FALSE;
211			`bufadr <= pc; // clears the miss`
212			`end`
213	30	robfinch	`endif
214	21	robfinch
215	5	robfinch	`endcase`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Blame information for rev 30