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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
// Cache controller
// Also takes care of loading the instruction buffer for non-cached access
//
 
//IDLE:
//      begin
//              if (!cyc_o) begin
//`ifdef SUPPORT_DCACHE
//                      // A write to a cacheable address does not cause a cache load
//                      if (dmiss) begin
//                              isDataCacheLoad <= `TRUE;
//                              if (isRMW)
//                                      lock_o <= 1'b1;
//                              cti_o <= 3'b001;
//                              bl_o <= 6'd3;
//                              cyc_o <= 1'b1;
//                              stb_o <= 1'b1;
//                              sel_o <= 4'hF;
//                              adr_o <= {radr[31:2],4'h0};
//                              cstate <= LOAD_DCACHE;
//                      end
//                      else
//`endif
//`ifdef SUPPORT_ICACHE
//                      if (!unCachedInsn && imiss && !hit0) begin
//                              isInsnCacheLoad <= `TRUE;
//                              bte_o <= 2'b00;
//                              cti_o <= 3'd001;
//                              bl_o <= 6'd3;
//                              cyc_o <= 1'b1;
//                              stb_o <= 1'b1;
//                              sel_o <= 4'hF;
//                              adr_o <= {pc[31:4],4'h0};
//                              cstate <= LOAD_ICACHE;
//                      end
//                      else if (!unCachedInsn && imiss && !hit1) begin
//                              isInsnCacheLoad <= `TRUE;
//                              bte_o <= 2'b00;
//                              cti_o <= 3'd001;
//                              bl_o <= 6'd3;
//                              cyc_o <= 1'b1;
//                              stb_o <= 1'b1;
//                              sel_o <= 4'hF;
//                              adr_o <= {pcp8[31:4],4'h0};
//                              cstate <= LOAD_ICACHE;
//                      end
//                      else 
//`endif
//                      if (unCachedInsn && imiss) begin
//                              bte_o <= 2'b00;
//                              cti_o <= 3'b001;
//                              bl_o <= 6'd2;
//                              cyc_o <= 1'b1;
//                              stb_o <= 1'b1;
//                              sel_o <= 4'hf;
//                              adr_o <= {pc[31:2],2'b00};
//                              cstate <= LOAD_IBUF1;
//                      end
//              end
//      end
 
 
`ifdef SUPPORT_DCACHE
DCACHE1:
        begin
                isDataCacheLoad <= `TRUE;
                if (isRMW)
                        lock_o <= 1'b1;
                cti_o <= 3'b001;
                bl_o <= 6'd3;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr[31:2],4'h0};
                state <= LOAD_DCACHE;
        end
LOAD_DCACHE:
        if (ack_i) begin
                if (adr_o[3:2]==2'b11) begin
                        dmiss <= `FALSE;
                        isDataCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'h0;
                        state <= retstate;
                end
                adr_o[3:2] <= adr_o[3:2] + 2'd1;
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                if (adr_o[3:2]==2'b11) begin
                        dmiss <= `FALSE;
                        isDataCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'h0;
                        // The state machine will be waiting for a dhit.
                        // Override the next state and send the processor to the bus error state.
                        state <= BUS_ERROR;
                end
                adr_o[3:2] <= adr_o[3:2] + 2'd1;
        end
`endif
`endif
`ifdef SUPPORT_ICACHE
ICACHE1:
        if (!hit0) begin
                isInsnCacheLoad <= `TRUE;
                bte_o <= 2'b00;
                cti_o <= 3'b001;
                bl_o <= 6'd3;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {pc[31:4],4'h0};
                state <= LOAD_ICACHE;
        end
        else if (!hit1) begin
                isInsnCacheLoad <= `TRUE;
                bte_o <= 2'b00;
                cti_o <= 3'b001;
                bl_o <= 6'd3;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {pcp8[31:4],4'h0};
                state <= LOAD_ICACHE;
        end
        else
                state <= em ? BYTE_IFETCH : IFETCH;
LOAD_ICACHE:
        if (ack_i) begin
                if (adr_o[3:2]==2'b11) begin
                        isInsnCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'd0;
`ifdef ICACHE_2WAY
                        clfsr <= {clfsr,clfsr_fb};
`endif
                        state <= ICACHE1;
                end
                adr_o[3:2] <= adr_o[3:2] + 2'd1;
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                if (adr_o[3:2]==2'b11) begin
                        isInsnCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'd0;
                        state <= INSN_BUS_ERROR;
`ifdef ICACHE_2WAY
                        clfsr <= {clfsr,clfsr_fb};
`endif
                end
                adr_o[3:2] <= adr_o[3:2] + 2'd1;
        end
`endif
`endif
//IBUF1:
//      begin
//              bte_o <= 2'b00;
//              cti_o <= 3'b001;
//              bl_o <= 6'd2;
//              cyc_o <= 1'b1;
//              stb_o <= 1'b1;
//              sel_o <= 4'hf;
//              adr_o <= {pc[31:2],2'b00};
//              state <= LOAD_IBUF1;
//      end
LOAD_IBUF1:
        if (!cyc_o) begin
                bte_o <= 2'b00;
                cti_o <= 3'b001;
                bl_o <= 6'd2;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {pc[31:2],2'b00};
        end
        else if (ack_i|err_i) begin
                case(pc[1:0])
                2'd0:   ibuf <= dat_i;
                2'd1:   ibuf <= dat_i[31:8];
                2'd2:   ibuf <= dat_i[31:16];
                2'd3:   ibuf <= dat_i[31:24];
                endcase
                state <= LOAD_IBUF2;
                adr_o <= adr_o + 34'd4;
        end
LOAD_IBUF2:
        if (ack_i|err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                case(pc[1:0])
                2'd0:   ibuf[55:32] <= dat_i[23:0];
                2'd1:   ibuf[55:24] <= dat_i;
                2'd2:   ibuf[47:16] <= dat_i;
                2'd3:   ibuf[39:8] <= dat_i;
                endcase
                state <= LOAD_IBUF3;
                adr_o <= adr_o + 34'd4;
        end
LOAD_IBUF3:
        if (ack_i) begin
                cti_o <= 3'b000;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                case(pc[1:0])
                2'd0:   ;
                2'd1:   ;
                2'd2:   ibuf[55:48] <= dat_i[7:0];
                2'd3:   ibuf[55:40] <= dat_i[15:0];
                endcase
                adr_o <= 34'd0;
                state <= IFETCH;
                bufadr <= pc;   // clears the miss
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                case(pc[1:0])
                2'd0:   ;
                2'd1:   ;
                2'd2:   ibuf[55:48] <= dat_i[7:0];
                2'd3:   ibuf[55:40] <= dat_i[15:0];
                endcase
                cti_o <= 3'b000;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'd0;
                state <= INSN_BUS_ERROR;
                bufadr <= pc;   // clears the miss
        end
`endif

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`// Cache controller`
24			`// Also takes care of loading the instruction buffer for non-cached access`
25			`//`
26	32	robfinch
27			`//IDLE:`
28			`// begin`
29			`// if (!cyc_o) begin`
30			//`ifdef SUPPORT_DCACHE
31			`// // A write to a cacheable address does not cause a cache load`
32			`// if (dmiss) begin`
33			// isDataCacheLoad <= `TRUE;
34			`// if (isRMW)`
35			`// lock_o <= 1'b1;`
36			`// cti_o <= 3'b001;`
37			`// bl_o <= 6'd3;`
38			`// cyc_o <= 1'b1;`
39			`// stb_o <= 1'b1;`
40			`// sel_o <= 4'hF;`
41			`// adr_o <= {radr[31:2],4'h0};`
42			`// cstate <= LOAD_DCACHE;`
43			`// end`
44			`// else`
45			//`endif
46			//`ifdef SUPPORT_ICACHE
47			`// if (!unCachedInsn && imiss && !hit0) begin`
48			// isInsnCacheLoad <= `TRUE;
49			`// bte_o <= 2'b00;`
50			`// cti_o <= 3'd001;`
51			`// bl_o <= 6'd3;`
52			`// cyc_o <= 1'b1;`
53			`// stb_o <= 1'b1;`
54			`// sel_o <= 4'hF;`
55			`// adr_o <= {pc[31:4],4'h0};`
56			`// cstate <= LOAD_ICACHE;`
57			`// end`
58			`// else if (!unCachedInsn && imiss && !hit1) begin`
59			// isInsnCacheLoad <= `TRUE;
60			`// bte_o <= 2'b00;`
61			`// cti_o <= 3'd001;`
62			`// bl_o <= 6'd3;`
63			`// cyc_o <= 1'b1;`
64			`// stb_o <= 1'b1;`
65			`// sel_o <= 4'hF;`
66			`// adr_o <= {pcp8[31:4],4'h0};`
67			`// cstate <= LOAD_ICACHE;`
68			`// end`
69			`// else`
70			//`endif
71			`// if (unCachedInsn && imiss) begin`
72			`// bte_o <= 2'b00;`
73			`// cti_o <= 3'b001;`
74			`// bl_o <= 6'd2;`
75			`// cyc_o <= 1'b1;`
76			`// stb_o <= 1'b1;`
77			`// sel_o <= 4'hf;`
78			`// adr_o <= {pc[31:2],2'b00};`
79			`// cstate <= LOAD_IBUF1;`
80			`// end`
81			`// end`
82			`// end`
83
84
85			`ifdef SUPPORT_DCACHE
86			`DCACHE1:`
87	5	robfinch	`begin`
88	32	robfinch	isDataCacheLoad <= `TRUE;
89			`if (isRMW)`
90			`lock_o <= 1'b1;`
91			`cti_o <= 3'b001;`
92			`bl_o <= 6'd3;`
93			`cyc_o <= 1'b1;`
94			`stb_o <= 1'b1;`
95			`sel_o <= 4'hF;`
96			`adr_o <= {radr[31:2],4'h0};`
97			`state <= LOAD_DCACHE;`
98	5	robfinch	`end`
99			`LOAD_DCACHE:`
100			`if (ack_i) begin`
101			`if (adr_o[3:2]==2'b11) begin`
102			dmiss <= `FALSE;
103			isDataCacheLoad <= `FALSE;
104			`cti_o <= 3'b000;`
105			`bl_o <= 6'd0;`
106			`cyc_o <= 1'b0;`
107			`stb_o <= 1'b0;`
108			`sel_o <= 4'h0;`
109			`adr_o <= 34'h0;`
110	32	robfinch	`state <= retstate;`
111	5	robfinch	`end`
112	32	robfinch	`adr_o[3:2] <= adr_o[3:2] + 2'd1;`
113	5	robfinch	`end`
114	30	robfinch	`ifdef SUPPORT_BERR
115	21	robfinch	`else if (err_i) begin`
116			`if (adr_o[3:2]==2'b11) begin`
117			dmiss <= `FALSE;
118			isDataCacheLoad <= `FALSE;
119			`cti_o <= 3'b000;`
120			`bl_o <= 6'd0;`
121			`cyc_o <= 1'b0;`
122			`stb_o <= 1'b0;`
123			`sel_o <= 4'h0;`
124			`adr_o <= 34'h0;`
125			`// The state machine will be waiting for a dhit.`
126			`// Override the next state and send the processor to the bus error state.`
127			`state <= BUS_ERROR;`
128			`end`
129	32	robfinch	`adr_o[3:2] <= adr_o[3:2] + 2'd1;`
130	21	robfinch	`end`
131	30	robfinch	`endif
132			`endif
133			`ifdef SUPPORT_ICACHE
134	32	robfinch	`ICACHE1:`
135			`if (!hit0) begin`
136			isInsnCacheLoad <= `TRUE;
137			`bte_o <= 2'b00;`
138			`cti_o <= 3'b001;`
139			`bl_o <= 6'd3;`
140			`cyc_o <= 1'b1;`
141			`stb_o <= 1'b1;`
142			`sel_o <= 4'hF;`
143			`adr_o <= {pc[31:4],4'h0};`
144			`state <= LOAD_ICACHE;`
145			`end`
146			`else if (!hit1) begin`
147			isInsnCacheLoad <= `TRUE;
148			`bte_o <= 2'b00;`
149			`cti_o <= 3'b001;`
150			`bl_o <= 6'd3;`
151			`cyc_o <= 1'b1;`
152			`stb_o <= 1'b1;`
153			`sel_o <= 4'hF;`
154			`adr_o <= {pcp8[31:4],4'h0};`
155			`state <= LOAD_ICACHE;`
156			`end`
157			`else`
158			`state <= em ? BYTE_IFETCH : IFETCH;`
159	5	robfinch	`LOAD_ICACHE:`
160			`if (ack_i) begin`
161			`if (adr_o[3:2]==2'b11) begin`
162			isInsnCacheLoad <= `FALSE;
163			`cti_o <= 3'b000;`
164			`bl_o <= 6'd0;`
165			`cyc_o <= 1'b0;`
166			`stb_o <= 1'b0;`
167			`sel_o <= 4'h0;`
168			`adr_o <= 34'd0;`
169	32	robfinch	`ifdef ICACHE_2WAY
170			`clfsr <= {clfsr,clfsr_fb};`
171			`endif
172			`state <= ICACHE1;`
173	5	robfinch	`end`
174	32	robfinch	`adr_o[3:2] <= adr_o[3:2] + 2'd1;`
175	5	robfinch	`end`
176	30	robfinch	`ifdef SUPPORT_BERR
177	21	robfinch	`else if (err_i) begin`
178			`if (adr_o[3:2]==2'b11) begin`
179			isInsnCacheLoad <= `FALSE;
180			`cti_o <= 3'b000;`
181			`bl_o <= 6'd0;`
182			`cyc_o <= 1'b0;`
183			`stb_o <= 1'b0;`
184			`sel_o <= 4'h0;`
185			`adr_o <= 34'd0;`
186			`state <= INSN_BUS_ERROR;`
187	32	robfinch	`ifdef ICACHE_2WAY
188			`clfsr <= {clfsr,clfsr_fb};`
189			`endif
190	21	robfinch	`end`
191	32	robfinch	`adr_o[3:2] <= adr_o[3:2] + 2'd1;`
192	21	robfinch	`end`
193	30	robfinch	`endif
194			`endif
195	32	robfinch	`//IBUF1:`
196			`// begin`
197			`// bte_o <= 2'b00;`
198			`// cti_o <= 3'b001;`
199			`// bl_o <= 6'd2;`
200			`// cyc_o <= 1'b1;`
201			`// stb_o <= 1'b1;`
202			`// sel_o <= 4'hf;`
203			`// adr_o <= {pc[31:2],2'b00};`
204			`// state <= LOAD_IBUF1;`
205			`// end`
206	5	robfinch	`LOAD_IBUF1:`
207	32	robfinch	`if (!cyc_o) begin`
208			`bte_o <= 2'b00;`
209			`cti_o <= 3'b001;`
210			`bl_o <= 6'd2;`
211			`cyc_o <= 1'b1;`
212			`stb_o <= 1'b1;`
213			`sel_o <= 4'hF;`
214			`adr_o <= {pc[31:2],2'b00};`
215			`end`
216			`else if (ack_i\|err_i) begin`
217	5	robfinch	`case(pc[1:0])`
218			`2'd0: ibuf <= dat_i;`
219			`2'd1: ibuf <= dat_i[31:8];`
220			`2'd2: ibuf <= dat_i[31:16];`
221			`2'd3: ibuf <= dat_i[31:24];`
222			`endcase`
223	32	robfinch	`state <= LOAD_IBUF2;`
224	5	robfinch	`adr_o <= adr_o + 34'd4;`
225			`end`
226			`LOAD_IBUF2:`
227	21	robfinch	`if (ack_i\|err_i) begin`
228	32	robfinch	`cyc_o <= 1'b0;`
229			`stb_o <= 1'b0;`
230			`sel_o <= 4'h0;`
231	5	robfinch	`case(pc[1:0])`
232			`2'd0: ibuf[55:32] <= dat_i[23:0];`
233	20	robfinch	`2'd1: ibuf[55:24] <= dat_i;`
234			`2'd2: ibuf[47:16] <= dat_i;`
235	5	robfinch	`2'd3: ibuf[39:8] <= dat_i;`
236			`endcase`
237	32	robfinch	`state <= LOAD_IBUF3;`
238	5	robfinch	`adr_o <= adr_o + 34'd4;`
239			`end`
240			`LOAD_IBUF3:`
241			`if (ack_i) begin`
242	32	robfinch	`cti_o <= 3'b000;`
243			`cyc_o <= 1'b0;`
244			`stb_o <= 1'b0;`
245			`sel_o <= 4'h0;`
246	5	robfinch	`case(pc[1:0])`
247			`2'd0: ;`
248			`2'd1: ;`
249			`2'd2: ibuf[55:48] <= dat_i[7:0];`
250			`2'd3: ibuf[55:40] <= dat_i[15:0];`
251			`endcase`
252			`adr_o <= 34'd0;`
253	32	robfinch	`state <= IFETCH;`
254	5	robfinch	`bufadr <= pc; // clears the miss`
255			`end`
256	30	robfinch	`ifdef SUPPORT_BERR
257	21	robfinch	`else if (err_i) begin`
258			`case(pc[1:0])`
259			`2'd0: ;`
260			`2'd1: ;`
261			`2'd2: ibuf[55:48] <= dat_i[7:0];`
262			`2'd3: ibuf[55:40] <= dat_i[15:0];`
263			`endcase`
264	32	robfinch	`cti_o <= 3'b000;`
265	21	robfinch	`cyc_o <= 1'b0;`
266			`stb_o <= 1'b0;`
267			`sel_o <= 4'h0;`
268			`adr_o <= 34'd0;`
269			`state <= INSN_BUS_ERROR;`
270			`bufadr <= pc; // clears the miss`
271			`end`
272	30	robfinch	`endif

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Blame information for rev 32