OpenCores
URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [calc.v] - Blame information for rev 30

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch<remove>@opencores.org
6
//       ||
7
//
8
// This source file is free software: you can redistribute it and/or modify 
9
// it under the terms of the GNU Lesser General Public License as published 
10
// by the Free Software Foundation, either version 3 of the License, or     
11
// (at your option) any later version.                                      
12
//                                                                          
13
// This source file is distributed in the hope that it will be useful,      
14
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
15
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
16
// GNU General Public License for more details.                             
17
//                                                                          
18
// You should have received a copy of the GNU General Public License        
19
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
20 20 robfinch
//                                                   
21 30 robfinch
// Extra state required for some datapath operations.                       
22 10 robfinch
// ============================================================================
23
//
24 5 robfinch
CALC:
25
        begin
26
                state <= IFETCH;
27 30 robfinch
                res <= calc_res;
28
                wadr <= radr;                   // These two lines for the shift/inc/dec ops
29
                store_what <= `STW_CALC;
30 20 robfinch
                case(ir[7:0])
31 30 robfinch
                `ASL_ZPX,`ASL_ABS,`ASL_ABSX,
32
                `ROL_ZPX,`ROL_ABS,`ROL_ABSX,
33
                `LSR_ZPX,`LSR_ABS,`LSR_ABSX,
34
                `ROR_ZPX,`ROR_ABS,`ROR_ABSX,
35
                `INC_ZPX,`INC_ABS,`INC_ABSX,
36
                `DEC_ZPX,`DEC_ABS,`DEC_ABSX:
37
                        state <= STORE1;
38 20 robfinch
                endcase
39 5 robfinch
        end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.