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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [calc.v] - Blame information for rev 32

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Line No. Rev Author Line
1 10 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                   
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// Extra state required for some datapath operations.                       
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// ============================================================================
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//
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task calc_tsk;
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        begin
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                state <= IFETCH;
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                res <= alu_out;
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                wadr <= radr;                   // These two lines for the shift/inc/dec ops
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                store_what <= `STW_CALC;
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                case(ir9)
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                `BMS_ZPX,`BMS_ABS,`BMS_ABSX,
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                `BMC_ZPX,`BMC_ABS,`BMC_ABSX,
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                `BMF_ZPX,`BMF_ABS,`BMF_ABSX,
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                `ASL_ZPX,`ASL_ABS,`ASL_ABSX,
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                `ROL_ZPX,`ROL_ABS,`ROL_ABSX,
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                `LSR_ZPX,`LSR_ABS,`LSR_ABSX,
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                `ROR_ZPX,`ROR_ABS,`ROR_ABSX,
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                `INC_ZPX,`INC_ABS,`INC_ABSX,
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                `DEC_ZPX,`DEC_ABS,`DEC_ABSX:
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                        state <= STORE1;
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                endcase
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        end
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endtask

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