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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
DECODE:
        begin
                first_ifetch <= `TRUE;
                Rt <= 4'h0;             // Default
                state <= IFETCH;
                pc <= pc + pc_inc;
                a <= rfoa;
                // This case statement should include all opcodes or the opcode
                // will end up being treated as an undefined operation.
                case(ir[7:0])
                `STP:   clk_en <= 1'b0;
                `NOP:   ;
//                              casex(ir[63:0])
//                              {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:      pc <= pcp8;
//                              {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:     pc <= pcp7;
//                              {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:       pc <= pcp6;
//                              {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}:  pc <= pcp5;
//                              {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}:     pc <= pcp4;
//                              {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}:        pc <= pcp3;
//                              {48'hxxxxxxxxxxxx,`NOP,`NOP}:   pc <= pcp2;
//                              {56'hxxxxxxxxxxxxxx,`NOP}:      pc <= pcp1;
//                              endcase
                `CLC:   cf <= 1'b0;
                `SEC:   cf <= 1'b1;
                `CLV:   vf <= 1'b0;
                `CLI:   im <= 1'b0;
                `CLD:   df <= 1'b0;
                `SED:   df <= 1'b1;
                `SEI:   im <= 1'b1;
                `WAI:   wai <= 1'b1;
                `EMM:   em <= 1'b1;
                `DEX:   begin
                                        res <= x - 32'd1;
                                        // DEX/BNE accelerator
//                                      if (ir[15:8]==`BNE) begin
//                                              if (x!=32'd1) begin
//                                                      if (ir[23:16]==8'h01)
//                                                              pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;
//                                                      else
//                                                              pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1;
//                                              end
//                                              else begin
//                                                      if (ir[23:16]==8'h01)
//                                                              pc <= pcp5;
//                                                      else
//                                                              pc <= pcp3;
//                                              end
//                                      end
                                end
                `INX:   res <= x + 32'd1;
                `DEY:   res <= y - 32'd1;
                `INY:   res <= y + 32'd1;
                `DEA:   res <= acc - 32'd1;
                `INA:   res <= acc + 32'd1;
                `TSX,`TSA:      res <= isp;
                `TXS,`TXA,`TXY: res <= x;
                `TAX,`TAY,`TAS: res <= acc;
                `TYA,`TYX:      res <= y;
                `TRS:           res <= rfoa;
                `TSR:           begin
                                                Rt <= ir[15:12];
                                                case(ir[11:8])
                                                4'h0:
                                                        begin
`ifdef SUPPORT_ICACHE
                                                                res[0] <= icacheOn;
`endif
`ifdef SUPPORT_DCACHE
                                                                res[1] <= dcacheOn;
                                                                res[2] <= write_allocate;
`endif
                                                                res[31:3] <= 29'd0;
                                                        end
                                                4'h2:   res <= prod[31:0];
                                                4'h3:   res <= prod[63:32];
                                                4'h4:   res <= tick;
                                                4'h5:   begin res <= lfsr; lfsr <= {lfsr[30:0],lfsr_fb}; end
                                                4'h7:   begin res <= history_buf[history_ndx];  history_ndx <= history_ndx + 6'd1; end// was abs8
                                                4'h8:   res <= {vbr[31:1],nmoi};
                                                4'h9:   res <= derr_address;
                                                4'hE:   res <= {spage[31:8],sp};
                                                4'hF:   res <= isp;
                                                default:        res <= 32'd0;
                                                endcase
                                        end
                `ASL_ACC:       begin res <= {acc,1'b0}; end
                `ROL_ACC:       begin res <= {acc,cf};end
                `LSR_ACC:       begin res <= {acc[0],1'b0,acc[31:1]}; end
                `ROR_ACC:       begin res <= {acc[0],cf,acc[31:1]}; end
 
                `RR:
                        begin
                                state <= IFETCH;
                                Rt <= ir[19:16];
                                case(ir[23:20])
                                `ADD_RR:        begin res <= rfoa + rfob + {31'b0,df&cf}; b <= rfob; end
                                `SUB_RR:        begin res <= rfoa - rfob - {31'b0,df&~cf&|ir[19:16]}; b <= rfob; end
                                `AND_RR:        begin res <= rfoa & rfob; b <= rfob; end        // for bit flags
                                `OR_RR:         begin res <= rfoa | rfob; b <= rfob; end
                                `EOR_RR:        begin res <= rfoa ^ rfob; b <= rfob; end
                                `MUL_RR:        begin state <= MULDIV1; end
                                `MULS_RR:       begin state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                                `DIV_RR:        begin state <= MULDIV1; end
                                `DIVS_RR:       begin state <= MULDIV1; end
                                `MOD_RR:        begin state <= MULDIV1; end
                                `MODS_RR:       begin state <= MULDIV1; end
`endif
`ifdef SUPPORT_SHIFT
                                `ASL_RRR:       begin b <= rfob; state <= CALC; end
                                `LSR_RRR:       begin b <= rfob; state <= CALC; end
`endif
                                default:
                                        begin
                                                Rt <= 4'h0;
                                                ir <= {8{`BRK}};
                                                hwi <= `TRUE;
                                                vect <= {vbr[31:9],9'd495,2'b00};
                                                pc <= pc;               // override the pc increment
                                                state <= DECODE;
                                        end
                                endcase
                        end
                `LD_RR:         begin res <= rfoa; Rt <= ir[15:12]; end
                `ASL_RR:        begin res <= {rfoa,1'b0}; Rt <= ir[15:12]; end
                `ROL_RR:        begin res <= {rfoa,cf}; Rt <= ir[15:12]; end
                `LSR_RR:        begin res <= {rfoa[0],1'b0,rfoa[31:1]}; Rt <= ir[15:12]; end
                `ROR_RR:        begin res <= {rfoa[0],cf,rfoa[31:1]}; Rt <= ir[15:12]; end
                `DEC_RR:        begin res <= rfoa - 32'd1; Rt <= ir[15:12]; end
                `INC_RR:        begin res <= rfoa + 32'd1; Rt <= ir[15:12]; end
 
                `ADD_IMM8:      begin res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `SUB_IMM8:      begin res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `OR_IMM8:       begin res <= rfoa | {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; end
                `AND_IMM8:      begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `EOR_IMM8:      begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; end
                `CMP_IMM8:      begin res <= acc - {{24{ir[15]}},ir[15:8]}; end
`ifdef SUPPORT_SHIFT
                `ASL_IMM8:      begin b <= ir[20:16]; Rt <= ir[15:12]; state <= CALC; end
                `LSR_IMM8:      begin b <= ir[20:16]; Rt <= ir[15:12]; state <= CALC; end
`endif
                `ADD_IMM16:     begin res <= rfoa + {{16{ir[31]}},ir[31:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
                `SUB_IMM16:     begin res <= rfoa - {{16{ir[31]}},ir[31:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
                `OR_IMM16:      begin res <= rfoa | {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; end
                `AND_IMM16:     begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
                `EOR_IMM16:     begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; end
 
                `ADD_IMM32:     begin res <= rfoa + ir[47:16] + {31'b0,df&cf}; Rt <= ir[15:12]; b <= ir[47:16]; end
                `SUB_IMM32:     begin res <= rfoa - ir[47:16] - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; b <= ir[47:16]; end
                `OR_IMM32:      begin res <= rfoa | ir[47:16]; Rt <= ir[15:12]; end
                `AND_IMM32:     begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; b <= ir[47:16]; end
                `EOR_IMM32:     begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; end
 
                `LDX_IMM32,`LDY_IMM32,`LDA_IMM32:       res <= ir[39:8];
                `LDX_IMM16,`LDA_IMM16:  res <= {{16{ir[23]}},ir[23:8]};
                `LDX_IMM8,`LDA_IMM8: res <= {{24{ir[15]}},ir[15:8]};
 
                `SUB_SP8:       res <= isp - {{24{ir[15]}},ir[15:8]};
                `SUB_SP16:      res <= isp - {{16{ir[23]}},ir[23:8]};
                `SUB_SP32:      res <= isp - ir[39:8];
 
                `CPX_IMM32:     res <= x - ir[39:8];
                `CPY_IMM32:     res <= y - ir[39:8];
 
                `LDX_ZPX,`LDY_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address[31:2];
                                radr2LSB <= zpx32_address[1:0];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LDX_ABS,`LDY_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ABS:
                        begin
                                Rt <= ir[15:12];
                                radr <= ir[47:18];
                                radr2LSB <= ir[17:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LDX_ABSY,`LDY_ABSX:
                        begin
                                radr <= absx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ABSX:
                        begin
                                Rt <= ir[19:16];
                                radr <= absx32_address[31:2];
                                radr2LSB <= absx32_address[1:0];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ST_ZPX:
                        begin
                                wadr <= zpx32_address;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ZPX:
                        begin
                                wadr <= zpx32_address[31:2];
                                wadr2LSB <= zpx32_address[1:0];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `ST_DSP:
                        begin
                                wadr <= {{24{ir[23]}},ir[23:16]} + isp;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `ST_ABS:
                        begin
                                wadr <= ir[47:16];
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ABS:
                        begin
                                wadr <= ir[47:18];
                                wadr2LSB <= ir[17:16];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `ST_ABSX:
                        begin
                                wadr <= absx32_address;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ABSX:
                        begin
                                wadr <= absx32_address[31:2];
                                wadr2LSB <= absx32_address[1:0];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `STX_ZPX:
                        begin
                                wadr <= zpx32xy_address;
                                store_what <= `STW_X;
                                state <= STORE1;
                        end
                `STX_ABS:
                        begin
                                wadr <= ir[39:8];
                                store_what <= `STW_X;
                                state <= STORE1;
                        end
                `STY_ZPX:
                        begin
                                wadr <= zpx32xy_address;
                                store_what <= `STW_Y;
                                state <= STORE1;
                        end
                `STY_ABS:
                        begin
                                wadr <= ir[39:8];
                                store_what <= `STW_Y;
                                state <= STORE1;
                        end
                `ADD_ZPX,`SUB_ZPX,`OR_ZPX,`AND_ZPX,`EOR_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
                        begin
                                Rt <= ir[15:12];
                                radr <= {{24{ir[23]}},ir[23:16]} + isp;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
                        begin
                                if (ir[7:0]!=`ST_IX)     // for ST_IX, Rt=0
                                        Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= `IA_310;
                                store_what <= `STW_A;
                                state <= LOAD_MAC1;
                        end
                `ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
                        begin
                                radr <= rfob;
                                Rt <= ir[19:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ST_RIND:
                        begin
                                wadr <= rfob;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
                        begin
                                if (ir[7:0]!=`ST_IY)     // for ST_IY, Rt=0
                                        Rt <= ir[19:16];
                                isIY <= 1'b1;
                                radr <= ir[31:20];
                                load_what <= `IA_310;
                                store_what <= `STW_A;
                                state <= LOAD_MAC1;
                        end
                `ADD_ABS,`SUB_ABS,`OR_ABS,`AND_ABS,`EOR_ABS:
                        begin
                                radr <= ir[47:16];
                                Rt <= ir[15:12];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_ABSX,`SUB_ABSX,`OR_ABSX,`AND_ABSX,`EOR_ABSX:
                        begin
                                radr <= absx32_address;
                                Rt <= ir[19:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
                        begin
                                radr <= absx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
 
                `CPX_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPY_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPX_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPY_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BRK:
                        begin
                                bf <= !hwi;
                                hist_capture <= `FALSE;
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_PCHWI;
                                state <= STORE1;
                        end
                `INT0,`INT1:
                        begin
                                ir <= {8{`BRK}};
                                vect <= {vbr[31:9],ir[15:7],2'b00};
                                state <= DECODE;
                        end
                `JMP:
                        begin
                                pc[15:0] <= ir[23:8];
                                state <= IFETCH;
                        end
                `JML:
                        begin
                                pc <= ir[39:8];
                                state <= IFETCH;
                        end
                `JMP_IND:
                        begin
                                radr <= ir[39:8];
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                        end
                `JMP_INDX:
                        begin
                                radr <= ir[39:8] + x;
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                        end
                `JMP_RIND:
                        begin
                                pc <= rfoa;
                                res <= pc + 32'd2;
                                Rt <= ir[15:12];
                                state <= IFETCH;
                        end
                `JSR:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= pc+{31'd1,suppress_pcinc[0]};
                                pc <= {pc[31:16],ir[23:8]};
                                state <= STORE1;
                        end
                `JSR_RIND:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                wdat <= pc + 32'd2;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                pc <= rfoa;
                                state <= STORE1;
                        end
                `JSL:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
                                pc <= ir[39:8];
                                state <= STORE1;
                        end
                `BSR:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= pc+{31'd1,suppress_pcinc[0]};
                                pc <= pc + {{16{ir[23]}},ir[23:8]};
                                state <= STORE1;
                        end
                `JSR_INDX:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                sel_o <= 4'hF;
                                adr_o <= {isp-32'd1,2'b00};
                                dat_o <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
                                state <= JSR_INDX1;
                        end
//              `JSR16:
//                      begin
//                              radr <= isp - 32'd1;
//                              wadr <= isp - 32'd1;
//                              wdat <= pc + 32'd3;
//                              cyc_o <= 1'b1;
//                              stb_o <= 1'b1;
//                              we_o <= 1'b1;
//                              sel_o <= 4'hF;
//                              adr_o <= {isp-32'd1,2'b00};
//                              dat_o <= pc + 32'd3;
//                              state <= JSR161;
//                      end
                `RTS,`RTL:
                                begin
                                radr <= isp;
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                end
                `RTI:   begin
                                hist_capture <= `TRUE;
                                radr <= isp;
                                load_what <= `SR_310;
                                state <= LOAD_MAC1;
                                end
                `BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA,
                `BGT,`BGE,`BLT,`BLE,`BHI,`BLS:
                        begin
                                state <= IFETCH;
                                if (ir[15:8]==8'h00) begin
                                        ir <= {8{`BRK}};
                                        pc <= pc;               // override the pc increment
                                        vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
                                        state <= DECODE;
                                end
                                else if (ir[15:8]==8'h1) begin
                                        if (takb)
                                                pc <= pc + {{16{ir[31]}},ir[31:16]};
                                        else
                                                pc <= pcp4;
                                end
                                else begin
                                        if (takb)
                                                pc <= pc + {{24{ir[15]}},ir[15:8]};
                                        else
                                                pc <= pcp2;
                                end
                        end
                `BRL:
                        begin
                                if (ir[23:8]==16'h0000) begin
                                        ir <= {8{`BRK}};
                                        vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
                                        pc <= pc;               // override the pc increment
                                        state <= DECODE;
                                end
                                else begin
                                        pc <= pc + {{16{ir[23]}},ir[23:8]};
                                        state <= IFETCH;
                                end
                        end
`ifdef SUPPORT_EXEC
                `EXEC,`ATNI:
                        begin
                                exbuf[31:0] <= rfoa;
                                exbuf[63:32] <= rfob;
                                state <= IFETCH;
                        end
`endif
                `PHP:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_SR;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHA:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_ACC;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHX:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_X;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHY:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_Y;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PUSH:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                                isp <= isp_dec;
                        end
                `PLP:
                        begin
                                radr <= isp;
                                load_what <= `SR_310;
                                state <= LOAD_MAC1;
                        end
                `PLA,`PLX,`PLY:
                        begin
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `POP:
                        begin
                                Rt <= ir[15:12];
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
`ifdef SUPPORT_STRING
                `MVN:   state <= MVN1;
                `MVP:   state <= MVP1;
                `STS:   state <= STS1;
`endif
                default:        // unimplemented opcode
                        begin
                                res <= 32'd0;
                                ir <= {8{`BRK}};
                                hwi <= `TRUE;
                                vect <= {vbr[31:9],9'd495,2'b00};
                                pc <= pc;               // override the pc increment
                                state <= DECODE;
                        end
                endcase
        end

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`DECODE:`
24			`begin`
25			first_ifetch <= `TRUE;
26			`Rt <= 4'h0; // Default`
27			`state <= IFETCH;`
28	30	robfinch	`pc <= pc + pc_inc;`
29			`a <= rfoa;`
30			`// This case statement should include all opcodes or the opcode`
31			`// will end up being treated as an undefined operation.`
32	20	robfinch	`case(ir[7:0])`
33	30	robfinch	`STP: clk_en <= 1'b0;
34			`NOP: ;
35			`// casex(ir[63:0])`
36			// {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8;
37			// {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7;
38			// {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp6;
39			// {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp5;
40			// {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}: pc <= pcp4;
41			// {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}: pc <= pcp3;
42			// {48'hxxxxxxxxxxxx,`NOP,`NOP}: pc <= pcp2;
43			// {56'hxxxxxxxxxxxxxx,`NOP}: pc <= pcp1;
44			`// endcase`
45			`CLC: cf <= 1'b0;
46			`SEC: cf <= 1'b1;
47			`CLV: vf <= 1'b0;
48			`CLI: im <= 1'b0;
49			`CLD: df <= 1'b0;
50			`SED: df <= 1'b1;
51			`SEI: im <= 1'b1;
52			`WAI: wai <= 1'b1;
53			`EMM: em <= 1'b1;
54	25	robfinch	`DEX: begin
55			`res <= x - 32'd1;`
56			`// DEX/BNE accelerator`
57			// if (ir[15:8]==`BNE) begin
58			`// if (x!=32'd1) begin`
59			`// if (ir[23:16]==8'h01)`
60			`// pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;`
61			`// else`
62			`// pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1;`
63			`// end`
64			`// else begin`
65			`// if (ir[23:16]==8'h01)`
66			`// pc <= pcp5;`
67			`// else`
68			`// pc <= pcp3;`
69			`// end`
70			`// end`
71			`end`
72	30	robfinch	`INX: res <= x + 32'd1;
73			`DEY: res <= y - 32'd1;
74			`INY: res <= y + 32'd1;
75			`DEA: res <= acc - 32'd1;
76			`INA: res <= acc + 32'd1;
77			`TSX,`TSA: res <= isp;
78			`TXS,`TXA,`TXY: res <= x;
79			`TAX,`TAY,`TAS: res <= acc;
80			`TYA,`TYX: res <= y;
81			`TRS: res <= rfoa;
82	20	robfinch	`TSR: begin
83			`Rt <= ir[15:12];`
84			`case(ir[11:8])`
85	30	robfinch	`4'h0:`
86			`begin`
87			`ifdef SUPPORT_ICACHE
88			`res[0] <= icacheOn;`
89			`endif
90			`ifdef SUPPORT_DCACHE
91			`res[1] <= dcacheOn;`
92			`res[2] <= write_allocate;`
93			`endif
94			`res[31:3] <= 29'd0;`
95			`end`
96	20	robfinch	`4'h2: res <= prod[31:0];`
97			`4'h3: res <= prod[63:32];`
98			`4'h4: res <= tick;`
99			`4'h5: begin res <= lfsr; lfsr <= {lfsr[30:0],lfsr_fb}; end`
100	30	robfinch	`4'h7: begin res <= history_buf[history_ndx]; history_ndx <= history_ndx + 6'd1; end// was abs8`
101	20	robfinch	`4'h8: res <= {vbr[31:1],nmoi};`
102	23	robfinch	`4'h9: res <= derr_address;`
103	20	robfinch	`4'hE: res <= {spage[31:8],sp};`
104			`4'hF: res <= isp;`
105	30	robfinch	`default: res <= 32'd0;`
106	20	robfinch	`endcase`
107			`end`
108	25	robfinch	`ASL_ACC: begin res <= {acc,1'b0}; end
109			`ROL_ACC: begin res <= {acc,cf};end
110			`LSR_ACC: begin res <= {acc[0],1'b0,acc[31:1]}; end
111			`ROR_ACC: begin res <= {acc[0],cf,acc[31:1]}; end
112	20	robfinch
113			`RR:
114			`begin`
115			`state <= IFETCH;`
116	30	robfinch	`Rt <= ir[19:16];`
117	20	robfinch	`case(ir[23:20])`
118	30	robfinch	`ADD_RR: begin res <= rfoa + rfob + {31'b0,df&cf}; b <= rfob; end
119			`SUB_RR: begin res <= rfoa - rfob - {31'b0,df&~cf&\|ir[19:16]}; b <= rfob; end
120			`AND_RR: begin res <= rfoa & rfob; b <= rfob; end // for bit flags
121			`OR_RR: begin res <= rfoa \| rfob; b <= rfob; end
122			`EOR_RR: begin res <= rfoa ^ rfob; b <= rfob; end
123	20	robfinch	`MUL_RR: begin state <= MULDIV1; end
124			`MULS_RR: begin state <= MULDIV1; end
125	30	robfinch	`ifdef SUPPORT_DIVMOD
126	20	robfinch	`DIV_RR: begin state <= MULDIV1; end
127			`DIVS_RR: begin state <= MULDIV1; end
128			`MOD_RR: begin state <= MULDIV1; end
129			`MODS_RR: begin state <= MULDIV1; end
130	30	robfinch	`endif
131			`ifdef SUPPORT_SHIFT
132			`ASL_RRR: begin b <= rfob; state <= CALC; end
133			`LSR_RRR: begin b <= rfob; state <= CALC; end
134			`endif
135			`default:`
136			`begin`
137			`Rt <= 4'h0;`
138			ir <= {8{`BRK}};
139			hwi <= `TRUE;
140			`vect <= {vbr[31:9],9'd495,2'b00};`
141			`pc <= pc; // override the pc increment`
142			`state <= DECODE;`
143			`end`
144	20	robfinch	`endcase`
145			`end`
146	30	robfinch	`LD_RR: begin res <= rfoa; Rt <= ir[15:12]; end
147			`ASL_RR: begin res <= {rfoa,1'b0}; Rt <= ir[15:12]; end
148			`ROL_RR: begin res <= {rfoa,cf}; Rt <= ir[15:12]; end
149			`LSR_RR: begin res <= {rfoa[0],1'b0,rfoa[31:1]}; Rt <= ir[15:12]; end
150			`ROR_RR: begin res <= {rfoa[0],cf,rfoa[31:1]}; Rt <= ir[15:12]; end
151			`DEC_RR: begin res <= rfoa - 32'd1; Rt <= ir[15:12]; end
152			`INC_RR: begin res <= rfoa + 32'd1; Rt <= ir[15:12]; end
153	20	robfinch
154	30	robfinch	`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
155			`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&\|ir[15:12]}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
156			`OR_IMM8: begin res <= rfoa \| {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; end
157			`AND_IMM8: begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
158			`EOR_IMM8: begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; end
159			`CMP_IMM8: begin res <= acc - {{24{ir[15]}},ir[15:8]}; end
160			`ifdef SUPPORT_SHIFT
161			`ASL_IMM8: begin b <= ir[20:16]; Rt <= ir[15:12]; state <= CALC; end
162			`LSR_IMM8: begin b <= ir[20:16]; Rt <= ir[15:12]; state <= CALC; end
163			`endif
164			`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
165			`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]} - {31'b0,df&~cf&\|ir[15:12]}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
166			`OR_IMM16: begin res <= rfoa \| {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; end
167			`AND_IMM16: begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
168			`EOR_IMM16: begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; end
169	20	robfinch
170	30	robfinch	`ADD_IMM32: begin res <= rfoa + ir[47:16] + {31'b0,df&cf}; Rt <= ir[15:12]; b <= ir[47:16]; end
171			`SUB_IMM32: begin res <= rfoa - ir[47:16] - {31'b0,df&~cf&\|ir[15:12]}; Rt <= ir[15:12]; b <= ir[47:16]; end
172			`OR_IMM32: begin res <= rfoa \| ir[47:16]; Rt <= ir[15:12]; end
173			`AND_IMM32: begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; b <= ir[47:16]; end
174			`EOR_IMM32: begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; end
175	20	robfinch
176	30	robfinch	`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: res <= ir[39:8];
177			`LDX_IMM16,`LDA_IMM16: res <= {{16{ir[23]}},ir[23:8]};
178			`LDX_IMM8,`LDA_IMM8: res <= {{24{ir[15]}},ir[15:8]};
179	20	robfinch
180	30	robfinch	`SUB_SP8: res <= isp - {{24{ir[15]}},ir[15:8]};
181			`SUB_SP16: res <= isp - {{16{ir[23]}},ir[23:8]};
182			`SUB_SP32: res <= isp - ir[39:8];
183	23	robfinch
184	30	robfinch	`CPX_IMM32: res <= x - ir[39:8];
185			`CPY_IMM32: res <= y - ir[39:8];
186
187	20	robfinch	`LDX_ZPX,`LDY_ZPX:
188			`begin`
189			`radr <= zpx32xy_address;`
190	21	robfinch	load_what <= `WORD_311;
191			`state <= LOAD_MAC1;`
192	20	robfinch	`end`
193			`ORB_ZPX:
194			`begin`
195			`Rt <= ir[19:16];`
196			`radr <= zpx32_address[31:2];`
197			`radr2LSB <= zpx32_address[1:0];`
198	21	robfinch	load_what <= `WORD_310;
199			`state <= LOAD_MAC1;`
200	20	robfinch	`end`
201			`LDX_ABS,`LDY_ABS:
202			`begin`
203			`radr <= ir[39:8];`
204	21	robfinch	load_what <= `WORD_311;
205			`state <= LOAD_MAC1;`
206	20	robfinch	`end`
207			`ORB_ABS:
208			`begin`
209			`Rt <= ir[15:12];`
210			`radr <= ir[47:18];`
211			`radr2LSB <= ir[17:16];`
212	21	robfinch	load_what <= `WORD_310;
213			`state <= LOAD_MAC1;`
214	20	robfinch	`end`
215			`LDX_ABSY,`LDY_ABSX:
216			`begin`
217			`radr <= absx32xy_address;`
218	21	robfinch	load_what <= `WORD_311;
219			`state <= LOAD_MAC1;`
220	20	robfinch	`end`
221			`ORB_ABSX:
222			`begin`
223			`Rt <= ir[19:16];`
224			`radr <= absx32_address[31:2];`
225			`radr2LSB <= absx32_address[1:0];`
226	21	robfinch	load_what <= `WORD_310;
227			`state <= LOAD_MAC1;`
228	20	robfinch	`end`
229			`ST_ZPX:
230			`begin`
231			`wadr <= zpx32_address;`
232	30	robfinch	store_what <= `STW_RFA;
233	20	robfinch	`state <= STORE1;`
234			`end`
235			`STB_ZPX:
236			`begin`
237			`wadr <= zpx32_address[31:2];`
238			`wadr2LSB <= zpx32_address[1:0];`
239	30	robfinch	store_what <= `STW_RFA8;
240	20	robfinch	`state <= STORE1;`
241			`end`
242	23	robfinch	`ST_DSP:
243			`begin`
244			`wadr <= {{24{ir[23]}},ir[23:16]} + isp;`
245	30	robfinch	store_what <= `STW_RFA;
246	23	robfinch	`state <= STORE1;`
247			`end`
248	20	robfinch	`ST_ABS:
249			`begin`
250			`wadr <= ir[47:16];`
251	30	robfinch	store_what <= `STW_RFA;
252	20	robfinch	`state <= STORE1;`
253			`end`
254			`STB_ABS:
255			`begin`
256			`wadr <= ir[47:18];`
257			`wadr2LSB <= ir[17:16];`
258	30	robfinch	store_what <= `STW_RFA8;
259	20	robfinch	`state <= STORE1;`
260			`end`
261			`ST_ABSX:
262			`begin`
263			`wadr <= absx32_address;`
264	30	robfinch	store_what <= `STW_RFA;
265	20	robfinch	`state <= STORE1;`
266			`end`
267			`STB_ABSX:
268			`begin`
269			`wadr <= absx32_address[31:2];`
270			`wadr2LSB <= absx32_address[1:0];`
271	30	robfinch	store_what <= `STW_RFA8;
272	20	robfinch	`state <= STORE1;`
273			`end`
274			`STX_ZPX:
275			`begin`
276	30	robfinch	`wadr <= zpx32xy_address;`
277			store_what <= `STW_X;
278	20	robfinch	`state <= STORE1;`
279			`end`
280			`STX_ABS:
281			`begin`
282			`wadr <= ir[39:8];`
283	30	robfinch	store_what <= `STW_X;
284	20	robfinch	`state <= STORE1;`
285			`end`
286			`STY_ZPX:
287			`begin`
288	30	robfinch	`wadr <= zpx32xy_address;`
289			store_what <= `STW_Y;
290	20	robfinch	`state <= STORE1;`
291			`end`
292			`STY_ABS:
293			`begin`
294			`wadr <= ir[39:8];`
295	30	robfinch	store_what <= `STW_Y;
296	20	robfinch	`state <= STORE1;`
297			`end`
298			`ADD_ZPX,`SUB_ZPX,`OR_ZPX,`AND_ZPX,`EOR_ZPX:
299			`begin`
300			`Rt <= ir[19:16];`
301			`radr <= zpx32_address;`
302	21	robfinch	load_what <= `WORD_310;
303			`state <= LOAD_MAC1;`
304	20	robfinch	`end`
305			`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
306			`begin`
307	30	robfinch	`radr <= zpx32xy_address;`
308	21	robfinch	load_what <= `WORD_310;
309			`state <= LOAD_MAC1;`
310	20	robfinch	`end`
311	23	robfinch	`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
312			`begin`
313			`Rt <= ir[15:12];`
314			`radr <= {{24{ir[23]}},ir[23:16]} + isp;`
315			load_what <= `WORD_310;
316			`state <= LOAD_MAC1;`
317			`end`
318	20	robfinch	`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
319			`begin`
320	25	robfinch	if (ir[7:0]!=`ST_IX) // for ST_IX, Rt=0
321	20	robfinch	`Rt <= ir[19:16];`
322	30	robfinch	`radr <= zpx32_address;`
323	21	robfinch	load_what <= `IA_310;
324	30	robfinch	store_what <= `STW_A;
325	21	robfinch	`state <= LOAD_MAC1;`
326	20	robfinch	`end`
327	25	robfinch	`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
328	20	robfinch	`begin`
329			`radr <= rfob;`
330	25	robfinch	`Rt <= ir[19:16];`
331			load_what <= `WORD_310;
332			`state <= LOAD_MAC1;`
333	20	robfinch	`end`
334	25	robfinch	`ST_RIND:
335			`begin`
336			`wadr <= rfob;`
337	30	robfinch	store_what <= `STW_RFA;
338	25	robfinch	`state <= STORE1;`
339			`end`
340	20	robfinch	`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
341			`begin`
342	25	robfinch	if (ir[7:0]!=`ST_IY) // for ST_IY, Rt=0
343	20	robfinch	`Rt <= ir[19:16];`
344	21	robfinch	`isIY <= 1'b1;`
345	30	robfinch	`radr <= ir[31:20];`
346	21	robfinch	load_what <= `IA_310;
347	30	robfinch	store_what <= `STW_A;
348	21	robfinch	`state <= LOAD_MAC1;`
349	20	robfinch	`end`
350			`ADD_ABS,`SUB_ABS,`OR_ABS,`AND_ABS,`EOR_ABS:
351			`begin`
352			`radr <= ir[47:16];`
353			`Rt <= ir[15:12];`
354	21	robfinch	load_what <= `WORD_310;
355			`state <= LOAD_MAC1;`
356	20	robfinch	`end`
357			`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
358			`begin`
359			`radr <= ir[39:8];`
360	21	robfinch	load_what <= `WORD_310;
361			`state <= LOAD_MAC1;`
362	20	robfinch	`end`
363			`ADD_ABSX,`SUB_ABSX,`OR_ABSX,`AND_ABSX,`EOR_ABSX:
364			`begin`
365	30	robfinch	`radr <= absx32_address;`
366	20	robfinch	`Rt <= ir[19:16];`
367	21	robfinch	load_what <= `WORD_310;
368			`state <= LOAD_MAC1;`
369	20	robfinch	`end`
370			`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
371			`begin`
372	30	robfinch	`radr <= absx32xy_address;`
373	21	robfinch	load_what <= `WORD_310;
374			`state <= LOAD_MAC1;`
375	20	robfinch	`end`
376	30	robfinch
377	20	robfinch	`CPX_ZPX:
378			`begin`
379	30	robfinch	`radr <= zpx32xy_address;`
380	21	robfinch	load_what <= `WORD_310;
381			`state <= LOAD_MAC1;`
382	20	robfinch	`end`
383			`CPY_ZPX:
384			`begin`
385	30	robfinch	`radr <= zpx32xy_address;`
386	21	robfinch	load_what <= `WORD_310;
387			`state <= LOAD_MAC1;`
388	20	robfinch	`end`
389			`CPX_ABS:
390			`begin`
391			`radr <= ir[39:8];`
392	21	robfinch	load_what <= `WORD_310;
393			`state <= LOAD_MAC1;`
394	20	robfinch	`end`
395			`CPY_ABS:
396			`begin`
397			`radr <= ir[39:8];`
398	21	robfinch	load_what <= `WORD_310;
399			`state <= LOAD_MAC1;`
400	20	robfinch	`end`
401			`BRK:
402			`begin`
403	30	robfinch	`bf <= !hwi;`
404			hist_capture <= `FALSE;
405	20	robfinch	`radr <= isp_dec;`
406			`wadr <= isp_dec;`
407	30	robfinch	`isp <= isp_dec;`
408			store_what <= `STW_PCHWI;
409			`state <= STORE1;`
410	20	robfinch	`end`
411	21	robfinch	`INT0,`INT1:
412			`begin`
413	30	robfinch	ir <= {8{`BRK}};
414	21	robfinch	`vect <= {vbr[31:9],ir[15:7],2'b00};`
415	30	robfinch	`state <= DECODE;`
416	21	robfinch	`end`
417	20	robfinch	`JMP:
418			`begin`
419			`pc[15:0] <= ir[23:8];`
420			`state <= IFETCH;`
421			`end`
422			`JML:
423			`begin`
424			`pc <= ir[39:8];`
425			`state <= IFETCH;`
426			`end`
427			`JMP_IND:
428			`begin`
429			`radr <= ir[39:8];`
430	21	robfinch	load_what <= `PC_310;
431			`state <= LOAD_MAC1;`
432	20	robfinch	`end`
433			`JMP_INDX:
434			`begin`
435			`radr <= ir[39:8] + x;`
436	21	robfinch	load_what <= `PC_310;
437			`state <= LOAD_MAC1;`
438	20	robfinch	`end`
439			`JMP_RIND:
440			`begin`
441			`pc <= rfoa;`
442			`res <= pc + 32'd2;`
443			`Rt <= ir[15:12];`
444			`state <= IFETCH;`
445			`end`
446			`JSR:
447			`begin`
448			`radr <= isp_dec;`
449			`wadr <= isp_dec;`
450	30	robfinch	`isp <= isp_dec;`
451			store_what <= `STW_DEF;
452			`wdat <= pc+{31'd1,suppress_pcinc[0]};`
453			`pc <= {pc[31:16],ir[23:8]};`
454			`state <= STORE1;`
455	20	robfinch	`end`
456			`JSR_RIND:
457			`begin`
458			`radr <= isp_dec;`
459			`wadr <= isp_dec;`
460			`wdat <= pc + 32'd2;`
461	30	robfinch	`isp <= isp_dec;`
462			store_what <= `STW_DEF;
463			`pc <= rfoa;`
464			`state <= STORE1;`
465	20	robfinch	`end`
466			`JSL:
467			`begin`
468			`radr <= isp_dec;`
469			`wadr <= isp_dec;`
470	30	robfinch	`isp <= isp_dec;`
471			store_what <= `STW_DEF;
472	25	robfinch	`wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;`
473	30	robfinch	`pc <= ir[39:8];`
474			`state <= STORE1;`
475	20	robfinch	`end`
476			`BSR:
477			`begin`
478			`radr <= isp_dec;`
479			`wadr <= isp_dec;`
480	30	robfinch	`isp <= isp_dec;`
481			store_what <= `STW_DEF;
482			`wdat <= pc+{31'd1,suppress_pcinc[0]};`
483			`pc <= pc + {{16{ir[23]}},ir[23:8]};`
484			`state <= STORE1;`
485	20	robfinch	`end`
486			`JSR_INDX:
487			`begin`
488	30	robfinch	`radr <= isp_dec;`
489			`wadr <= isp_dec;`
490	25	robfinch	`wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;`
491	20	robfinch	`cyc_o <= 1'b1;`
492			`stb_o <= 1'b1;`
493			`we_o <= 1'b1;`
494			`sel_o <= 4'hF;`
495			`adr_o <= {isp-32'd1,2'b00};`
496	25	robfinch	`dat_o <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;`
497	20	robfinch	`state <= JSR_INDX1;`
498			`end`
499			// `JSR16:
500			`// begin`

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