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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
task decode_tsk;
        begin
                first_ifetch <= `TRUE;
                Rt <= 4'h0;             // Default
                state <= IFETCH;
                pc <= pc + pc_inc;
                a <= rfoa;
                res <= alu_out;
                ttrig <= tf;
                // This case statement should include all opcodes or the opcode
                // will end up being treated as an undefined operation.
                case(ir9)
                `STP:   clk_en <= 1'b0;
                `NOP:   ;
//                              casex(ir[63:0])
//                              {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:      pc <= pcp8;
//                              {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:     pc <= pcp7;
//                              {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:       pc <= pcp6;
//                              {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}:  pc <= pcp5;
//                              {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}:     pc <= pcp4;
//                              {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}:        pc <= pcp3;
//                              {48'hxxxxxxxxxxxx,`NOP,`NOP}:   pc <= pcp2;
//                              {56'hxxxxxxxxxxxxxx,`NOP}:      pc <= pcp1;
//                              endcase
                `CLC:   cf <= 1'b0;
                `SEC:   cf <= 1'b1;
                `CLV:   vf <= 1'b0;
                `CLI:   im <= 1'b0;
                `CLD:   df <= 1'b0;
                `SED:   df <= 1'b1;
                `SEI:   im <= 1'b1;
                `WAI:   wai <= 1'b1;
                `TON:   tf <= 1'b1;
                `TOFF:  tf <= 1'b0;
                `HOFF:  hist_capture <= 1'b0;
                `EMM:   begin em <= 1'b1;
`ifdef SUPPORT_EM8
                                state <= BYTE_IFETCH;
`endif
                                end
                `DEX:   Rt <= 4'd2;
                                        // DEX/BNE accelerator
//                                      if (ir[15:8]==`BNE) begin
//                                              if (x!=32'd1) begin
//                                                      if (ir[23:16]==8'h01)
//                                                              pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;
//                                                      else
//                                                              pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1;
//                                              end
//                                              else begin
//                                                      if (ir[23:16]==8'h01)
//                                                              pc <= pcp5;
//                                                      else
//                                                              pc <= pcp3;
//                                              end
//                                      end
                `INX:   Rt <= 4'd2;
                `DEY:   Rt <= 4'd3;
                `INY:   Rt <= 4'd3;
                `DEA:   Rt <= 4'd1;
                `INA:   Rt <= 4'd1;
                `TSX:   Rt <= 4'd2;
                `TSA:   Rt <= 4'd1;
                `TXS:   ;
                `TXA:   Rt <= 4'd1;
                `TXY:   Rt <= 4'd3;
                `TAX:   Rt <= 4'd2;
                `TAY:   Rt <= 4'd3;
                `TAS:   ;
                `TYA:   Rt <= 4'd1;
                `TYX:   Rt <= 4'd2;
                `TRS:           ;
                `TSR:           begin
                                                Rt <= ir[15:12];
                                                case(ir[11:8])
                                                4'h0:   ;
                                                4'h2:   ;
                                                4'h3:   ;
                                                4'h4:   ;
                                                4'h5:   lfsr <= {lfsr[30:0],lfsr_fb};
                                                4'd7:   ;
                                                4'h8:   ;
                                                4'h9:   ;
                                                4'hA:   history_ndx <= history_ndx + 6'd1;
                                                4'hE:   ;
                                                4'hF:   ;
                                                default:        ;
                                                endcase
                                        end
                `ASL_ACC:       Rt <= 4'd1;
                `ROL_ACC:       Rt <= 4'd1;
                `LSR_ACC:       Rt <= 4'd1;
                `ROR_ACC:       Rt <= 4'd1;
 
                `RR:
                        begin
                                Rt <= ir[19:16];
                                case(ir[23:20])
                                `ADD_RR:        b <= rfob;
                                `SUB_RR:        b <= rfob;
                                `AND_RR:        b <= rfob;      // for bit flags
                                `OR_RR:         b <= rfob;
                                `EOR_RR:        b <= rfob;
                                `MUL_RR:        begin b <= rfob; state <= MULDIV1; end
                                `MULS_RR:       begin b <= rfob; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                                `DIV_RR:        begin b <= rfob; state <= MULDIV1; end
                                `DIVS_RR:       begin b <= rfob; state <= MULDIV1; end
                                `MOD_RR:        begin b <= rfob; state <= MULDIV1; end
                                `MODS_RR:       begin b <= rfob; state <= MULDIV1; end
`endif
`ifdef SUPPORT_SHIFT
                                `ASL_RRR:       begin b <= rfob; state <= CALC; end
                                `LSR_RRR:       begin b <= rfob; state <= CALC; end
`endif
                                default:
                                        begin
                                                Rt <= 4'h0;
                                                pg2 <= `FALSE;
                                                ir <= {8{`BRK}};
                                                hwi <= `TRUE;
                                                vect <= {vbr[31:9],9'd495,2'b00};
                                                pc <= pc;               // override the pc increment
                                                state <= DECODE;
                                        end
                                endcase
                        end
                `LD_RR:         Rt <= ir[15:12];
                `ASL_RR:        Rt <= ir[15:12];
                `ROL_RR:        Rt <= ir[15:12];
                `LSR_RR:        Rt <= ir[15:12];
                `ROR_RR:        Rt <= ir[15:12];
                `DEC_RR:        Rt <= ir[15:12];
                `INC_RR:        Rt <= ir[15:12];
 
                `ADD_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `SUB_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `MUL_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
                `MOD_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
`endif
                `OR_IMM8:       begin Rt <= ir[15:12]; end
                `AND_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `EOR_IMM8:      begin Rt <= ir[15:12]; end
                `CMP_IMM8:      ;
`ifdef SUPPORT_SHIFT
                `ASL_IMM8:      begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
                `LSR_IMM8:      begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
`endif
 
                `ADD_IMM16:     begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
                `SUB_IMM16:     begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
                `MUL_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
                `MOD_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
`endif
                `OR_IMM16:      begin Rt <= ir[15:12]; end
                `AND_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
                `EOR_IMM16:     begin Rt <= ir[15:12]; end
 
                `ADD_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; end
                `SUB_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; end
                `MUL_IMM16:     begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
                `MOD_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
`endif
                `OR_IMM32:      begin Rt <= ir[15:12]; end
                `AND_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; end
                `EOR_IMM32:     begin Rt <= ir[15:12]; end
 
                `LDA_IMM32:     Rt <= 4'd1;
                `LDX_IMM32:     Rt <= 4'd2;
                `LDY_IMM32: Rt <= 4'd3;
                `LDA_IMM16:     Rt <= 4'd1;
                `LDX_IMM16: Rt <= 4'd2;
                `LDA_IMM8: Rt <= 4'd1;
                `LDX_IMM8: Rt <= 4'd2;
 
                `SUB_SP8:       ;
                `SUB_SP16:      ;
                `SUB_SP32:      ;
 
                `CPX_IMM32:     ;
                `CPY_IMM32:     ;
 
                `LDX_ZPX:
                        begin
                                Rt <= 4'd2;
                                radr <= zpx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `LDY_ZPX:
                        begin
                                Rt <= 4'd3;
                                radr <= zpx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address[31:2];
                                radr2LSB <= zpx32_address[1:0];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LDX_ABS:
                        begin
                                Rt <= 4'd2;
                                radr <= ir[39:8];
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `LDY_ABS:
                        begin
                                Rt <= 4'd3;
                                radr <= ir[39:8];
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ABS:
                        begin
                                Rt <= ir[15:12];
                                radr <= ir[47:18];
                                radr2LSB <= ir[17:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LDX_ABSY:
                        begin
                                Rt <= 4'd2;
                                radr <= absx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `LDY_ABSX:
                        begin
                                Rt <= 4'd3;
                                radr <= absx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ABSX:
                        begin
                                Rt <= ir[19:16];
                                radr <= absx32_address[31:2];
                                radr2LSB <= absx32_address[1:0];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ST_ZPX:
                        begin
                                wadr <= zpx32_address;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ZPX:
                        begin
                                wadr <= zpx32_address[31:2];
                                wadr2LSB <= zpx32_address[1:0];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `ST_DSP:
                        begin
                                wadr <= {{24{ir[23]}},ir[23:16]} + isp;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `ST_ABS:
                        begin
                                wadr <= ir[47:16];
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ABS:
                        begin
                                wadr <= ir[47:18];
                                wadr2LSB <= ir[17:16];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `ST_ABSX:
                        begin
                                wadr <= absx32_address;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ABSX:
                        begin
                                wadr <= absx32_address[31:2];
                                wadr2LSB <= absx32_address[1:0];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `STX_ZPX:
                        begin
                                wadr <= zpx32xy_address;
                                store_what <= `STW_X;
                                state <= STORE1;
                        end
                `STX_ABS:
                        begin
                                wadr <= ir[39:8];
                                store_what <= `STW_X;
                                state <= STORE1;
                        end
                `STY_ZPX:
                        begin
                                wadr <= zpx32xy_address;
                                store_what <= `STW_Y;
                                state <= STORE1;
                        end
                `STY_ABS:
                        begin
                                wadr <= ir[39:8];
                                store_what <= `STW_Y;
                                state <= STORE1;
                        end
                `ADD_ZPX,`SUB_ZPX,`AND_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                // Trim a clock cycle off of loads by testing for Ra = 0.
                `OR_ZPX,`EOR_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BMS_ZPX,`BMC_ZPX,`BMF_ZPX,`BMT_ZPX:
                        begin
                                radr <= zpx32xy_address + acc[31:5];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
                        begin
                                Rt <= ir[15:12];
                                radr <= {{24{ir[23]}},ir[23:16]} + isp;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
                        begin
                                if (ir[7:0]!=`ST_IX)     // for ST_IX, Rt=0
                                        Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= `IA_310;
                                store_what <= `STW_A;
                                state <= LOAD_MAC1;
                        end
                `ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
                        begin
                                radr <= rfob;
                                Rt <= ir[19:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ST_RIND:
                        begin
                                wadr <= rfob;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
                        begin
                                if (ir[7:0]!=`ST_IY)     // for ST_IY, Rt=0
                                        Rt <= ir[19:16];
                                isIY <= 1'b1;
                                radr <= ir[31:20];
                                load_what <= `IA_310;
                                store_what <= `STW_A;
                                state <= LOAD_MAC1;
                        end
                `OR_ABS,`EOR_ABS:
                        begin
                                radr <= ir[47:16];
                                Rt <= ir[15:12];
                                load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_ABS,`SUB_ABS,`AND_ABS:
                        begin
                                radr <= ir[47:16];
                                Rt <= ir[15:12];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
                        begin
                                radr <= ir[39:8] + acc[31:5];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_ABSX,`SUB_ABSX,`AND_ABSX:
                        begin
                                radr <= absx32_address;
                                Rt <= ir[19:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `OR_ABSX,`EOR_ABSX:
                        begin
                                radr <= absx32_address;
                                Rt <= ir[19:16];
                                load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
                        begin
                                radr <= absx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BMS_ABSX,`BMC_ABSX,`BMF_ABSX,`BMT_ABSX:
                        begin
                                radr <= absx32xy_address + acc[31:5];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
 
                `CPX_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPY_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPX_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPY_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BRK:
                        begin
                                bf <= !hwi;
                                km <= `TRUE;
                                hist_capture <= `FALSE;
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_PCHWI;
                                state <= STORE1;
                        end
                `INT0,`INT1:
                        begin
                                pg2 <= `FALSE;
                                ir <= {8{`BRK}};
                                vect <= {vbr[31:9],ir[15:7],2'b00};
                                state <= DECODE;
                        end
                `JMP:
                        begin
                                pc[15:0] <= ir[23:8];
                                state <= IFETCH;
                        end
                `JML:
                        begin
                                pc <= ir[39:8];
                                state <= IFETCH;
                        end
                `JMP_IND:
                        begin
                                radr <= ir[39:8];
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                        end
                `JMP_INDX:
                        begin
                                radr <= ir[39:8] + x;
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                        end
                `JMP_RIND:
                        begin
                                pc <= rfoa;
                                res <= pc + 32'd2;
                                Rt <= ir[15:12];
                                state <= IFETCH;
                        end
                `JSR:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= pc+{31'd1,suppress_pcinc[0]};
                                pc <= {pc[31:16],ir[23:8]};
                                state <= STORE1;
                        end
                `JSR_RIND:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                wdat <= pc + 32'd2;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                pc <= rfoa;
                                state <= STORE1;
                        end
                `JSL,`JSR_INDX,`JSR_IND:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
                                pc <= ir[39:8];         // This pc assignment will be overridden later by JSR_INDX
                                state <= STORE1;
                        end
                `BSR:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= pc+{31'd1,suppress_pcinc[0]};
                                pc <= pc + {{16{ir[23]}},ir[23:8]};
                                state <= STORE1;
                        end
                `RTS,`RTL:
                                begin
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                end
                `RTI:   begin
                                hist_capture <= `TRUE;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `SR_310;
                                state <= LOAD_MAC1;
                                end
                `BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA,
                `BGT,`BGE,`BLT,`BLE,`BHI,`BLS:
                        begin
                                if (ir[15:8]==8'h00) begin
                                        pg2 <= `FALSE;
                                        ir <= {8{`BRK}};
                                        pc <= pc;               // override the pc increment
                                        vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
                                        state <= DECODE;
                                end
                                else if (ir[15:8]==8'h1) begin
                                        if (takb)
                                                pc <= pc + {{16{ir[31]}},ir[31:16]};
                                        else
                                                pc <= pcp4;
                                end
                                else begin
                                        if (takb)
                                                pc <= pc + {{24{ir[15]}},ir[15:8]};
                                        else
                                                pc <= pcp2;
                                end
                        end
                `BRL:
                        begin
                                if (ir[23:8]==16'h0000) begin
                                        pg2 <= `FALSE;
                                        ir <= {8{`BRK}};
                                        vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
                                        pc <= pc;               // override the pc increment
                                        state <= DECODE;
                                end
                                else begin
                                        pc <= pc + {{16{ir[23]}},ir[23:8]};
                                        state <= IFETCH;
                                end
                        end
`ifdef SUPPORT_EXEC
                `EXEC,`ATNI:
                        begin
                                exbuf[31:0] <= rfoa;
                                exbuf[63:32] <= rfob;
                        end
`endif
                `PHP:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_SR;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHA:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_ACC;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHX:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_X;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHY:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_Y;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PUSH:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_A;
                                state <= STORE1;
                                isp <= isp_dec;
                        end
                `PUSHA:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                ir[11:8] <= 4'd1;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                                isp <= isp_dec;
                        end
                `PLP:
                        begin
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `SR_310;
                                state <= LOAD_MAC1;
                        end
                `PLA:
                        begin
                                Rt <= 4'd1;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `PLX:
                        begin
                                Rt <= 4'd2;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `PLY:
                        begin
                                Rt <= 4'd3;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `POP:
                        begin
                                Rt <= ir[15:12];
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `POPA:
                        begin
                                Rt <= 4'd15;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
`ifdef SUPPORT_STRING
                `MVN:
                        begin
                                Rt <= 4'd3;
                                radr <= x;
                                res <= x + 32'd1;
                                load_what <= `WORD_312;
                                state <= LOAD_MAC1;
                        end
                `MVP:
                        begin
                                Rt <= 4'd3;
                                radr <= x;
                                res <= x - 32'd1;
                                load_what <= `WORD_312;
                                state <= LOAD_MAC1;
                        end
                `STS:
                        begin
                                Rt <= 4'd3;
                                radr <= y;
                                wadr <= y;
                                store_what <= `STW_X;
                                acc <= acc - 32'd1;
                                state <= STORE1;
                        end
                `CMPS:
                        begin
                                Rt <= 4'd3;
                                radr <= x;
                                res <= x + 32'd1;
                                load_what <= `WORD_313;
                                state <= LOAD_MAC1;
                        end
`endif
                `PG2:   begin
                                        pg2 <= `TRUE;
                                        ir <= ir[63:8];
                                        state <= DECODE;
                                end
                default:        // unimplemented opcode
                        begin
                                res <= 32'd0;
                                pg2 <= `FALSE;
                                ir <= {8{`BRK}};
                                hwi <= `TRUE;
                                vect <= {vbr[31:9],9'd495,2'b00};
                                pc <= pc;               // override the pc increment
                                state <= DECODE;
                        end
                endcase
        end
endtask

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	32	robfinch	`task decode_tsk;`
24	20	robfinch	`begin`
25			first_ifetch <= `TRUE;
26			`Rt <= 4'h0; // Default`
27			`state <= IFETCH;`
28	30	robfinch	`pc <= pc + pc_inc;`
29			`a <= rfoa;`
30	32	robfinch	`res <= alu_out;`
31			`ttrig <= tf;`
32	30	robfinch	`// This case statement should include all opcodes or the opcode`
33			`// will end up being treated as an undefined operation.`
34	32	robfinch	`case(ir9)`
35	30	robfinch	`STP: clk_en <= 1'b0;
36			`NOP: ;
37			`// casex(ir[63:0])`
38			// {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8;
39			// {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7;
40			// {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp6;
41			// {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp5;
42			// {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}: pc <= pcp4;
43			// {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}: pc <= pcp3;
44			// {48'hxxxxxxxxxxxx,`NOP,`NOP}: pc <= pcp2;
45			// {56'hxxxxxxxxxxxxxx,`NOP}: pc <= pcp1;
46			`// endcase`
47			`CLC: cf <= 1'b0;
48			`SEC: cf <= 1'b1;
49			`CLV: vf <= 1'b0;
50			`CLI: im <= 1'b0;
51			`CLD: df <= 1'b0;
52			`SED: df <= 1'b1;
53			`SEI: im <= 1'b1;
54			`WAI: wai <= 1'b1;
55	32	robfinch	`TON: tf <= 1'b1;
56			`TOFF: tf <= 1'b0;
57			`HOFF: hist_capture <= 1'b0;
58			`EMM: begin em <= 1'b1;
59			`ifdef SUPPORT_EM8
60			`state <= BYTE_IFETCH;`
61			`endif
62			`end`
63			`DEX: Rt <= 4'd2;
64	25	robfinch	`// DEX/BNE accelerator`
65			// if (ir[15:8]==`BNE) begin
66			`// if (x!=32'd1) begin`
67			`// if (ir[23:16]==8'h01)`
68			`// pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;`
69			`// else`
70			`// pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1;`
71			`// end`
72			`// else begin`
73			`// if (ir[23:16]==8'h01)`
74			`// pc <= pcp5;`
75			`// else`
76			`// pc <= pcp3;`
77			`// end`
78			`// end`
79	32	robfinch	`INX: Rt <= 4'd2;
80			`DEY: Rt <= 4'd3;
81			`INY: Rt <= 4'd3;
82			`DEA: Rt <= 4'd1;
83			`INA: Rt <= 4'd1;
84			`TSX: Rt <= 4'd2;
85			`TSA: Rt <= 4'd1;
86			`TXS: ;
87			`TXA: Rt <= 4'd1;
88			`TXY: Rt <= 4'd3;
89			`TAX: Rt <= 4'd2;
90			`TAY: Rt <= 4'd3;
91			`TAS: ;
92			`TYA: Rt <= 4'd1;
93			`TYX: Rt <= 4'd2;
94			`TRS: ;
95	20	robfinch	`TSR: begin
96			`Rt <= ir[15:12];`
97			`case(ir[11:8])`
98	32	robfinch	`4'h0: ;`
99			`4'h2: ;`
100			`4'h3: ;`
101			`4'h4: ;`
102			`4'h5: lfsr <= {lfsr[30:0],lfsr_fb};`
103			`4'd7: ;`
104			`4'h8: ;`
105			`4'h9: ;`
106			`4'hA: history_ndx <= history_ndx + 6'd1;`
107			`4'hE: ;`
108			`4'hF: ;`
109			`default: ;`
110	20	robfinch	`endcase`
111			`end`
112	32	robfinch	`ASL_ACC: Rt <= 4'd1;
113			`ROL_ACC: Rt <= 4'd1;
114			`LSR_ACC: Rt <= 4'd1;
115			`ROR_ACC: Rt <= 4'd1;
116	20	robfinch
117			`RR:
118			`begin`
119	30	robfinch	`Rt <= ir[19:16];`
120	20	robfinch	`case(ir[23:20])`
121	32	robfinch	`ADD_RR: b <= rfob;
122			`SUB_RR: b <= rfob;
123			`AND_RR: b <= rfob; // for bit flags
124			`OR_RR: b <= rfob;
125			`EOR_RR: b <= rfob;
126			`MUL_RR: begin b <= rfob; state <= MULDIV1; end
127			`MULS_RR: begin b <= rfob; state <= MULDIV1; end
128	30	robfinch	`ifdef SUPPORT_DIVMOD
129	32	robfinch	`DIV_RR: begin b <= rfob; state <= MULDIV1; end
130			`DIVS_RR: begin b <= rfob; state <= MULDIV1; end
131			`MOD_RR: begin b <= rfob; state <= MULDIV1; end
132			`MODS_RR: begin b <= rfob; state <= MULDIV1; end
133	30	robfinch	`endif
134			`ifdef SUPPORT_SHIFT
135			`ASL_RRR: begin b <= rfob; state <= CALC; end
136			`LSR_RRR: begin b <= rfob; state <= CALC; end
137			`endif
138			`default:`
139			`begin`
140			`Rt <= 4'h0;`
141	32	robfinch	pg2 <= `FALSE;
142	30	robfinch	ir <= {8{`BRK}};
143			hwi <= `TRUE;
144			`vect <= {vbr[31:9],9'd495,2'b00};`
145			`pc <= pc; // override the pc increment`
146			`state <= DECODE;`
147			`end`
148	20	robfinch	`endcase`
149			`end`
150	32	robfinch	`LD_RR: Rt <= ir[15:12];
151			`ASL_RR: Rt <= ir[15:12];
152			`ROL_RR: Rt <= ir[15:12];
153			`LSR_RR: Rt <= ir[15:12];
154			`ROR_RR: Rt <= ir[15:12];
155			`DEC_RR: Rt <= ir[15:12];
156			`INC_RR: Rt <= ir[15:12];
157	20	robfinch
158	32	robfinch	`ADD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
159			`SUB_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
160			`MUL_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
161			`ifdef SUPPORT_DIVMOD
162			`DIV_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
163			`MOD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
164			`endif
165			`OR_IMM8: begin Rt <= ir[15:12]; end
166			`AND_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
167			`EOR_IMM8: begin Rt <= ir[15:12]; end
168			`CMP_IMM8: ;
169	30	robfinch	`ifdef SUPPORT_SHIFT
170	32	robfinch	`ASL_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
171			`LSR_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
172	30	robfinch	`endif
173	32	robfinch
174			`ADD_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
175			`SUB_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
176			`MUL_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
177			`ifdef SUPPORT_DIVMOD
178			`DIV_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
179			`MOD_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
180			`endif
181			`OR_IMM16: begin Rt <= ir[15:12]; end
182			`AND_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
183			`EOR_IMM16: begin Rt <= ir[15:12]; end
184	20	robfinch
185	32	robfinch	`ADD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
186			`SUB_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
187			`MUL_IMM16: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
188			`ifdef SUPPORT_DIVMOD
189			`DIV_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
190			`MOD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
191			`endif
192			`OR_IMM32: begin Rt <= ir[15:12]; end
193			`AND_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
194			`EOR_IMM32: begin Rt <= ir[15:12]; end
195	20	robfinch
196	32	robfinch	`LDA_IMM32: Rt <= 4'd1;
197			`LDX_IMM32: Rt <= 4'd2;
198			`LDY_IMM32: Rt <= 4'd3;
199			`LDA_IMM16: Rt <= 4'd1;
200			`LDX_IMM16: Rt <= 4'd2;
201			`LDA_IMM8: Rt <= 4'd1;
202			`LDX_IMM8: Rt <= 4'd2;
203	20	robfinch
204	32	robfinch	`SUB_SP8: ;
205			`SUB_SP16: ;
206			`SUB_SP32: ;
207	23	robfinch
208	32	robfinch	`CPX_IMM32: ;
209			`CPY_IMM32: ;
210	30	robfinch
211	32	robfinch	`LDX_ZPX:
212	20	robfinch	`begin`
213	32	robfinch	`Rt <= 4'd2;`
214	20	robfinch	`radr <= zpx32xy_address;`
215	21	robfinch	load_what <= `WORD_311;
216			`state <= LOAD_MAC1;`
217	20	robfinch	`end`
218	32	robfinch	`LDY_ZPX:
219			`begin`
220			`Rt <= 4'd3;`
221			`radr <= zpx32xy_address;`
222			load_what <= `WORD_311;
223			`state <= LOAD_MAC1;`
224			`end`
225	20	robfinch	`ORB_ZPX:
226			`begin`
227			`Rt <= ir[19:16];`
228			`radr <= zpx32_address[31:2];`
229			`radr2LSB <= zpx32_address[1:0];`
230	21	robfinch	load_what <= `WORD_310;
231			`state <= LOAD_MAC1;`
232	20	robfinch	`end`
233	32	robfinch	`LDX_ABS:
234	20	robfinch	`begin`
235	32	robfinch	`Rt <= 4'd2;`
236	20	robfinch	`radr <= ir[39:8];`
237	21	robfinch	load_what <= `WORD_311;
238			`state <= LOAD_MAC1;`
239	20	robfinch	`end`
240	32	robfinch	`LDY_ABS:
241			`begin`
242			`Rt <= 4'd3;`
243			`radr <= ir[39:8];`
244			load_what <= `WORD_311;
245			`state <= LOAD_MAC1;`
246			`end`
247	20	robfinch	`ORB_ABS:
248			`begin`
249			`Rt <= ir[15:12];`
250			`radr <= ir[47:18];`
251			`radr2LSB <= ir[17:16];`
252	21	robfinch	load_what <= `WORD_310;
253			`state <= LOAD_MAC1;`
254	20	robfinch	`end`
255	32	robfinch	`LDX_ABSY:
256	20	robfinch	`begin`
257	32	robfinch	`Rt <= 4'd2;`
258	20	robfinch	`radr <= absx32xy_address;`
259	21	robfinch	load_what <= `WORD_311;
260			`state <= LOAD_MAC1;`
261	20	robfinch	`end`
262	32	robfinch	`LDY_ABSX:
263			`begin`
264			`Rt <= 4'd3;`
265			`radr <= absx32xy_address;`
266			load_what <= `WORD_311;
267			`state <= LOAD_MAC1;`
268			`end`
269	20	robfinch	`ORB_ABSX:
270			`begin`
271			`Rt <= ir[19:16];`
272			`radr <= absx32_address[31:2];`
273			`radr2LSB <= absx32_address[1:0];`
274	21	robfinch	load_what <= `WORD_310;
275			`state <= LOAD_MAC1;`
276	20	robfinch	`end`
277			`ST_ZPX:
278			`begin`
279			`wadr <= zpx32_address;`
280	30	robfinch	store_what <= `STW_RFA;
281	20	robfinch	`state <= STORE1;`
282			`end`
283			`STB_ZPX:
284			`begin`
285			`wadr <= zpx32_address[31:2];`
286			`wadr2LSB <= zpx32_address[1:0];`
287	30	robfinch	store_what <= `STW_RFA8;
288	20	robfinch	`state <= STORE1;`
289			`end`
290	23	robfinch	`ST_DSP:
291			`begin`
292			`wadr <= {{24{ir[23]}},ir[23:16]} + isp;`
293	30	robfinch	store_what <= `STW_RFA;
294	23	robfinch	`state <= STORE1;`
295			`end`
296	20	robfinch	`ST_ABS:
297			`begin`
298			`wadr <= ir[47:16];`
299	30	robfinch	store_what <= `STW_RFA;
300	20	robfinch	`state <= STORE1;`
301			`end`
302			`STB_ABS:
303			`begin`
304			`wadr <= ir[47:18];`
305			`wadr2LSB <= ir[17:16];`
306	30	robfinch	store_what <= `STW_RFA8;
307	20	robfinch	`state <= STORE1;`
308			`end`
309			`ST_ABSX:
310			`begin`
311			`wadr <= absx32_address;`
312	30	robfinch	store_what <= `STW_RFA;
313	20	robfinch	`state <= STORE1;`
314			`end`
315			`STB_ABSX:
316			`begin`
317			`wadr <= absx32_address[31:2];`
318			`wadr2LSB <= absx32_address[1:0];`
319	30	robfinch	store_what <= `STW_RFA8;
320	20	robfinch	`state <= STORE1;`
321			`end`
322			`STX_ZPX:
323			`begin`
324	30	robfinch	`wadr <= zpx32xy_address;`
325			store_what <= `STW_X;
326	20	robfinch	`state <= STORE1;`
327			`end`
328			`STX_ABS:
329			`begin`
330			`wadr <= ir[39:8];`
331	30	robfinch	store_what <= `STW_X;
332	20	robfinch	`state <= STORE1;`
333			`end`
334			`STY_ZPX:
335			`begin`
336	30	robfinch	`wadr <= zpx32xy_address;`
337			store_what <= `STW_Y;
338	20	robfinch	`state <= STORE1;`
339			`end`
340			`STY_ABS:
341			`begin`
342			`wadr <= ir[39:8];`
343	30	robfinch	store_what <= `STW_Y;
344	20	robfinch	`state <= STORE1;`
345			`end`
346	32	robfinch	`ADD_ZPX,`SUB_ZPX,`AND_ZPX:
347	20	robfinch	`begin`
348			`Rt <= ir[19:16];`
349			`radr <= zpx32_address;`
350	21	robfinch	load_what <= `WORD_310;
351			`state <= LOAD_MAC1;`
352	20	robfinch	`end`
353	32	robfinch	`// Trim a clock cycle off of loads by testing for Ra = 0.`
354			`OR_ZPX,`EOR_ZPX:
355			`begin`
356			`Rt <= ir[19:16];`
357			`radr <= zpx32_address;`
358			load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
359			`state <= LOAD_MAC1;`
360			`end`
361	20	robfinch	`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
362			`begin`
363	30	robfinch	`radr <= zpx32xy_address;`
364	21	robfinch	load_what <= `WORD_310;
365			`state <= LOAD_MAC1;`
366	20	robfinch	`end`
367	32	robfinch	`BMS_ZPX,`BMC_ZPX,`BMF_ZPX,`BMT_ZPX:
368			`begin`
369			`radr <= zpx32xy_address + acc[31:5];`
370			load_what <= `WORD_310;
371			`state <= LOAD_MAC1;`
372			`end`
373	23	robfinch	`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
374			`begin`
375			`Rt <= ir[15:12];`
376			`radr <= {{24{ir[23]}},ir[23:16]} + isp;`
377			load_what <= `WORD_310;
378			`state <= LOAD_MAC1;`
379			`end`
380	20	robfinch	`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
381			`begin`
382	25	robfinch	if (ir[7:0]!=`ST_IX) // for ST_IX, Rt=0
383	20	robfinch	`Rt <= ir[19:16];`
384	30	robfinch	`radr <= zpx32_address;`
385	21	robfinch	load_what <= `IA_310;
386	30	robfinch	store_what <= `STW_A;
387	21	robfinch	`state <= LOAD_MAC1;`
388	20	robfinch	`end`
389	25	robfinch	`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
390	20	robfinch	`begin`
391			`radr <= rfob;`
392	25	robfinch	`Rt <= ir[19:16];`
393			load_what <= `WORD_310;
394			`state <= LOAD_MAC1;`
395	20	robfinch	`end`
396	25	robfinch	`ST_RIND:
397			`begin`
398			`wadr <= rfob;`
399	30	robfinch	store_what <= `STW_RFA;
400	25	robfinch	`state <= STORE1;`
401			`end`
402	20	robfinch	`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
403			`begin`
404	25	robfinch	if (ir[7:0]!=`ST_IY) // for ST_IY, Rt=0
405	20	robfinch	`Rt <= ir[19:16];`
406	21	robfinch	`isIY <= 1'b1;`
407	30	robfinch	`radr <= ir[31:20];`
408	21	robfinch	load_what <= `IA_310;
409	30	robfinch	store_what <= `STW_A;
410	21	robfinch	`state <= LOAD_MAC1;`
411	20	robfinch	`end`
412	32	robfinch	`OR_ABS,`EOR_ABS:
413	20	robfinch	`begin`
414			`radr <= ir[47:16];`
415			`Rt <= ir[15:12];`
416	32	robfinch	load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
417			`state <= LOAD_MAC1;`
418			`end`
419			`ADD_ABS,`SUB_ABS,`AND_ABS:
420			`begin`
421			`radr <= ir[47:16];`
422			`Rt <= ir[15:12];`
423	21	robfinch	load_what <= `WORD_310;
424			`state <= LOAD_MAC1;`
425	20	robfinch	`end`
426			`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
427			`begin`
428			`radr <= ir[39:8];`
429	21	robfinch	load_what <= `WORD_310;
430			`state <= LOAD_MAC1;`
431	20	robfinch	`end`
432	32	robfinch	`BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
433	20	robfinch	`begin`
434	32	robfinch	`radr <= ir[39:8] + acc[31:5];`
435			load_what <= `WORD_310;
436			`state <= LOAD_MAC1;`
437			`end`
438			`ADD_ABSX,`SUB_ABSX,`AND_ABSX:
439			`begin`
440	30	robfinch	`radr <= absx32_address;`
441	20	robfinch	`Rt <= ir[19:16];`
442	21	robfinch	load_what <= `WORD_310;
443			`state <= LOAD_MAC1;`
444	20	robfinch	`end`
445	32	robfinch	`OR_ABSX,`EOR_ABSX:
446			`begin`
447			`radr <= absx32_address;`
448			`Rt <= ir[19:16];`
449			load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
450			`state <= LOAD_MAC1;`
451			`end`
452	20	robfinch	`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
453			`begin`
454	30	robfinch	`radr <= absx32xy_address;`
455	21	robfinch	load_what <= `WORD_310;
456			`state <= LOAD_MAC1;`
457	20	robfinch	`end`
458	32	robfinch	`BMS_ABSX,`BMC_ABSX,`BMF_ABSX,`BMT_ABSX:
459			`begin`
460			`radr <= absx32xy_address + acc[31:5];`
461			load_what <= `WORD_310;
462			`state <= LOAD_MAC1;`
463			`end`
464	30	robfinch
465	20	robfinch	`CPX_ZPX:
466			`begin`
467	30	robfinch	`radr <= zpx32xy_address;`
468	21	robfinch	load_what <= `WORD_310;
469			`state <= LOAD_MAC1;`
470	20	robfinch	`end`
471			`CPY_ZPX:
472			`begin`
473	30	robfinch	`radr <= zpx32xy_address;`
474	21	robfinch	load_what <= `WORD_310;
475			`state <= LOAD_MAC1;`
476	20	robfinch	`end`
477			`CPX_ABS:
478			`begin`
479			`radr <= ir[39:8];`
480	21	robfinch	load_what <= `WORD_310;
481			`state <= LOAD_MAC1;`
482	20	robfinch	`end`
483			`CPY_ABS:
484			`begin`
485			`radr <= ir[39:8];`
486	21	robfinch	load_what <= `WORD_310;
487			`state <= LOAD_MAC1;`
488	20	robfinch	`end`
489			`BRK:
490			`begin`
491	30	robfinch	`bf <= !hwi;`
492	32	robfinch	km <= `TRUE;
493	30	robfinch	hist_capture <= `FALSE;
494	20	robfinch	`radr <= isp_dec;`
495			`wadr <= isp_dec;`
496	30	robfinch	`isp <= isp_dec;`
497			store_what <= `STW_PCHWI;
498			`state <= STORE1;`
499	20	robfinch	`end`
500	21	robfinch	`INT0,`INT1:

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