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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [ifetch.v] - Blame information for rev 23

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1 20 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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IFETCH:
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        begin
25 23 robfinch
                opc <= pc;
26 20 robfinch
                if (nmi_edge & !imiss & gie) begin      // imiss indicates cache controller is active and this state is in a waiting loop
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                        nmi_edge <= 1'b0;
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                        wai <= 1'b0;
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                        bf <= 1'b0;
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                        if (em & !nmoi) begin
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                                radr <= {spage[31:8],sp[7:2]};
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                                radr2LSB <= sp[1:0];
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                                wadr <= {spage[31:8],sp[7:2]};
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                                wadr2LSB <= sp[1:0];
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                                wdat <= {4{pc[31:24]}};
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                                cyc_o <= 1'b1;
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                                stb_o <= 1'b1;
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                                we_o <= 1'b1;
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                                case(sp[1:0])
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                                2'd0:   sel_o <= 4'b0001;
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                                2'd1:   sel_o <= 4'b0010;
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                                2'd2:   sel_o <= 4'b0100;
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                                2'd3:   sel_o <= 4'b1000;
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                                endcase
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                                adr_o <= {spage[31:8],sp[7:2],2'b00};
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                                dat_o <= {4{pc[31:24]}};
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                                sp <= sp_dec;
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                                vect <= `BYTE_NMI_VECT;
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                                state <= BYTE_IRQ1;
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                        end
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                        else begin
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                                radr <= isp_dec;
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                                wadr <= isp_dec;
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                                wdat <= pc;
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                                cyc_o <= 1'b1;
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                                stb_o <= 1'b1;
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                                we_o <= 1'b1;
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                                sel_o <= 4'hF;
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                                adr_o <= {isp_dec,2'b00};
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                                dat_o <= pc;
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                                vect <= `NMI_VECT;
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                                state <= IRQ1;
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                        end
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                end
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                else if (irq_i && !imiss & gie) begin
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                        if (im) begin
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                                wai <= 1'b0;
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                                if (unCachedInsn) begin
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                                        if (bhit) begin
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                                                ir <= ibuf;
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                                                state <= em ? BYTE_DECODE : DECODE;
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                                        end
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                                        else
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                                                imiss <= `TRUE;
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                                end
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                                else begin
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                                        if (ihit) begin
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                                                ir <= insn;
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                                                state <= em ? BYTE_DECODE : DECODE;
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                                        end
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                                        else
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                                                imiss <= `TRUE;
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                                end
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                        end
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                        else begin
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                                bf <= 1'b0;
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                                wai <= 1'b0;
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                                if (em & !nmoi) begin
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                                        radr <= {spage[31:8],sp[7:2]};
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                                        radr2LSB <= sp[1:0];
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                                        wadr <= {spage[31:8],sp[7:2]};
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                                        wadr2LSB <= sp[1:0];
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                                        wdat <= {4{pc[31:24]}};
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                                        cyc_o <= 1'b1;
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                                        stb_o <= 1'b1;
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                                        we_o <= 1'b1;
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                                        case(sp[1:0])
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                                        2'd0:   sel_o <= 4'b0001;
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                                        2'd1:   sel_o <= 4'b0010;
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                                        2'd2:   sel_o <= 4'b0100;
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                                        2'd3:   sel_o <= 4'b1000;
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                                        endcase
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                                        adr_o <= {spage[31:8],sp[7:2],2'b00};
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                                        dat_o <= {4{pc[31:24]}};
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                                        sp <= sp_dec;
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                                        vect <= `BYTE_IRQ_VECT;
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                                        state <= BYTE_IRQ1;
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                                end
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                                else begin
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                                        radr <= isp_dec;
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                                        wadr <= isp_dec;
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                                        wdat <= pc;
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                                        cyc_o <= 1'b1;
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                                        stb_o <= 1'b1;
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                                        we_o <= 1'b1;
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                                        sel_o <= 4'hF;
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                                        adr_o <= {isp_dec,2'b00};
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                                        dat_o <= pc;
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                                        vect <= {vbr[31:9],irq_vect,2'b00};
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                                        state <= IRQ1;
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                                end
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                        end
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                end
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                else if (!wai) begin
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                        if (unCachedInsn) begin
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                                if (bhit) begin
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                                        ir <= ibuf;
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                                        state <= em ? BYTE_DECODE : DECODE;
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                                end
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                                else
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                                        imiss <= `TRUE;
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                        end
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                        else begin
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                                if (ihit) begin
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                                        ir <= insn;
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                                        state <= em ? BYTE_DECODE : DECODE;
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                                end
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                                else
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                                        imiss <= `TRUE;
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                        end
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                end
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                if (first_ifetch) begin
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                        first_ifetch <= `FALSE;
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                        if (em) begin
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                                case(ir[7:0])
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                                `TAY,`TXY,`DEY,`INY:    begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
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                                `TAX,`TYX,`TSX,`DEX,`INX:       begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
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                                `TSA,`TYA,`TXA,`INA,`DEA:       begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
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                                `TAS,`TXS: begin sp <= res8[7:0]; end
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                                `ADC_IMM:
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                                        begin
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                                                acc[7:0] <= df ? bcaio : res8;
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                                                cf <= df ? bcaico : resc8;
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//                                              vf <= resv8;
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                                                vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
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                                                nf <= df ? bcaio[7] : resn8;
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                                                zf <= df ? bcaio==8'h00 : resz8;
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                                        end
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                                `ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I:
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                                        begin
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                                                acc[7:0] <= df ? bcao : res8;
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                                                cf <= df ? bcaco : resc8;
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                                                vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
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                                                nf <= df ? bcao[7] : resn8;
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                                                zf <= df ? bcao==8'h00 : resz8;
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                                        end
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                                `SBC_IMM:
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                                        begin
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                                                acc[7:0] <= df ? bcsio : res8;
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                                                cf <= ~(df ? bcsico : resc8);
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                                                vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
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                                                nf <= df ? bcsio[7] : resn8;
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                                                zf <= df ? bcsio==8'h00 : resz8;
174
                                        end
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                                `SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I:
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                                        begin
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                                                acc[7:0] <= df ? bcso : res8;
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                                                vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
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                                                cf <= ~(df ? bcsco : resc8);
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                                                nf <= df ? bcso[7] : resn8;
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                                                zf <= df ? bcso==8'h00 : resz8;
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                                        end
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                                `CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I,
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                                `CPX_IMM,`CPX_ZP,`CPX_ABS,
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                                `CPY_IMM,`CPY_ZP,`CPY_ABS:
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                                                begin cf <= ~resc8; nf <= resn8; zf <= resz8; end
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                                `BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX:
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                                                begin nf <= b8[7]; vf <= b8[6]; zf <= resz8; end
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                                `TRB_ZP,`TRB_ABS,`TSB_ZP,`TSB_ABS:
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                                        begin zf <= resz8; end
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                                `LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_I,
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                                `AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I,
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                                `ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_I,
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                                `EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_I:
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                                        begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
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                                `ASL_ACC:       begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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                                `ROL_ACC:       begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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                                `LSR_ACC:       begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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                                `ROR_ACC:       begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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                                `ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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                                `ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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                                `LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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                                `ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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                                `INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn8; zf <= resz8; end
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                                `DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn8; zf <= resz8; end
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                                `PLA:   begin acc[7:0] <= res8; zf <= resz8; nf <= resn8; end
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                                `PLX:   begin x[7:0] <= res8; zf <= resz8; nf <= resn8; end
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                                `PLY:   begin y[7:0] <= res8; zf <= resz8; nf <= resn8; end
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                                `LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY:   begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
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                                `LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX:   begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
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                                endcase
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                        end
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                        else begin
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                                regfile[Rt] <= res;
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                                case(Rt)
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                                4'h1:   acc <= res;
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                                4'h2:   x <= res;
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                                4'h3:   y <= res;
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                                default:        ;
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                                endcase
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                                case(ir[7:0])
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                                `TAY,`TXY,`DEY,`INY:    begin y <= res; nf <= resn32; zf <= resz32; end
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                                `TAX,`TYX,`TSX,`DEX,`INX:       begin x <= res; nf <= resn32; zf <= resz32; end
224 23 robfinch
                                `TAS,`TXS,`SUB_SP:      begin isp <= res; gie <= 1'b1; end
225 20 robfinch
                                `TSA,`TYA,`TXA,`INA,`DEA:       begin acc <= res; nf <= resn32; zf <= resz32; end
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                                `TRS:
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                                        begin
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                                                case(ir[15:12])
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                                                4'h0:   begin
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                                                                $display("res=%h",res);
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                                                                icacheOn <= res[0];
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                                                                dcacheOn <= res[1];
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                                                                write_allocate <= res[2];
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                                                                end
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                                                4'h1:   dp <= res;
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                                                4'h5:   lfsr <= res;
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                                                4'h6:   dp8 <= res;
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                                                4'h7:   abs8 <= res;
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                                                4'h8:   begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end
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                                                4'hE:   begin sp <= res[7:0]; spage[31:8] <= res[31:8]; end
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                                                4'hF:   begin isp <= res; gie <= 1'b1; end
242
                                                endcase
243
                                        end
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                                `RR:
245
                                        case(ir[23:20])
246
                                        `ADD_RR:        begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
247
                                        `SUB_RR:
248
                                                        if (Rt==4'h0)   // CMP doesn't set overflow
249
                                                                begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
250
                                                        else
251
                                                                begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
252
                                        `AND_RR:
253
                                                if (Rt==4'h0)   // BIT sets overflow
254
                                                        begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
255
                                                else
256
                                                        begin nf <= resn32; zf <= resz32; end
257
                                        `OR_RR: begin nf <= resn32; zf <= resz32; end
258
                                        `EOR_RR:        begin nf <= resn32; zf <= resz32; end
259
                                        `MUL_RR:        begin nf <= resn32; zf <= resz32; end
260
                                        `MULS_RR:       begin nf <= resn32; zf <= resz32; end
261
                                        `DIV_RR:        begin nf <= resn32; zf <= resz32; end
262
                                        `DIVS_RR:       begin nf <= resn32; zf <= resz32; end
263
                                        `MOD_RR:        begin nf <= resn32; zf <= resz32; end
264
                                        `MODS_RR:       begin nf <= resn32; zf <= resz32; end
265
                                        `ASL_RRR:       begin nf <= resn32; zf <= resz32; end
266
                                        `LSR_RRR:       begin nf <= resn32; zf <= resz32; end
267
                                        endcase
268
                                `LD_RR: begin zf <= resz32; nf <= resn32; end
269
                                `DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
270
                                `ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR: begin cf <= resc32; nf <= resn32; zf <= resz32; end
271
                                `ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
272
                                        begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
273
                                `SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
274
                                        if (Rt==4'h0)   // CMP doesn't set overflow
275
                                                begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
276
                                        else
277
                                                begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
278
                                `AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
279
                                        if (Rt==4'h0)   // BIT sets overflow
280
                                                begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
281
                                        else
282
                                                begin nf <= resn32; zf <= resz32; end
283
                                `ORB_ZPX,`ORB_ABS,`ORB_ABSX,
284
                                `OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
285
                                `EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
286
                                        begin nf <= resn32; zf <= resz32; end
287
                                `ASL_ACC:       begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
288
                                `ROL_ACC:       begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
289
                                `LSR_ACC:       begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
290
                                `ROR_ACC:       begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
291
                                `ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
292
                                `ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
293
                                `LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
294
                                `ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
295
                                `ASL_IMM8: begin nf <= resn32; zf <= resz32; end
296
                                `LSR_IMM8: begin nf <= resn32; zf <= resz32; end
297
                                `INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
298
                                `DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
299
                                `PLA:   begin acc <= res; zf <= resz32; nf <= resn32; end
300
                                `PLX:   begin x <= res; zf <= resz32; nf <= resn32; end
301
                                `PLY:   begin y <= res; zf <= resz32; nf <= resn32; end
302
                                `LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY:    begin x <= res; nf <= resn32; zf <= resz32; end
303
                                `LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin y <= res; nf <= resn32; zf <= resz32; end
304
                                `CPX_IMM32,`CPX_ZPX,`CPX_ABS:   begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
305
                                `CPY_IMM32,`CPY_ZPX,`CPY_ABS:   begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
306
                                `CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
307
                                `LDA_IMM32,`LDA_IMM16,`LDA_IMM8:        begin acc <= res; nf <= resn32; zf <= resz32; end
308
                                endcase
309
                        end
310
                end
311
        end

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