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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
IFETCH:
        begin
                if (em)
                        vect <= `BYTE_IRQ_VECT;
                else
                        vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
                suppress_pcinc <= 4'hF;                         // default: no suppression of increment
                opc <= pc;
                hwi <= `FALSE;
                store_what <= `STW_DEF;
                if (nmi_edge & !imiss & gie & !isExec & !isAtni) begin  // imiss indicates cache controller is active and this state is in a waiting loop
                        ir <= 64'd0;
                        nmi_edge <= 1'b0;
                        wai <= 1'b0;
                        hwi <= `TRUE;
                        if (em & !nmoi) begin
                                vect <= `BYTE_NMI_VECT;
                                state <= BYTE_DECODE;
                        end
                        else begin
                                state <= DECODE;
                                vect <= `NMI_VECT;
                        end
                end
                else if (irq_i && !imiss & gie & !isExec & !isAtni) begin
                        wai <= 1'b0;
                        if (im) begin
                                if (isExec) begin
                                        ir <= exbuf;
                                        exbuf <= 64'd0;
                                        suppress_pcinc <= 4'h0;
                                        state <= em ? BYTE_DECODE : DECODE;
                                end
                                else if (unCachedInsn) begin
                                        if (bhit) begin
                                                ir <= ibuf + exbuf;
                                                exbuf <= 64'd0;
                                                state <= em ? BYTE_DECODE : DECODE;
                                        end
                                        else
                                                imiss <= `TRUE;
                                end
                                else begin
                                        if (ihit) begin
                                                ir <= insn + exbuf;
                                                exbuf <= 64'd0;
                                                state <= em ? BYTE_DECODE : DECODE;
                                        end
                                        else
                                                imiss <= `TRUE;
                                end
                        end
                        else begin
                                ir <= 64'd0;
                                hwi <= `TRUE;
                                if (em & !nmoi) begin
                                        state <= BYTE_DECODE;
                                end
                                else begin
                                        vect <= {vbr[31:9],irq_vect,2'b00};
                                        state <= DECODE;
                                end
                        end
                end
                else if (!wai) begin
                        if (isExec) begin
                                ir <= exbuf;
                                exbuf <= 64'd0;
                                suppress_pcinc <= 4'h0;
                                state <= em ? BYTE_DECODE : DECODE;
                        end
                        else if (unCachedInsn) begin
                                if (bhit) begin
                                        ir <= ibuf + exbuf;
                                        exbuf <= 64'd0;
                                        state <= em ? BYTE_DECODE : DECODE;
                                end
                                else
                                        imiss <= `TRUE;
                        end
                        else begin
                                if (ihit) begin
                                        ir <= insn + exbuf;
                                        exbuf <= 64'd0;
                                        state <= em ? BYTE_DECODE : DECODE;
                                end
                                else
                                        imiss <= `TRUE;
                        end
                end
                if (first_ifetch) begin
                        first_ifetch <= `FALSE;
                        if (hist_capture) begin
                                history_buf[history_ndx] <= pc;
                                history_ndx <= history_ndx+6'd1;
                        end
`ifdef SUPPORT_EM8
                        if (em) begin
                                case(ir[7:0])
                                `TAY,`TXY,`DEY,`INY:    begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
                                `TAX,`TYX,`TSX,`DEX,`INX:       begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
                                `TSA,`TYA,`TXA,`INA,`DEA:       begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
                                `TAS,`TXS: begin sp <= res8[7:0]; end
                                `ADC_IMM:
                                        begin
                                                acc[7:0] <= df ? bcaio : res8;
                                                cf <= df ? bcaico : resc8;
//                                              vf <= resv8;
                                                vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
                                                nf <= df ? bcaio[7] : resn8;
                                                zf <= df ? bcaio==8'h00 : resz8;
                                        end
                                `ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I:
                                        begin
                                                acc[7:0] <= df ? bcao : res8;
                                                cf <= df ? bcaco : resc8;
                                                vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
                                                nf <= df ? bcao[7] : resn8;
                                                zf <= df ? bcao==8'h00 : resz8;
                                        end
                                `SBC_IMM:
                                        begin
                                                acc[7:0] <= df ? bcsio : res8;
                                                cf <= ~(df ? bcsico : resc8);
                                                vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
                                                nf <= df ? bcsio[7] : resn8;
                                                zf <= df ? bcsio==8'h00 : resz8;
                                        end
                                `SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I:
                                        begin
                                                acc[7:0] <= df ? bcso : res8;
                                                vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
                                                cf <= ~(df ? bcsco : resc8);
                                                nf <= df ? bcso[7] : resn8;
                                                zf <= df ? bcso==8'h00 : resz8;
                                        end
                                `CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I,
                                `CPX_IMM,`CPX_ZP,`CPX_ABS,
                                `CPY_IMM,`CPY_ZP,`CPY_ABS:
                                                begin cf <= ~resc8; nf <= resn8; zf <= resz8; end
                                `BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX:
                                                begin nf <= b8[7]; vf <= b8[6]; zf <= resz8; end
                                `TRB_ZP,`TRB_ABS,`TSB_ZP,`TSB_ABS:
                                        begin zf <= resz8; end
                                `LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_I,
                                `AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I,
                                `ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_I,
                                `EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_I:
                                        begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
                                `ASL_ACC:       begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
                                `ROL_ACC:       begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
                                `LSR_ACC:       begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
                                `ROR_ACC:       begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
                                `ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
                                `ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
                                `LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
                                `ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
                                `INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn8; zf <= resz8; end
                                `DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn8; zf <= resz8; end
                                `PLA:   begin acc[7:0] <= res8; zf <= resz8; nf <= resn8; end
                                `PLX:   begin x[7:0] <= res8; zf <= resz8; nf <= resn8; end
                                `PLY:   begin y[7:0] <= res8; zf <= resz8; nf <= resn8; end
                                `LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY:   begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
                                `LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX:   begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
                                endcase
                        end
                        else
`endif
                        begin
                                regfile[Rt] <= res;
                                case(Rt)
                                4'h1:   acc <= res;
                                4'h2:   x <= res;
                                4'h3:   y <= res;
                                default:        ;
                                endcase
                                case(ir[7:0])
                                `TAS,`TXS:      begin isp <= res; gie <= 1'b1; end
                                `SUB_SP8,`SUB_SP16,`SUB_SP32:   isp <= res;
                                `TRS:
                                        begin
                                                case(ir[15:12])
                                                4'h0:   begin
                                                                $display("res=%h",res);
`ifdef SUPPORT_ICACHE
                                                                icacheOn <= res[0];
`endif
`ifdef SUPPORT_DCACHE
                                                                dcacheOn <= res[1];
                                                                write_allocate <= res[2];
`endif
                                                                end
                                                4'h5:   lfsr <= res;
                                                4'h7:   abs8 <= res;
                                                4'h8:   begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end
                                                4'hE:   begin sp <= res[7:0]; spage[31:8] <= res[31:8]; end
                                                4'hF:   begin isp <= res; gie <= 1'b1; end
                                                endcase
                                        end
                                `RR:
                                        case(ir[23:20])
                                        `ADD_RR:        begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
                                        `SUB_RR:
                                                        if (Rt==4'h0)   // CMP doesn't set overflow
                                                                begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                                                        else
                                                                begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
                                        `AND_RR:
                                                if (Rt==4'h0)   // BIT sets overflow
                                                        begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
                                                else
                                                        begin nf <= resn32; zf <= resz32; end
                                        default:
                                                        begin nf <= resn32; zf <= resz32; end
                                        endcase
                                `LD_RR: begin zf <= resz32; nf <= resn32; end
                                `DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
                                `ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
                                        begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
                                `SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
                                        if (Rt==4'h0)   // CMP doesn't set overflow
                                                begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                                        else
                                                begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
                                `AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
                                        if (Rt==4'h0)   // BIT sets overflow
                                                begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
                                        else
                                                begin nf <= resn32; zf <= resz32; end
                                `ORB_ZPX,`ORB_ABS,`ORB_ABSX,
                                `OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
                                `EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
                                        begin nf <= resn32; zf <= resz32; end
                                `ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
                                        begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
                                `ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
                                `ASL_ZPX,`ASL_ABS,`ASL_ABSX,
                                `ROL_ZPX,`ROL_ABS,`ROL_ABSX,
                                `LSR_ZPX,`LSR_ABS,`LSR_ABSX,
                                `ROR_ZPX,`ROR_ABS,`ROR_ABSX:
                                        begin cf <= resc32; nf <= resn32; zf <= resz32; end
                                `ASL_IMM8: begin nf <= resn32; zf <= resz32; end
                                `LSR_IMM8: begin nf <= resn32; zf <= resz32; end
                                `INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
                                `DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
                                `TAX,`TYX,`TSX,`DEX,`INX,
                                `LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`PLX:
                                        begin x <= res; nf <= resn32; zf <= resz32; end
                                `TAY,`TXY,`DEY,`INY,
                                `LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`PLY:
                                        begin y <= res; nf <= resn32; zf <= resz32; end
                                `CPX_IMM32,`CPX_ZPX,`CPX_ABS:   begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                                `CPY_IMM32,`CPY_ZPX,`CPY_ABS:   begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                                `CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                                `TSA,`TYA,`TXA,`INA,`DEA,
                                `LDA_IMM32,`LDA_IMM16,`LDA_IMM8,`PLA:   begin acc <= res; nf <= resn32; zf <= resz32; end
                                `POP:   begin nf <= resn32; zf <= resz32; end
                                endcase
                        end
                end
        end

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`IFETCH:`
24			`begin`
25	30	robfinch	`if (em)`
26			vect <= `BYTE_IRQ_VECT;
27			`else`
28			vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
29	25	robfinch	`suppress_pcinc <= 4'hF; // default: no suppression of increment`
30	23	robfinch	`opc <= pc;`
31	25	robfinch	hwi <= `FALSE;
32	30	robfinch	store_what <= `STW_DEF;
33	25	robfinch	`if (nmi_edge & !imiss & gie & !isExec & !isAtni) begin // imiss indicates cache controller is active and this state is in a waiting loop`
34	30	robfinch	`ir <= 64'd0;`
35	20	robfinch	`nmi_edge <= 1'b0;`
36			`wai <= 1'b0;`
37	25	robfinch	hwi <= `TRUE;
38	20	robfinch	`if (em & !nmoi) begin`
39			vect <= `BYTE_NMI_VECT;
40	30	robfinch	`state <= BYTE_DECODE;`
41	20	robfinch	`end`
42			`else begin`
43	30	robfinch	`state <= DECODE;`
44	20	robfinch	vect <= `NMI_VECT;
45			`end`
46			`end`
47	25	robfinch	`else if (irq_i && !imiss & gie & !isExec & !isAtni) begin`
48	30	robfinch	`wai <= 1'b0;`
49	20	robfinch	`if (im) begin`
50	25	robfinch	`if (isExec) begin`
51			`ir <= exbuf;`
52			`exbuf <= 64'd0;`
53			`suppress_pcinc <= 4'h0;`
54			`state <= em ? BYTE_DECODE : DECODE;`
55			`end`
56			`else if (unCachedInsn) begin`
57	20	robfinch	`if (bhit) begin`
58	25	robfinch	`ir <= ibuf + exbuf;`
59			`exbuf <= 64'd0;`
60	20	robfinch	`state <= em ? BYTE_DECODE : DECODE;`
61			`end`
62			`else`
63			imiss <= `TRUE;
64			`end`
65			`else begin`
66			`if (ihit) begin`
67	25	robfinch	`ir <= insn + exbuf;`
68			`exbuf <= 64'd0;`
69	20	robfinch	`state <= em ? BYTE_DECODE : DECODE;`
70			`end`
71			`else`
72			imiss <= `TRUE;
73			`end`
74			`end`
75			`else begin`
76	30	robfinch	`ir <= 64'd0;`
77	25	robfinch	hwi <= `TRUE;
78	20	robfinch	`if (em & !nmoi) begin`
79	30	robfinch	`state <= BYTE_DECODE;`
80	20	robfinch	`end`
81			`else begin`
82			`vect <= {vbr[31:9],irq_vect,2'b00};`
83	30	robfinch	`state <= DECODE;`
84	20	robfinch	`end`
85			`end`
86			`end`
87			`else if (!wai) begin`
88	25	robfinch	`if (isExec) begin`
89			`ir <= exbuf;`
90			`exbuf <= 64'd0;`
91			`suppress_pcinc <= 4'h0;`
92			`state <= em ? BYTE_DECODE : DECODE;`
93			`end`
94			`else if (unCachedInsn) begin`
95	20	robfinch	`if (bhit) begin`
96	25	robfinch	`ir <= ibuf + exbuf;`
97			`exbuf <= 64'd0;`
98	20	robfinch	`state <= em ? BYTE_DECODE : DECODE;`
99			`end`
100			`else`
101			imiss <= `TRUE;
102			`end`
103			`else begin`
104			`if (ihit) begin`
105	25	robfinch	`ir <= insn + exbuf;`
106			`exbuf <= 64'd0;`
107	20	robfinch	`state <= em ? BYTE_DECODE : DECODE;`
108			`end`
109			`else`
110			imiss <= `TRUE;
111			`end`
112			`end`
113			`if (first_ifetch) begin`
114			first_ifetch <= `FALSE;
115	30	robfinch	`if (hist_capture) begin`
116			`history_buf[history_ndx] <= pc;`
117			`history_ndx <= history_ndx+6'd1;`
118			`end`
119			`ifdef SUPPORT_EM8
120	20	robfinch	`if (em) begin`
121			`case(ir[7:0])`
122			`TAY,`TXY,`DEY,`INY: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
123			`TAX,`TYX,`TSX,`DEX,`INX: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
124			`TSA,`TYA,`TXA,`INA,`DEA: begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
125			`TAS,`TXS: begin sp <= res8[7:0]; end
126			`ADC_IMM:
127			`begin`
128			`acc[7:0] <= df ? bcaio : res8;`
129			`cf <= df ? bcaico : resc8;`
130			`// vf <= resv8;`
131			`vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);`
132			`nf <= df ? bcaio[7] : resn8;`
133			`zf <= df ? bcaio==8'h00 : resz8;`
134			`end`
135			`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I:
136			`begin`
137			`acc[7:0] <= df ? bcao : res8;`
138			`cf <= df ? bcaco : resc8;`
139			`vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);`
140			`nf <= df ? bcao[7] : resn8;`
141			`zf <= df ? bcao==8'h00 : resz8;`
142			`end`
143			`SBC_IMM:
144			`begin`
145			`acc[7:0] <= df ? bcsio : res8;`
146			`cf <= ~(df ? bcsico : resc8);`
147			`vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);`
148			`nf <= df ? bcsio[7] : resn8;`
149			`zf <= df ? bcsio==8'h00 : resz8;`
150			`end`
151			`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I:
152			`begin`
153			`acc[7:0] <= df ? bcso : res8;`
154			`vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);`
155			`cf <= ~(df ? bcsco : resc8);`
156			`nf <= df ? bcso[7] : resn8;`
157			`zf <= df ? bcso==8'h00 : resz8;`
158			`end`
159			`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I,
160			`CPX_IMM,`CPX_ZP,`CPX_ABS,
161			`CPY_IMM,`CPY_ZP,`CPY_ABS:
162			`begin cf <= ~resc8; nf <= resn8; zf <= resz8; end`
163			`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX:
164			`begin nf <= b8[7]; vf <= b8[6]; zf <= resz8; end`
165			`TRB_ZP,`TRB_ABS,`TSB_ZP,`TSB_ABS:
166			`begin zf <= resz8; end`
167			`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_I,
168			`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I,
169			`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_I,
170			`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_I:
171			`begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end`
172			`ASL_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
173			`ROL_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
174			`LSR_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
175			`ROR_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
176			`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
177			`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
178			`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
179			`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
180			`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn8; zf <= resz8; end
181			`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn8; zf <= resz8; end
182			`PLA: begin acc[7:0] <= res8; zf <= resz8; nf <= resn8; end
183			`PLX: begin x[7:0] <= res8; zf <= resz8; nf <= resn8; end
184			`PLY: begin y[7:0] <= res8; zf <= resz8; nf <= resn8; end
185			`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
186			`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
187			`endcase`
188			`end`
189	30	robfinch	`else`
190			`endif
191			`begin`
192	20	robfinch	`regfile[Rt] <= res;`
193			`case(Rt)`
194			`4'h1: acc <= res;`
195			`4'h2: x <= res;`
196			`4'h3: y <= res;`
197			`default: ;`
198			`endcase`
199			`case(ir[7:0])`
200	25	robfinch	`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
201			`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res;
202	20	robfinch	`TRS:
203			`begin`
204			`case(ir[15:12])`
205			`4'h0: begin`
206			`$display("res=%h",res);`
207	30	robfinch	`ifdef SUPPORT_ICACHE
208	20	robfinch	`icacheOn <= res[0];`
209	30	robfinch	`endif
210			`ifdef SUPPORT_DCACHE
211	20	robfinch	`dcacheOn <= res[1];`
212			`write_allocate <= res[2];`
213	30	robfinch	`endif
214	20	robfinch	`end`
215			`4'h5: lfsr <= res;`
216			`4'h7: abs8 <= res;`
217			`4'h8: begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end`
218			`4'hE: begin sp <= res[7:0]; spage[31:8] <= res[31:8]; end`
219			`4'hF: begin isp <= res; gie <= 1'b1; end`
220			`endcase`
221			`end`
222			`RR:
223			`case(ir[23:20])`
224			`ADD_RR: begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
225			`SUB_RR:
226			`if (Rt==4'h0) // CMP doesn't set overflow`
227			`begin cf <= ~resc32; nf <= resn32; zf <= resz32; end`
228			`else`
229			`begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end`
230			`AND_RR:
231			`if (Rt==4'h0) // BIT sets overflow`
232			`begin nf <= b[31]; vf <= b[30]; zf <= resz32; end`
233			`else`
234			`begin nf <= resn32; zf <= resz32; end`
235	30	robfinch	`default:`
236			`begin nf <= resn32; zf <= resz32; end`
237	20	robfinch	`endcase`
238			`LD_RR: begin zf <= resz32; nf <= resn32; end
239			`DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
240			`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
241			`begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end`
242			`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
243			`if (Rt==4'h0) // CMP doesn't set overflow`
244			`begin cf <= ~resc32; nf <= resn32; zf <= resz32; end`
245			`else`
246			`begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end`
247			`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
248			`if (Rt==4'h0) // BIT sets overflow`
249			`begin nf <= b[31]; vf <= b[30]; zf <= resz32; end`
250			`else`
251			`begin nf <= resn32; zf <= resz32; end`
252			`ORB_ZPX,`ORB_ABS,`ORB_ABSX,
253			`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
254			`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
255			`begin nf <= resn32; zf <= resz32; end`
256	30	robfinch	`ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
257			`begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end`
258			`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
259			`ASL_ZPX,`ASL_ABS,`ASL_ABSX,
260			`ROL_ZPX,`ROL_ABS,`ROL_ABSX,
261			`LSR_ZPX,`LSR_ABS,`LSR_ABSX,
262			`ROR_ZPX,`ROR_ABS,`ROR_ABSX:
263			`begin cf <= resc32; nf <= resn32; zf <= resz32; end`
264	20	robfinch	`ASL_IMM8: begin nf <= resn32; zf <= resz32; end
265			`LSR_IMM8: begin nf <= resn32; zf <= resz32; end
266			`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
267			`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
268	30	robfinch	`TAX,`TYX,`TSX,`DEX,`INX,
269			`LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`PLX:
270			`begin x <= res; nf <= resn32; zf <= resz32; end`
271			`TAY,`TXY,`DEY,`INY,
272			`LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`PLY:
273			`begin y <= res; nf <= resn32; zf <= resz32; end`
274	20	robfinch	`CPX_IMM32,`CPX_ZPX,`CPX_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
275			`CPY_IMM32,`CPY_ZPX,`CPY_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
276			`CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
277	30	robfinch	`TSA,`TYA,`TXA,`INA,`DEA,
278			`LDA_IMM32,`LDA_IMM16,`LDA_IMM8,`PLA: begin acc <= res; nf <= resn32; zf <= resz32; end
279			`POP: begin nf <= resn32; zf <= resz32; end
280	20	robfinch	`endcase`
281			`end`
282			`end`
283			`end`

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