URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_mac.v] - Blame information for rev 23

Go to most recent revision | Details | Compare with Previous | View Log


// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
LOAD_MAC1:
        if (unCachedData) begin
                if (isRMW)
                        lock_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= LOAD_MAC2;
        end
        else if (dhit) begin
                case(load_what)
                `WORD_310:
                                begin
                                        b <= rdat;
                                        b8 <= rdat8;            // for the orb instruction
                                        state <= CALC;
                                end
                `WORD_311:      // For pla/plx/ply/pop
                                        begin
                                                res <= rdat;
                                                state <= IFETCH;
                                        end
                `WORD_312:
                                begin
                                        b <= rdat;
                                        state <= retstate;
                                end
                `BYTE_70:
                                begin
                                        b8 <= rdat8;
                                        state <= BYTE_CALC;
                                end
                `BYTE_71:
                                begin
                                        res8 <= rdat8;
                                        state <= IFETCH;
                                end
                `SR_310:
                                begin
                                        cf <= rdat[0];
                                        zf <= rdat[1];
                                        im <= rdat[2];
                                        df <= rdat[3];
                                        bf <= rdat[4];
                                        em <= rdat[29];
                                        vf <= rdat[30];
                                        nf <= rdat[31];
                                        isp <= isp_inc;
                                        radr <= isp_inc;
                                        if (isRTI)
                                                load_what <= `PC_310;
                                        else    // PLP
                                                state <= IFETCH;
                                end
                `SR_70:
                                begin
                                        cf <= rdat8[0];
                                        zf <= rdat8[1];
                                        im <= rdat8[2];
                                        df <= rdat8[3];
                                        bf <= rdat8[4];
                                        vf <= rdat8[6];
                                        nf <= rdat8[7];
                                        if (isRTI) begin
                                                load_what <= `PC_70;
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        else    // PLP
                                                state <= IFETCH;
                                end
                `PC_70:
                                begin
                                        pc[7:0] <= rdat8;
                                        if (isRTI | isRTS | isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        else begin      // JMP (abs)
                                                radr <= radr34p1[33:2];
                                                radr2LSB <= radr34p1[1:0];
                                        end
                                        load_what <= `PC_158;
                                end
                `PC_158:
                                begin
                                        pc[15:8] <= rdat8;
                                        if (isRTI|isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                                load_what <= `PC_2316;
                                        end
                                        else if (isRTS) // rts instruction
                                                state <= RTS1;
                                        else                    // jmp (abs)
                                                state <= IFETCH;
                                end
                `PC_2316:
                                begin
                                        pc[23:16] <= rdat8;
                                        if (isRTI|isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        load_what <= `PC_3124;
                                end
                `PC_3124:
                                begin
                                        pc[31:24] <= rdat8;
                                        load_what <= `NOTHING;
                                        if (isRTL)
                                                state <= RTS1;
                                        else
                                                state <= IFETCH;
                                end
                `PC_310:
                                begin
                                        pc <= rdat;
                                        if (isRTI|isRTS|isRTL)
                                                isp <= isp_inc;
                                        load_what <= `NOTHING;
                                        state <= IFETCH;
                                end
                `IA_310:
                                begin
                                        radr <= rdat;
                                        wadr <= rdat;
                                        wdat <= a;
                                        if (isIY)
                                                state <= IY3;
                                        else if (ir[7:0]==`ST_IX)
                                                state <= STORE1;
                                        else begin
                                                load_what <= `WORD_310;
                                        end
                                end
                `IA_70:
                                begin
                                        radr <= radr34p1[33:2];
                                        radr2LSB <= radr34p1[1:0];
                                        ia[7:0] <= rdat8;
                                        load_what <= `IA_158;
                                end
                `IA_158:
                                begin
                                        ia[15:8] <= rdat8;
                                        ia[31:16] <= 16'h0000;
                                        state <= isIY ? BYTE_IY5 : BYTE_IX5;
                                end
                endcase
        end
        else
                dmiss <= `TRUE;
LOAD_MAC2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                case(load_what)
                `WORD_310:
                                        begin
                                                b <= dat_i;
                                                b8 <= dati;             // for the orb instruction
                                                state <= CALC;
                                        end
                `WORD_311:      // For pla/plx/ply/pop/ldx/ldy
                                        begin
                                                res <= dat_i;
                                                state <= IFETCH;
                                        end
                `WORD_312:
                                begin
                                        b <= dat_i;
                                        state <= retstate;
                                end
                `BYTE_70:
                                        begin
                                                b8 <= dati;
                                                state <= BYTE_CALC;
                                        end
                `BYTE_71:
                                begin
                                        res8 <= dati;
                                        state <= IFETCH;
                                end
                `SR_310:        begin
                                                cf <= dat_i[0];
                                                zf <= dat_i[1];
                                                im <= dat_i[2];
                                                df <= dat_i[3];
                                                bf <= dat_i[4];
                                                em <= dat_i[29];
                                                vf <= dat_i[30];
                                                nf <= dat_i[31];
                                                isp <= isp_inc;
                                                radr <= isp_inc;
                                                if (isRTI) begin
                                                        load_what <= `PC_310;
                                                        state <= LOAD_MAC1;
                                                end
                                                else    // PLP
                                                        state <= IFETCH;
                                        end
                `SR_70:         begin
                                                cf <= dati[0];
                                                zf <= dati[1];
                                                im <= dati[2];
                                                df <= dati[3];
                                                bf <= dati[4];
                                                vf <= dati[6];
                                                nf <= dati[7];
                                                if (isRTI) begin
                                                        load_what <= `PC_70;
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                        state <= LOAD_MAC1;
                                                end
                                                else    // PLP
                                                        state <= IFETCH;
                                        end
                `PC_70:         begin
                                                pc[7:0] <= dati;
                                                load_what <= `PC_158;
                                                if (isRTI|isRTS|isRTL) begin
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                end
                                                else begin      // JMP (abs)
                                                        radr <= radr34p1[33:2];
                                                        radr2LSB <= radr34p1[1:0];
                                                end
                                                state <= LOAD_MAC1;
                                        end
                `PC_158:        begin
                                                pc[15:8] <= dati;
                                                if (isRTI|isRTL) begin
                                                        load_what <= `PC_2316;
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                        state <= LOAD_MAC1;
                                                end
                                                else if (isRTS) // rts instruction
                                                        state <= RTS1;
                                                else                    // jmp (abs)
                                                        state <= IFETCH;
                                        end
                `PC_2316:       begin
                                                pc[23:16] <= dati;
                                                load_what <= `PC_3124;
                                                if (isRTI|isRTL) begin
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                end
                                                state <= LOAD_MAC1;
                                        end
                `PC_3124:       begin
                                                pc[31:24] <= dati;
                                                load_what <= `NOTHING;
                                                if (isRTL)
                                                        state <= RTS1;
                                                else
                                                        state <= IFETCH;
                                        end
                `PC_310:        begin
                                                pc <= dat_i;
                                                load_what <= `NOTHING;
                                                if (isRTI | isRTL | isRTS)
                                                        isp <= isp_inc;
                                                state <= IFETCH;
                                        end
                `IA_310:
                                begin
                                        radr <= dat_i;
                                        wadr <= dat_i;
                                        wdat <= a;
                                        if (isIY)
                                                state <= IY3;
                                        else if (ir[7:0]==`ST_IX)
                                                state <= STORE1;
                                        else begin
                                                load_what <= `WORD_310;
                                                state <= LOAD_MAC1;
                                        end
                                end
                `IA_70:
                                begin
                                        radr <= radr34p1[33:2];
                                        radr2LSB <= radr34p1[1:0];
                                        ia[7:0] <= dati;
                                        load_what <= `IA_158;
                                        state <= LOAD_MAC1;
                                end
                `IA_158:
                                begin
                                        ia[15:8] <= dati;
                                        ia[31:16] <= 16'h0000;
                                        state <= isIY ? BYTE_IY5 : BYTE_IX5;
                                end
                endcase
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
RTS1:
        begin
                pc <= pc + 32'd1;
                state <= IFETCH;
        end
IY3:
        begin
                radr <= radr + y;
                wadr <= radr + y;
                wdat <= a;
                if (ir[7:0]==`ST_IY)
                        state <= STORE1;
                else begin
                        load_what <= `WORD_310;
                        state <= LOAD_MAC1;
                end
                isIY <= 1'b0;
        end
BYTE_IX5:
        begin
                radr <= ia[31:2];
                radr2LSB <= ia[1:0];
                load_what <= `BYTE_70;
                state <= LOAD_MAC1;
                if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I) begin
                        wadr <= ia[31:2];
                        wadr2LSB <= ia[1:0];
                        wdat <= {4{acc8}};
                        state <= STORE1;
                end
        end
BYTE_IY5:
        begin
                isIY <= `FALSE;
                radr <= iapy8[31:2];
                radr2LSB <= iapy8[1:0];
                $display("IY addr: %h", iapy8);
                if (ir[7:0]==`STA_IY) begin
                        wadr <= iapy8[31:2];
                        wadr2LSB <= iapy8[1:0];
                        wdat <= {4{acc8}};
                        state <= STORE1;
                end
                else begin
                        load_what <= `BYTE_70;
                        state <= LOAD_MAC1;
                end
        end

Line No.	Rev	Author	Line
1	21	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`LOAD_MAC1:`
24			`if (unCachedData) begin`
25			`if (isRMW)`
26			`lock_o <= 1'b1;`
27			`cyc_o <= 1'b1;`
28			`stb_o <= 1'b1;`
29			`sel_o <= 4'hF;`
30			`adr_o <= {radr,2'b00};`
31			`state <= LOAD_MAC2;`
32			`end`
33			`else if (dhit) begin`
34			`case(load_what)`
35			`WORD_310:
36			`begin`
37			`b <= rdat;`
38			`b8 <= rdat8; // for the orb instruction`
39			`state <= CALC;`
40			`end`
41			`WORD_311: // For pla/plx/ply/pop
42			`begin`
43			`res <= rdat;`
44			`state <= IFETCH;`
45			`end`
46	23	robfinch	`WORD_312:
47			`begin`
48			`b <= rdat;`
49			`state <= retstate;`
50			`end`
51	21	robfinch	`BYTE_70:
52			`begin`
53			`b8 <= rdat8;`
54			`state <= BYTE_CALC;`
55			`end`
56			`BYTE_71:
57			`begin`
58			`res8 <= rdat8;`
59			`state <= IFETCH;`
60			`end`
61			`SR_310:
62			`begin`
63			`cf <= rdat[0];`
64			`zf <= rdat[1];`
65			`im <= rdat[2];`
66			`df <= rdat[3];`
67			`bf <= rdat[4];`
68			`em <= rdat[29];`
69			`vf <= rdat[30];`
70			`nf <= rdat[31];`
71			`isp <= isp_inc;`
72			`radr <= isp_inc;`
73			`if (isRTI)`
74			load_what <= `PC_310;
75			`else // PLP`
76			`state <= IFETCH;`
77			`end`
78			`SR_70:
79			`begin`
80			`cf <= rdat8[0];`
81			`zf <= rdat8[1];`
82			`im <= rdat8[2];`
83			`df <= rdat8[3];`
84			`bf <= rdat8[4];`
85			`vf <= rdat8[6];`
86			`nf <= rdat8[7];`
87			`if (isRTI) begin`
88			load_what <= `PC_70;
89			`radr <= {spage[31:8],sp_inc[7:2]};`
90			`radr2LSB <= sp_inc[1:0];`
91			`sp <= sp_inc;`
92			`end`
93			`else // PLP`
94			`state <= IFETCH;`
95			`end`
96			`PC_70:
97			`begin`
98			`pc[7:0] <= rdat8;`
99			`if (isRTI \| isRTS \| isRTL) begin`
100			`radr <= {spage[31:8],sp_inc[7:2]};`
101			`radr2LSB <= sp_inc[1:0];`
102			`sp <= sp_inc;`
103			`end`
104			`else begin // JMP (abs)`
105			`radr <= radr34p1[33:2];`
106			`radr2LSB <= radr34p1[1:0];`
107			`end`
108			load_what <= `PC_158;
109			`end`
110			`PC_158:
111			`begin`
112			`pc[15:8] <= rdat8;`
113			`if (isRTI\|isRTL) begin`
114			`radr <= {spage[31:8],sp_inc[7:2]};`
115			`radr2LSB <= sp_inc[1:0];`
116			`sp <= sp_inc;`
117			load_what <= `PC_2316;
118			`end`
119			`else if (isRTS) // rts instruction`
120			`state <= RTS1;`
121			`else // jmp (abs)`
122			`state <= IFETCH;`
123			`end`
124			`PC_2316:
125			`begin`
126			`pc[23:16] <= rdat8;`
127			`if (isRTI\|isRTL) begin`
128			`radr <= {spage[31:8],sp_inc[7:2]};`
129			`radr2LSB <= sp_inc[1:0];`
130			`sp <= sp_inc;`
131			`end`
132			load_what <= `PC_3124;
133			`end`
134			`PC_3124:
135			`begin`
136			`pc[31:24] <= rdat8;`
137			load_what <= `NOTHING;
138			`if (isRTL)`
139			`state <= RTS1;`
140			`else`
141			`state <= IFETCH;`
142			`end`
143			`PC_310:
144			`begin`
145			`pc <= rdat;`
146			`if (isRTI\|isRTS\|isRTL)`
147			`isp <= isp_inc;`
148			load_what <= `NOTHING;
149			`state <= IFETCH;`
150			`end`
151			`IA_310:
152			`begin`
153			`radr <= rdat;`
154			`wadr <= rdat;`
155			`wdat <= a;`
156			`if (isIY)`
157			`state <= IY3;`
158			else if (ir[7:0]==`ST_IX)
159			`state <= STORE1;`
160			`else begin`
161			load_what <= `WORD_310;
162			`end`
163			`end`
164			`IA_70:
165			`begin`
166			`radr <= radr34p1[33:2];`
167			`radr2LSB <= radr34p1[1:0];`
168			`ia[7:0] <= rdat8;`
169			load_what <= `IA_158;
170			`end`
171			`IA_158:
172			`begin`
173			`ia[15:8] <= rdat8;`
174			`ia[31:16] <= 16'h0000;`
175			`state <= isIY ? BYTE_IY5 : BYTE_IX5;`
176			`end`
177			`endcase`
178			`end`
179			`else`
180			dmiss <= `TRUE;
181			`LOAD_MAC2:`
182			`if (ack_i) begin`
183			`cyc_o <= 1'b0;`
184			`stb_o <= 1'b0;`
185			`sel_o <= 4'h0;`
186			`adr_o <= 34'h0;`
187			`case(load_what)`
188			`WORD_310:
189			`begin`
190			`b <= dat_i;`
191			`b8 <= dati; // for the orb instruction`
192			`state <= CALC;`
193			`end`
194			`WORD_311: // For pla/plx/ply/pop/ldx/ldy
195			`begin`
196			`res <= dat_i;`
197			`state <= IFETCH;`
198			`end`
199	23	robfinch	`WORD_312:
200			`begin`
201			`b <= dat_i;`
202			`state <= retstate;`
203			`end`
204	21	robfinch	`BYTE_70:
205			`begin`
206			`b8 <= dati;`
207			`state <= BYTE_CALC;`
208			`end`
209			`BYTE_71:
210			`begin`
211			`res8 <= dati;`
212			`state <= IFETCH;`
213			`end`
214			`SR_310: begin
215			`cf <= dat_i[0];`
216			`zf <= dat_i[1];`
217			`im <= dat_i[2];`
218			`df <= dat_i[3];`
219			`bf <= dat_i[4];`
220			`em <= dat_i[29];`
221			`vf <= dat_i[30];`
222			`nf <= dat_i[31];`
223			`isp <= isp_inc;`
224			`radr <= isp_inc;`
225			`if (isRTI) begin`
226			load_what <= `PC_310;
227			`state <= LOAD_MAC1;`
228			`end`
229			`else // PLP`
230			`state <= IFETCH;`
231			`end`
232			`SR_70: begin
233			`cf <= dati[0];`
234			`zf <= dati[1];`
235			`im <= dati[2];`
236			`df <= dati[3];`
237			`bf <= dati[4];`
238			`vf <= dati[6];`
239			`nf <= dati[7];`
240			`if (isRTI) begin`
241			load_what <= `PC_70;
242			`radr <= {spage[31:8],sp_inc[7:2]};`
243			`radr2LSB <= sp_inc[1:0];`
244			`sp <= sp_inc;`
245			`state <= LOAD_MAC1;`
246			`end`
247			`else // PLP`
248			`state <= IFETCH;`
249			`end`
250			`PC_70: begin
251			`pc[7:0] <= dati;`
252			load_what <= `PC_158;
253			`if (isRTI\|isRTS\|isRTL) begin`
254			`radr <= {spage[31:8],sp_inc[7:2]};`
255			`radr2LSB <= sp_inc[1:0];`
256			`sp <= sp_inc;`
257			`end`
258			`else begin // JMP (abs)`
259			`radr <= radr34p1[33:2];`
260			`radr2LSB <= radr34p1[1:0];`
261			`end`
262			`state <= LOAD_MAC1;`
263			`end`
264			`PC_158: begin
265			`pc[15:8] <= dati;`
266			`if (isRTI\|isRTL) begin`
267			load_what <= `PC_2316;
268			`radr <= {spage[31:8],sp_inc[7:2]};`
269			`radr2LSB <= sp_inc[1:0];`
270			`sp <= sp_inc;`
271			`state <= LOAD_MAC1;`
272			`end`
273			`else if (isRTS) // rts instruction`
274			`state <= RTS1;`
275			`else // jmp (abs)`
276			`state <= IFETCH;`
277			`end`
278			`PC_2316: begin
279			`pc[23:16] <= dati;`
280			load_what <= `PC_3124;
281			`if (isRTI\|isRTL) begin`
282			`radr <= {spage[31:8],sp_inc[7:2]};`
283			`radr2LSB <= sp_inc[1:0];`
284			`sp <= sp_inc;`
285			`end`
286			`state <= LOAD_MAC1;`
287			`end`
288			`PC_3124: begin
289			`pc[31:24] <= dati;`
290			load_what <= `NOTHING;
291			`if (isRTL)`
292			`state <= RTS1;`
293			`else`
294			`state <= IFETCH;`
295			`end`
296			`PC_310: begin
297			`pc <= dat_i;`
298			load_what <= `NOTHING;
299			`if (isRTI \| isRTL \| isRTS)`
300			`isp <= isp_inc;`
301			`state <= IFETCH;`
302			`end`
303			`IA_310:
304			`begin`
305			`radr <= dat_i;`
306			`wadr <= dat_i;`
307			`wdat <= a;`
308			`if (isIY)`
309			`state <= IY3;`
310			else if (ir[7:0]==`ST_IX)
311			`state <= STORE1;`
312			`else begin`
313			load_what <= `WORD_310;
314			`state <= LOAD_MAC1;`
315			`end`
316			`end`
317			`IA_70:
318			`begin`
319			`radr <= radr34p1[33:2];`
320			`radr2LSB <= radr34p1[1:0];`
321	22	robfinch	`ia[7:0] <= dati;`
322	21	robfinch	load_what <= `IA_158;
323			`state <= LOAD_MAC1;`
324			`end`
325			`IA_158:
326			`begin`
327	22	robfinch	`ia[15:8] <= dati;`
328	21	robfinch	`ia[31:16] <= 16'h0000;`
329			`state <= isIY ? BYTE_IY5 : BYTE_IX5;`
330			`end`
331			`endcase`
332			`end`
333			`else if (err_i) begin`
334			`lock_o <= 1'b0;`
335			`cyc_o <= 1'b0;`
336			`stb_o <= 1'b0;`
337			`we_o <= 1'b0;`
338			`sel_o <= 4'h0;`
339			`dat_o <= 32'h0;`
340			`state <= BUS_ERROR;`
341			`end`
342			`RTS1:`
343			`begin`
344			`pc <= pc + 32'd1;`
345			`state <= IFETCH;`
346			`end`
347			`IY3:`
348			`begin`
349			`radr <= radr + y;`
350			`wadr <= radr + y;`
351			`wdat <= a;`
352			if (ir[7:0]==`ST_IY)
353			`state <= STORE1;`
354			`else begin`
355			load_what <= `WORD_310;
356			`state <= LOAD_MAC1;`
357			`end`
358			`isIY <= 1'b0;`
359			`end`
360			`BYTE_IX5:`
361			`begin`
362			`radr <= ia[31:2];`
363			`radr2LSB <= ia[1:0];`
364			load_what <= `BYTE_70;
365			`state <= LOAD_MAC1;`
366			if (ir[7:0]==`STA_IX \|\| ir[7:0]==`STA_I) begin
367			`wadr <= ia[31:2];`
368			`wadr2LSB <= ia[1:0];`
369			`wdat <= {4{acc8}};`
370			`state <= STORE1;`
371			`end`
372			`end`
373			`BYTE_IY5:`
374			`begin`
375			isIY <= `FALSE;
376			`radr <= iapy8[31:2];`
377			`radr2LSB <= iapy8[1:0];`
378			`$display("IY addr: %h", iapy8);`
379			if (ir[7:0]==`STA_IY) begin
380			`wadr <= iapy8[31:2];`
381			`wadr2LSB <= iapy8[1:0];`
382			`wdat <= {4{acc8}};`
383			`state <= STORE1;`
384			`end`
385			`else begin`
386			load_what <= `BYTE_70;
387			`state <= LOAD_MAC1;`
388			`end`
389			`end`

Browse

Tools

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_mac.v] - Blame information for rev 23