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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
LOAD_MAC1:
`ifdef SUPPORT_DCACHE
        if (unCachedData)
`endif
        begin
                if (isRMW)
                        lock_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= LOAD_MAC2;
        end
`ifdef SUPPORT_DCACHE
        else if (dhit) begin
                case(load_what)
                `WORD_310:
                                begin
                                        b <= rdat;
                                        b8 <= rdat8;            // for the orb instruction
                                        state <= CALC;
                                end
                `WORD_311:      // For pla/plx/ply/pop
                                        begin
                                                res <= rdat;
                                                state <= IFETCH;
                                        end
                `WORD_312:
                                begin
                                        b <= rdat;
                                        state <= retstate;
                                end
`ifdef SUPPORT_EM8
                `BYTE_70:
                                begin
                                        b8 <= rdat8;
                                        state <= BYTE_CALC;
                                end
                `BYTE_71:
                                begin
                                        res8 <= rdat8;
                                        state <= IFETCH;
                                end
`endif
                `SR_310:
                                begin
                                        cf <= rdat[0];
                                        zf <= rdat[1];
                                        im <= rdat[2];
                                        df <= rdat[3];
                                        bf <= rdat[4];
                                        em <= rdat[29];
                                        vf <= rdat[30];
                                        nf <= rdat[31];
                                        isp <= isp_inc;
                                        radr <= isp_inc;
                                        if (isRTI)
                                                load_what <= `PC_310;
                                        else    // PLP
                                                state <= IFETCH;
                                end
`ifdef SUPPORT_EM8
                `SR_70:
                                begin
                                        cf <= rdat8[0];
                                        zf <= rdat8[1];
                                        im <= rdat8[2];
                                        df <= rdat8[3];
                                        bf <= rdat8[4];
                                        vf <= rdat8[6];
                                        nf <= rdat8[7];
                                        if (isRTI) begin
                                                load_what <= `PC_70;
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        else    // PLP
                                                state <= IFETCH;
                                end
                `PC_70:
                                begin
                                        pc[7:0] <= rdat8;
                                        if (isRTI | isRTS | isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        else begin      // JMP (abs)
                                                radr <= radr34p1[33:2];
                                                radr2LSB <= radr34p1[1:0];
                                        end
                                        load_what <= `PC_158;
                                end
                `PC_158:
                                begin
                                        pc[15:8] <= rdat8;
                                        if (isRTI|isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                                load_what <= `PC_2316;
                                        end
                                        else if (isRTS) // rts instruction
                                                state <= RTS1;
                                        else                    // jmp (abs)
                                                state <= IFETCH;
                                end
                `PC_2316:
                                begin
                                        pc[23:16] <= rdat8;
                                        if (isRTI|isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        load_what <= `PC_3124;
                                end
                `PC_3124:
                                begin
                                        pc[31:24] <= rdat8;
                                        load_what <= `NOTHING;
                                        if (isRTL)
                                                state <= RTS1;
                                        else
                                                state <= IFETCH;
                                end
`endif
                `PC_310:
                                begin
                                        pc <= rdat;
                                        if (isRTI|isRTS|isRTL)
                                                isp <= isp_inc;
                                        load_what <= `NOTHING;
                                        state <= IFETCH;
                                end
                `IA_310:
                                begin
                                        radr <= rdat;
                                        wadr <= rdat;
                                        wdat <= a;
                                        if (isIY)
                                                state <= IY3;
                                        else if (ir[7:0]==`ST_IX)
                                                state <= STORE1;
                                        else begin
                                                load_what <= `WORD_310;
                                        end
                                end
`ifdef SUPPORT_EM8
                `IA_70:
                                begin
                                        radr <= radr34p1[33:2];
                                        radr2LSB <= radr34p1[1:0];
                                        ia[7:0] <= rdat8;
                                        load_what <= `IA_158;
                                end
                `IA_158:
                                begin
                                        ia[15:8] <= rdat8;
                                        ia[31:16] <= 16'h0000;
                                        state <= isIY ? BYTE_IY5 : BYTE_IX5;
                                end
`endif
                endcase
        end
        else
                dmiss <= `TRUE;
`endif
LOAD_MAC2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                case(load_what)
                `WORD_310:
                                        begin
                                                b <= dat_i;
                                                b8 <= dati;             // for the orb instruction
                                                state <= CALC;
                                        end
                `WORD_311:      // For pla/plx/ply/pop/ldx/ldy
                                        begin
                                                res <= dat_i;
                                                state <= IFETCH;
                                        end
                `WORD_312:
                                begin
                                        b <= dat_i;
                                        state <= retstate;
                                end
`ifdef SUPPORT_EM8
                `BYTE_70:
                                        begin
                                                b8 <= dati;
                                                state <= BYTE_CALC;
                                        end
                `BYTE_71:
                                begin
                                        res8 <= dati;
                                        state <= IFETCH;
                                end
`endif
                `SR_310:        begin
                                                cf <= dat_i[0];
                                                zf <= dat_i[1];
                                                im <= dat_i[2];
                                                df <= dat_i[3];
                                                bf <= dat_i[4];
                                                em <= dat_i[29];
                                                vf <= dat_i[30];
                                                nf <= dat_i[31];
                                                isp <= isp_inc;
                                                radr <= isp_inc;
                                                if (isRTI) begin
                                                        load_what <= `PC_310;
                                                        state <= LOAD_MAC1;
                                                end
                                                else    // PLP
                                                        state <= IFETCH;
                                        end
`ifdef SUPPORT_EM8
                `SR_70:         begin
                                                cf <= dati[0];
                                                zf <= dati[1];
                                                im <= dati[2];
                                                df <= dati[3];
                                                bf <= dati[4];
                                                vf <= dati[6];
                                                nf <= dati[7];
                                                if (isRTI) begin
                                                        load_what <= `PC_70;
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                        state <= LOAD_MAC1;
                                                end
                                                else    // PLP
                                                        state <= IFETCH;
                                        end
                `PC_70:         begin
                                                pc[7:0] <= dati;
                                                load_what <= `PC_158;
                                                if (isRTI|isRTS|isRTL) begin
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                end
                                                else begin      // JMP (abs)
                                                        radr <= radr34p1[33:2];
                                                        radr2LSB <= radr34p1[1:0];
                                                end
                                                state <= LOAD_MAC1;
                                        end
                `PC_158:        begin
                                                pc[15:8] <= dati;
                                                if (isRTI|isRTL) begin
                                                        load_what <= `PC_2316;
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                        state <= LOAD_MAC1;
                                                end
                                                else if (isRTS) // rts instruction
                                                        state <= RTS1;
                                                else                    // jmp (abs)
                                                        state <= IFETCH;
                                        end
                `PC_2316:       begin
                                                pc[23:16] <= dati;
                                                load_what <= `PC_3124;
                                                if (isRTI|isRTL) begin
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                end
                                                state <= LOAD_MAC1;
                                        end
                `PC_3124:       begin
                                                pc[31:24] <= dati;
                                                load_what <= `NOTHING;
                                                if (isRTL)
                                                        state <= RTS1;
                                                else
                                                        state <= IFETCH;
                                        end
`endif
                `PC_310:        begin
                                                pc <= dat_i;
                                                load_what <= `NOTHING;
                                                if (isRTI | isRTL | isRTS)
                                                        isp <= isp_inc;
                                                state <= IFETCH;
                                        end
                `IA_310:
                                begin
                                        radr <= dat_i;
                                        wadr <= dat_i;
                                        wdat <= a;
                                        if (isIY)
                                                state <= IY3;
                                        else if (ir[7:0]==`ST_IX)
                                                state <= STORE1;
                                        else begin
                                                load_what <= `WORD_310;
                                                state <= LOAD_MAC1;
                                        end
                                end
`ifdef SUPPORT_EM8
                `IA_70:
                                begin
                                        radr <= radr34p1[33:2];
                                        radr2LSB <= radr34p1[1:0];
                                        ia[7:0] <= dati;
                                        load_what <= `IA_158;
                                        state <= LOAD_MAC1;
                                end
                `IA_158:
                                begin
                                        ia[15:8] <= dati;
                                        ia[31:16] <= 16'h0000;
                                        state <= isIY ? BYTE_IY5 : BYTE_IX5;
                                end
`endif
                endcase
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
`endif
RTS1:
        begin
                pc <= pc + 32'd1;
                state <= IFETCH;
        end
IY3:
        begin
                radr <= radr + y;
                wadr <= radr + y;
                if (ir[7:0]==`ST_IY) begin
                        store_what <= `STW_A;
                        state <= STORE1;
                end
                else begin
                        load_what <= `WORD_310;
                        state <= LOAD_MAC1;
                end
                isIY <= 1'b0;
        end
`ifdef SUPPORT_EM8
BYTE_IX5:
        begin
                radr <= ia[31:2];
                radr2LSB <= ia[1:0];
                load_what <= `BYTE_70;
                state <= LOAD_MAC1;
                if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I) begin
                        wadr <= ia[31:2];
                        wadr2LSB <= ia[1:0];
                        store_what <= `STW_ACC8;
                        state <= STORE1;
                end
        end
BYTE_IY5:
        begin
                isIY <= `FALSE;
                radr <= iapy8[31:2];
                radr2LSB <= iapy8[1:0];
                $display("IY addr: %h", iapy8);
                if (ir[7:0]==`STA_IY) begin
                        wadr <= iapy8[31:2];
                        wadr2LSB <= iapy8[1:0];
                        store_what <= `STW_ACC8;
                        state <= STORE1;
                end
                else begin
                        load_what <= `BYTE_70;
                        state <= LOAD_MAC1;
                end
        end
`endif

Line No.	Rev	Author	Line
1	21	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`LOAD_MAC1:`
24	30	robfinch	`ifdef SUPPORT_DCACHE
25			`if (unCachedData)`
26			`endif
27			`begin`
28	21	robfinch	`if (isRMW)`
29			`lock_o <= 1'b1;`
30			`cyc_o <= 1'b1;`
31			`stb_o <= 1'b1;`
32			`sel_o <= 4'hF;`
33			`adr_o <= {radr,2'b00};`
34			`state <= LOAD_MAC2;`
35			`end`
36	30	robfinch	`ifdef SUPPORT_DCACHE
37	21	robfinch	`else if (dhit) begin`
38			`case(load_what)`
39			`WORD_310:
40			`begin`
41			`b <= rdat;`
42			`b8 <= rdat8; // for the orb instruction`
43			`state <= CALC;`
44			`end`
45			`WORD_311: // For pla/plx/ply/pop
46			`begin`
47			`res <= rdat;`
48			`state <= IFETCH;`
49			`end`
50	23	robfinch	`WORD_312:
51			`begin`
52			`b <= rdat;`
53			`state <= retstate;`
54			`end`
55	30	robfinch	`ifdef SUPPORT_EM8
56	21	robfinch	`BYTE_70:
57			`begin`
58			`b8 <= rdat8;`
59			`state <= BYTE_CALC;`
60			`end`
61			`BYTE_71:
62			`begin`
63			`res8 <= rdat8;`
64			`state <= IFETCH;`
65			`end`
66	30	robfinch	`endif
67	21	robfinch	`SR_310:
68			`begin`
69			`cf <= rdat[0];`
70			`zf <= rdat[1];`
71			`im <= rdat[2];`
72			`df <= rdat[3];`
73			`bf <= rdat[4];`
74			`em <= rdat[29];`
75			`vf <= rdat[30];`
76			`nf <= rdat[31];`
77			`isp <= isp_inc;`
78			`radr <= isp_inc;`
79			`if (isRTI)`
80			load_what <= `PC_310;
81			`else // PLP`
82			`state <= IFETCH;`
83			`end`
84	30	robfinch	`ifdef SUPPORT_EM8
85	21	robfinch	`SR_70:
86			`begin`
87			`cf <= rdat8[0];`
88			`zf <= rdat8[1];`
89			`im <= rdat8[2];`
90			`df <= rdat8[3];`
91			`bf <= rdat8[4];`
92			`vf <= rdat8[6];`
93			`nf <= rdat8[7];`
94			`if (isRTI) begin`
95			load_what <= `PC_70;
96			`radr <= {spage[31:8],sp_inc[7:2]};`
97			`radr2LSB <= sp_inc[1:0];`
98			`sp <= sp_inc;`
99			`end`
100			`else // PLP`
101			`state <= IFETCH;`
102			`end`
103			`PC_70:
104			`begin`
105			`pc[7:0] <= rdat8;`
106			`if (isRTI \| isRTS \| isRTL) begin`
107			`radr <= {spage[31:8],sp_inc[7:2]};`
108			`radr2LSB <= sp_inc[1:0];`
109			`sp <= sp_inc;`
110			`end`
111			`else begin // JMP (abs)`
112			`radr <= radr34p1[33:2];`
113			`radr2LSB <= radr34p1[1:0];`
114			`end`
115			load_what <= `PC_158;
116			`end`
117			`PC_158:
118			`begin`
119			`pc[15:8] <= rdat8;`
120			`if (isRTI\|isRTL) begin`
121			`radr <= {spage[31:8],sp_inc[7:2]};`
122			`radr2LSB <= sp_inc[1:0];`
123			`sp <= sp_inc;`
124			load_what <= `PC_2316;
125			`end`
126			`else if (isRTS) // rts instruction`
127			`state <= RTS1;`
128			`else // jmp (abs)`
129			`state <= IFETCH;`
130			`end`
131			`PC_2316:
132			`begin`
133			`pc[23:16] <= rdat8;`
134			`if (isRTI\|isRTL) begin`
135			`radr <= {spage[31:8],sp_inc[7:2]};`
136			`radr2LSB <= sp_inc[1:0];`
137			`sp <= sp_inc;`
138			`end`
139			load_what <= `PC_3124;
140			`end`
141			`PC_3124:
142			`begin`
143			`pc[31:24] <= rdat8;`
144			load_what <= `NOTHING;
145			`if (isRTL)`
146			`state <= RTS1;`
147			`else`
148			`state <= IFETCH;`
149			`end`
150	30	robfinch	`endif
151	21	robfinch	`PC_310:
152			`begin`
153			`pc <= rdat;`
154			`if (isRTI\|isRTS\|isRTL)`
155			`isp <= isp_inc;`
156			load_what <= `NOTHING;
157			`state <= IFETCH;`
158			`end`
159			`IA_310:
160			`begin`
161			`radr <= rdat;`
162			`wadr <= rdat;`
163			`wdat <= a;`
164			`if (isIY)`
165			`state <= IY3;`
166			else if (ir[7:0]==`ST_IX)
167			`state <= STORE1;`
168			`else begin`
169			load_what <= `WORD_310;
170			`end`
171			`end`
172	30	robfinch	`ifdef SUPPORT_EM8
173	21	robfinch	`IA_70:
174			`begin`
175			`radr <= radr34p1[33:2];`
176			`radr2LSB <= radr34p1[1:0];`
177			`ia[7:0] <= rdat8;`
178			load_what <= `IA_158;
179			`end`
180			`IA_158:
181			`begin`
182			`ia[15:8] <= rdat8;`
183			`ia[31:16] <= 16'h0000;`
184			`state <= isIY ? BYTE_IY5 : BYTE_IX5;`
185			`end`
186	30	robfinch	`endif
187	21	robfinch	`endcase`
188			`end`
189			`else`
190			dmiss <= `TRUE;
191	30	robfinch	`endif
192	21	robfinch	`LOAD_MAC2:`
193			`if (ack_i) begin`
194			`cyc_o <= 1'b0;`
195			`stb_o <= 1'b0;`
196			`sel_o <= 4'h0;`
197			`adr_o <= 34'h0;`
198			`case(load_what)`
199			`WORD_310:
200			`begin`
201			`b <= dat_i;`
202			`b8 <= dati; // for the orb instruction`
203			`state <= CALC;`
204			`end`
205			`WORD_311: // For pla/plx/ply/pop/ldx/ldy
206			`begin`
207			`res <= dat_i;`
208			`state <= IFETCH;`
209			`end`
210	23	robfinch	`WORD_312:
211			`begin`
212			`b <= dat_i;`
213			`state <= retstate;`
214			`end`
215	30	robfinch	`ifdef SUPPORT_EM8
216	21	robfinch	`BYTE_70:
217			`begin`
218			`b8 <= dati;`
219			`state <= BYTE_CALC;`
220			`end`
221			`BYTE_71:
222			`begin`
223			`res8 <= dati;`
224			`state <= IFETCH;`
225			`end`
226	30	robfinch	`endif
227	21	robfinch	`SR_310: begin
228			`cf <= dat_i[0];`
229			`zf <= dat_i[1];`
230			`im <= dat_i[2];`
231			`df <= dat_i[3];`
232			`bf <= dat_i[4];`
233			`em <= dat_i[29];`
234			`vf <= dat_i[30];`
235			`nf <= dat_i[31];`
236			`isp <= isp_inc;`
237			`radr <= isp_inc;`
238			`if (isRTI) begin`
239			load_what <= `PC_310;
240			`state <= LOAD_MAC1;`
241			`end`
242			`else // PLP`
243			`state <= IFETCH;`
244			`end`
245	30	robfinch	`ifdef SUPPORT_EM8
246	21	robfinch	`SR_70: begin
247			`cf <= dati[0];`
248			`zf <= dati[1];`
249			`im <= dati[2];`
250			`df <= dati[3];`
251			`bf <= dati[4];`
252			`vf <= dati[6];`
253			`nf <= dati[7];`
254			`if (isRTI) begin`
255			load_what <= `PC_70;
256			`radr <= {spage[31:8],sp_inc[7:2]};`
257			`radr2LSB <= sp_inc[1:0];`
258			`sp <= sp_inc;`
259			`state <= LOAD_MAC1;`
260			`end`
261			`else // PLP`
262			`state <= IFETCH;`
263			`end`
264			`PC_70: begin
265			`pc[7:0] <= dati;`
266			load_what <= `PC_158;
267			`if (isRTI\|isRTS\|isRTL) begin`
268			`radr <= {spage[31:8],sp_inc[7:2]};`
269			`radr2LSB <= sp_inc[1:0];`
270			`sp <= sp_inc;`
271			`end`
272			`else begin // JMP (abs)`
273			`radr <= radr34p1[33:2];`
274			`radr2LSB <= radr34p1[1:0];`
275			`end`
276			`state <= LOAD_MAC1;`
277			`end`
278			`PC_158: begin
279			`pc[15:8] <= dati;`
280			`if (isRTI\|isRTL) begin`
281			load_what <= `PC_2316;
282			`radr <= {spage[31:8],sp_inc[7:2]};`
283			`radr2LSB <= sp_inc[1:0];`
284			`sp <= sp_inc;`
285			`state <= LOAD_MAC1;`
286			`end`
287			`else if (isRTS) // rts instruction`
288			`state <= RTS1;`
289			`else // jmp (abs)`
290			`state <= IFETCH;`
291			`end`
292			`PC_2316: begin
293			`pc[23:16] <= dati;`
294			load_what <= `PC_3124;
295			`if (isRTI\|isRTL) begin`
296			`radr <= {spage[31:8],sp_inc[7:2]};`
297			`radr2LSB <= sp_inc[1:0];`
298			`sp <= sp_inc;`
299			`end`
300			`state <= LOAD_MAC1;`
301			`end`
302			`PC_3124: begin
303			`pc[31:24] <= dati;`
304			load_what <= `NOTHING;
305			`if (isRTL)`
306			`state <= RTS1;`
307			`else`
308			`state <= IFETCH;`
309			`end`
310	30	robfinch	`endif
311	21	robfinch	`PC_310: begin
312			`pc <= dat_i;`
313			load_what <= `NOTHING;
314			`if (isRTI \| isRTL \| isRTS)`
315			`isp <= isp_inc;`
316			`state <= IFETCH;`
317			`end`
318			`IA_310:
319			`begin`
320			`radr <= dat_i;`
321			`wadr <= dat_i;`
322			`wdat <= a;`
323			`if (isIY)`
324			`state <= IY3;`
325			else if (ir[7:0]==`ST_IX)
326			`state <= STORE1;`
327			`else begin`
328			load_what <= `WORD_310;
329			`state <= LOAD_MAC1;`
330			`end`
331			`end`
332	30	robfinch	`ifdef SUPPORT_EM8
333	21	robfinch	`IA_70:
334			`begin`
335			`radr <= radr34p1[33:2];`
336			`radr2LSB <= radr34p1[1:0];`
337	22	robfinch	`ia[7:0] <= dati;`
338	21	robfinch	load_what <= `IA_158;
339			`state <= LOAD_MAC1;`
340			`end`
341			`IA_158:
342			`begin`
343	22	robfinch	`ia[15:8] <= dati;`
344	21	robfinch	`ia[31:16] <= 16'h0000;`
345			`state <= isIY ? BYTE_IY5 : BYTE_IX5;`
346			`end`
347	30	robfinch	`endif
348	21	robfinch	`endcase`
349			`end`
350	30	robfinch	`ifdef SUPPORT_BERR
351	21	robfinch	`else if (err_i) begin`
352			`lock_o <= 1'b0;`
353			`cyc_o <= 1'b0;`
354			`stb_o <= 1'b0;`
355			`we_o <= 1'b0;`
356			`sel_o <= 4'h0;`
357			`dat_o <= 32'h0;`
358			`state <= BUS_ERROR;`
359			`end`
360	30	robfinch	`endif
361	21	robfinch	`RTS1:`
362			`begin`
363			`pc <= pc + 32'd1;`
364			`state <= IFETCH;`
365			`end`
366			`IY3:`
367			`begin`
368			`radr <= radr + y;`
369			`wadr <= radr + y;`
370	30	robfinch	if (ir[7:0]==`ST_IY) begin
371			store_what <= `STW_A;
372	21	robfinch	`state <= STORE1;`
373	30	robfinch	`end`
374	21	robfinch	`else begin`
375			load_what <= `WORD_310;
376			`state <= LOAD_MAC1;`
377			`end`
378			`isIY <= 1'b0;`
379			`end`
380	30	robfinch	`ifdef SUPPORT_EM8
381	21	robfinch	`BYTE_IX5:`
382			`begin`
383			`radr <= ia[31:2];`
384			`radr2LSB <= ia[1:0];`
385			load_what <= `BYTE_70;
386			`state <= LOAD_MAC1;`
387			if (ir[7:0]==`STA_IX \|\| ir[7:0]==`STA_I) begin
388			`wadr <= ia[31:2];`
389			`wadr2LSB <= ia[1:0];`
390	30	robfinch	store_what <= `STW_ACC8;
391	21	robfinch	`state <= STORE1;`
392			`end`
393			`end`
394			`BYTE_IY5:`
395			`begin`
396			isIY <= `FALSE;
397			`radr <= iapy8[31:2];`
398			`radr2LSB <= iapy8[1:0];`
399			`$display("IY addr: %h", iapy8);`
400			if (ir[7:0]==`STA_IY) begin
401			`wadr <= iapy8[31:2];`
402			`wadr2LSB <= iapy8[1:0];`
403	30	robfinch	store_what <= `STW_ACC8;
404	21	robfinch	`state <= STORE1;`
405			`end`
406			`else begin`
407			load_what <= `BYTE_70;
408			`state <= LOAD_MAC1;`
409			`end`
410			`end`
411	30	robfinch	`endif

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