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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_tsk.v] - Blame information for rev 32

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
task load_tsk;
input [31:0] dat;
input [7:0] dat8;
begin
        case(load_what)
        `WORD_310:
                                begin
                                        b <= dat;
                                        b8 <= dat8;             // for the orb instruction
                                        state <= CALC;
                                end
        `WORD_311:      // For pla/plx/ply/pop/ldx/ldy
                                begin
                                        res <= dat;
                                        state <= isPopa ? LOAD_MAC3 : IFETCH;
                                end
        `WORD_312:
                        begin
                                b <= dat;
                                radr <= y;
                                wadr <= y;
                                store_what <= `STW_B;
                                x <= res;
                                acc <= acc - 32'd1;
                                state <= STORE1;
                        end
        `WORD_313:
                        begin
                                a <= dat;
                                radr <= y;
                                load_what <= `WORD_314;
                                x <= res;
                                state <= LOAD_MAC1;
                        end
        `WORD_314:
                        begin
                                b <= dat;
                                acc <= acc - 32'd1;
                                state <= CMPS1;
                        end
`ifdef SUPPORT_EM8
        `BYTE_70:
                                begin
                                        b8 <= dat8;
                                        state <= BYTE_CALC;
                                end
        `BYTE_71:
                        begin
                                res8 <= dat8;
                                state <= BYTE_IFETCH;
                        end
`endif
        `SR_310:        begin
                                        cf <= dat[0];
                                        zf <= dat[1];
                                        im <= dat[2];
                                        df <= dat[3];
                                        bf <= dat[4];
                                        tf <= dat[28];
                                        em <= dat[29];
                                        vf <= dat[30];
                                        nf <= dat[31];
                                        if (isRTI) begin
                                                radr <= isp;
                                                isp <= isp_inc;
                                                load_what <= `PC_310;
                                                state <= LOAD_MAC1;
                                        end
                                        else    // PLP
                                                state <= IFETCH;
                                end
`ifdef SUPPORT_EM8
        `SR_70:         begin
                                        cf <= dat8[0];
                                        zf <= dat8[1];
                                        im <= dat8[2];
                                        df <= dat8[3];
                                        bf <= dat8[4];
                                        vf <= dat8[6];
                                        nf <= dat8[7];
                                        if (isRTI) begin
                                                load_what <= `PC_70;
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                                state <= LOAD_MAC1;
                                        end
                                        else    // PLP
                                                state <= BYTE_IFETCH;
                                end
        `PC_70:         begin
                                        pc[7:0] <= dat8;
                                        load_what <= `PC_158;
                                        if (isRTI|isRTS|isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        else begin      // JMP (abs)
                                                radr <= radr34p1[33:2];
                                                radr2LSB <= radr34p1[1:0];
                                        end
                                        state <= LOAD_MAC1;
                                end
        `PC_158:        begin
                                        pc[15:8] <= dat8;
                                        if (isRTI|isRTL) begin
                                                load_what <= `PC_2316;
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                                state <= LOAD_MAC1;
                                        end
                                        else if (isRTS) // rts instruction
                                                state <= RTS1;
                                        else                    // jmp (abs)
                                                state <= BYTE_IFETCH;
                                end
        `PC_2316:       begin
                                        pc[23:16] <= dat8;
                                        load_what <= `PC_3124;
                                        if (isRTI|isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        state <= LOAD_MAC1;
                                end
        `PC_3124:       begin
                                        pc[31:24] <= dat8;
                                        load_what <= `NOTHING;
                                        if (isRTL)
                                                state <= RTS1;
                                        else
                                                state <= BYTE_IFETCH;
                                end
`endif
        `PC_310:        begin
                                        pc <= dat;
                                        load_what <= `NOTHING;
                                        if (isRTI) begin
                                                km <= `FALSE;
                                                hist_capture <= `TRUE;
                                        end
                                        state <= em ? BYTE_IFETCH : IFETCH;
                                end
        `IA_310:
                        begin
                                radr <= dat;
                                wadr <= dat;
                                wdat <= a;
                                if (isIY)
                                        state <= IY3;
                                else if (ir9==`ST_IX)
                                        state <= STORE1;
                                else begin
                                        load_what <= `WORD_310;
                                        state <= LOAD_MAC1;
                                end
                        end
`ifdef SUPPORT_EM8
        `IA_70:
                        begin
                                radr <= radr34p1[33:2];
                                radr2LSB <= radr34p1[1:0];
                                ia[7:0] <= dat8;
                                load_what <= `IA_158;
                                state <= LOAD_MAC1;
                        end
        `IA_158:
                        begin
                                ia[15:8] <= dat8;
                                ia[31:16] <= abs8[31:16];
                                state <= isIY ? BYTE_IY5 : BYTE_IX5;
                        end
`endif
        endcase
end
endtask

Line No.	Rev	Author	Line
1	32	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`task load_tsk;`
24			`input [31:0] dat;`
25			`input [7:0] dat8;`
26			`begin`
27			`case(load_what)`
28			`WORD_310:
29			`begin`
30			`b <= dat;`
31			`b8 <= dat8; // for the orb instruction`
32			`state <= CALC;`
33			`end`
34			`WORD_311: // For pla/plx/ply/pop/ldx/ldy
35			`begin`
36			`res <= dat;`
37			`state <= isPopa ? LOAD_MAC3 : IFETCH;`
38			`end`
39			`WORD_312:
40			`begin`
41			`b <= dat;`
42			`radr <= y;`
43			`wadr <= y;`
44			store_what <= `STW_B;
45			`x <= res;`
46			`acc <= acc - 32'd1;`
47			`state <= STORE1;`
48			`end`
49			`WORD_313:
50			`begin`
51			`a <= dat;`
52			`radr <= y;`
53			load_what <= `WORD_314;
54			`x <= res;`
55			`state <= LOAD_MAC1;`
56			`end`
57			`WORD_314:
58			`begin`
59			`b <= dat;`
60			`acc <= acc - 32'd1;`
61			`state <= CMPS1;`
62			`end`
63			`ifdef SUPPORT_EM8
64			`BYTE_70:
65			`begin`
66			`b8 <= dat8;`
67			`state <= BYTE_CALC;`
68			`end`
69			`BYTE_71:
70			`begin`
71			`res8 <= dat8;`
72			`state <= BYTE_IFETCH;`
73			`end`
74			`endif
75			`SR_310: begin
76			`cf <= dat[0];`
77			`zf <= dat[1];`
78			`im <= dat[2];`
79			`df <= dat[3];`
80			`bf <= dat[4];`
81			`tf <= dat[28];`
82			`em <= dat[29];`
83			`vf <= dat[30];`
84			`nf <= dat[31];`
85			`if (isRTI) begin`
86			`radr <= isp;`
87			`isp <= isp_inc;`
88			load_what <= `PC_310;
89			`state <= LOAD_MAC1;`
90			`end`
91			`else // PLP`
92			`state <= IFETCH;`
93			`end`
94			`ifdef SUPPORT_EM8
95			`SR_70: begin
96			`cf <= dat8[0];`
97			`zf <= dat8[1];`
98			`im <= dat8[2];`
99			`df <= dat8[3];`
100			`bf <= dat8[4];`
101			`vf <= dat8[6];`
102			`nf <= dat8[7];`
103			`if (isRTI) begin`
104			load_what <= `PC_70;
105			`radr <= {spage[31:8],sp_inc[7:2]};`
106			`radr2LSB <= sp_inc[1:0];`
107			`sp <= sp_inc;`
108			`state <= LOAD_MAC1;`
109			`end`
110			`else // PLP`
111			`state <= BYTE_IFETCH;`
112			`end`
113			`PC_70: begin
114			`pc[7:0] <= dat8;`
115			load_what <= `PC_158;
116			`if (isRTI\|isRTS\|isRTL) begin`
117			`radr <= {spage[31:8],sp_inc[7:2]};`
118			`radr2LSB <= sp_inc[1:0];`
119			`sp <= sp_inc;`
120			`end`
121			`else begin // JMP (abs)`
122			`radr <= radr34p1[33:2];`
123			`radr2LSB <= radr34p1[1:0];`
124			`end`
125			`state <= LOAD_MAC1;`
126			`end`
127			`PC_158: begin
128			`pc[15:8] <= dat8;`
129			`if (isRTI\|isRTL) begin`
130			load_what <= `PC_2316;
131			`radr <= {spage[31:8],sp_inc[7:2]};`
132			`radr2LSB <= sp_inc[1:0];`
133			`sp <= sp_inc;`
134			`state <= LOAD_MAC1;`
135			`end`
136			`else if (isRTS) // rts instruction`
137			`state <= RTS1;`
138			`else // jmp (abs)`
139			`state <= BYTE_IFETCH;`
140			`end`
141			`PC_2316: begin
142			`pc[23:16] <= dat8;`
143			load_what <= `PC_3124;
144			`if (isRTI\|isRTL) begin`
145			`radr <= {spage[31:8],sp_inc[7:2]};`
146			`radr2LSB <= sp_inc[1:0];`
147			`sp <= sp_inc;`
148			`end`
149			`state <= LOAD_MAC1;`
150			`end`
151			`PC_3124: begin
152			`pc[31:24] <= dat8;`
153			load_what <= `NOTHING;
154			`if (isRTL)`
155			`state <= RTS1;`
156			`else`
157			`state <= BYTE_IFETCH;`
158			`end`
159			`endif
160			`PC_310: begin
161			`pc <= dat;`
162			load_what <= `NOTHING;
163			`if (isRTI) begin`
164			km <= `FALSE;
165			hist_capture <= `TRUE;
166			`end`
167			`state <= em ? BYTE_IFETCH : IFETCH;`
168			`end`
169			`IA_310:
170			`begin`
171			`radr <= dat;`
172			`wadr <= dat;`
173			`wdat <= a;`
174			`if (isIY)`
175			`state <= IY3;`
176			else if (ir9==`ST_IX)
177			`state <= STORE1;`
178			`else begin`
179			load_what <= `WORD_310;
180			`state <= LOAD_MAC1;`
181			`end`
182			`end`
183			`ifdef SUPPORT_EM8
184			`IA_70:
185			`begin`
186			`radr <= radr34p1[33:2];`
187			`radr2LSB <= radr34p1[1:0];`
188			`ia[7:0] <= dat8;`
189			load_what <= `IA_158;
190			`state <= LOAD_MAC1;`
191			`end`
192			`IA_158:
193			`begin`
194			`ia[15:8] <= dat8;`
195			`ia[31:16] <= abs8[31:16];`
196			`state <= isIY ? BYTE_IY5 : BYTE_IX5;`
197			`end`
198			`endif
199			`endcase`
200			`end`
201			`endtask`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_tsk.v] - Blame information for rev 32