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// ============================================================================

//        __

//   \\__/ o\    (C) 2013  Robert Finch, Stratford

//    \  __ /    All rights reserved.

//     \/_//     robfinch<remove>@opencores.org

//       ||

//

// This source file is free software: you can redistribute it and/or modify 

// it under the terms of the GNU Lesser General Public License as published 

// by the Free Software Foundation, either version 3 of the License, or     

// (at your option) any later version.                                      

//                                                                          

// This source file is distributed in the hope that it will be useful,      

// but WITHOUT ANY WARRANTY; without even the implied warranty of           

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            

// GNU General Public License for more details.                             

//                                                                          

// You should have received a copy of the GNU General Public License        

// along with this program.  If not, see <http://www.gnu.org/licenses/>.    

//                                                   

// State for pushing processor regs. Works for both 8 and 32 bit modes.                       

// ============================================================================

//

PHP1:

        if (ack_i) begin

                state <= IFETCH;

                retstate <= IFETCH;

                cyc_o <= 1'b0;

                stb_o <= 1'b0;

                we_o <= 1'b0;

                sel_o <= 4'h0;

                adr_o <= 34'd0;

                dat_o <= 32'd0;

                pc <= pc + 32'd1;       // <= this is different from STORE2

                if (dhit) begin

                        wr <= 1'b1;

                        wrsel <= sel_o;

                end

                else if (write_allocate) begin

                        state <= WAIT_DHIT;

                        dmiss <= `TRUE;

                end

        end

        else if (err_i) begin

                lock_o <= 1'b0;

                cyc_o <= 1'b0;

                stb_o <= 1'b0;

                we_o <= 1'b0;

                sel_o <= 4'h0;

                dat_o <= 32'h0;

                state <= BUS_ERROR;

        end