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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// rtf65002.v
//  - 32 bit CPU
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
`define TRUE            1'b1
`define FALSE           1'b0
 
`define SUPPORT_ICACHE  1'b1
`define ICACHE_4K               1'b1
//`define ICACHE_16K            1'b1
//`define ICACHE_2WAY           1'b1
//`define SUPPORT_DCACHE        1'b1
`define SUPPORT_BCD             1'b1
`define SUPPORT_DIVMOD          1'b1
`define SUPPORT_EM8             1'b1
//`define SUPPORT_EXEC  1'b1
`define SUPPORT_BERR    1'b1
`define SUPPORT_STRING  1'b1
`define SUPPORT_SHIFT   1'b1
 
`define RST_VECT        34'h3FFFFFFF8
`define NMI_VECT        34'h3FFFFFFF4
`define IRQ_VECT        34'h3FFFFFFF0
`define BRK_VECTNO      9'd0
`define SLP_VECTNO      9'd1
`define BYTE_RST_VECT   34'h00000FFFC
`define BYTE_NMI_VECT   34'h00000FFFA
`define BYTE_IRQ_VECT   34'h00000FFFE
 
`define BRK                     9'h00
`define RTI                     9'h40
`define RTS                     9'h60
`define PHP                     9'h08
`define CLC                     9'h18
`define PLP                     9'h28
`define SEC                     9'h38
`define PHA                     9'h48
`define CLI                     9'h58
`define PLA                     9'h68
`define SEI                     9'h78
`define DEY                     9'h88
`define TYA                     9'h98
`define TAY                     9'hA8
`define CLV                     9'hB8
`define INY                     9'hC8
`define CLD                     9'hD8
`define INX                     9'hE8
`define SED                     9'hF8
`define ROR_ACC         9'h6A
`define TXA                     9'h8A
`define TXS                     9'h9A
`define TAX                     9'hAA
`define TSX                     9'hBA
`define DEX                     9'hCA
`define NOP                     9'hEA
`define TXY                     9'h9B
`define TYX                     9'hBB
`define TAS                     9'h1B
`define TSA                     9'h3B
`define TRS                     9'h8B
`define TSR                     9'hAB
`define STP                     9'hDB
`define NAT                     9'hFB
`define EMM                     9'hFB
`define INA                     9'h1A
`define DEA                     9'h3A
 
`define RR                      9'h02
`define ADD_RR                  4'd0
`define SUB_RR                  4'd1
`define CMP_RR                  4'd2
`define AND_RR                  4'd3
`define EOR_RR                  4'd4
`define OR_RR                   4'd5
`define MUL_RR                  4'd8
`define MULS_RR                 4'd9
`define DIV_RR                  4'd10
`define DIVS_RR                 4'd11
`define MOD_RR                  4'd12
`define MODS_RR                 4'd13
`define ASL_RRR                 4'd14
`define LSR_RRR                 4'd15
`define LD_RR           9'h7B
 
`define ADD_IMM8        9'h65           // 8 bit operand
`define ADD_IMM16       9'h79           // 16 bit operand
`define ADD_IMM32       9'h69           // 32 bit operand
`define ADD_ZPX         9'h75           // there is no ZP mode, use R0 to syntheisze
`define ADD_IX          9'h61
`define ADD_IY          9'h71
`define ADD_ABS         9'h6D
`define ADD_ABSX        9'h7D
`define ADD_RIND        9'h72
`define ADD_DSP         9'h63
 
`define SUB_IMM8        9'hE5
`define SUB_IMM16       9'hF9
`define SUB_IMM32       9'hE9
`define SUB_ZPX         9'hF5
`define SUB_IX          9'hE1
`define SUB_IY          9'hF1
`define SUB_ABS         9'hED
`define SUB_ABSX        9'hFD
`define SUB_RIND        9'hF2
`define SUB_DSP         9'hE3
 
// CMP = SUB r0,....
 
`define ADC_IMM         9'h69
`define ADC_ZP          9'h65
`define ADC_ZPX         9'h75
`define ADC_IX          9'h61
`define ADC_IY          9'h71
`define ADC_ABS         9'h6D
`define ADC_ABSX        9'h7D
`define ADC_ABSY        9'h79
`define ADC_I           9'h72
 
`define SBC_IMM         9'hE9
`define SBC_ZP          9'hE5
`define SBC_ZPX         9'hF5
`define SBC_IX          9'hE1
`define SBC_IY          9'hF1
`define SBC_ABS         9'hED
`define SBC_ABSX        9'hFD
`define SBC_ABSY        9'hF9
`define SBC_I           9'hF2
 
`define CMP_IMM8        9'hC5
`define CMP_IMM32       9'hC9
`define CMP_IMM         9'hC9
`define CMP_ZP          9'hC5
`define CMP_ZPX         9'hD5
`define CMP_IX          9'hC1
`define CMP_IY          9'hD1
`define CMP_ABS         9'hCD
`define CMP_ABSX        9'hDD
`define CMP_ABSY        9'hD9
`define CMP_I           9'hD2
 
 
`define LDA_IMM8        9'hA5
`define LDA_IMM16       9'hB9
`define LDA_IMM32       9'hA9
 
`define AND_IMM8        9'h25
`define AND_IMM16       9'h39
`define AND_IMM32       9'h29
`define AND_IMM         9'h29
`define AND_ZP          9'h25
`define AND_ZPX         9'h35
`define AND_IX          9'h21
`define AND_IY          9'h31
`define AND_ABS         9'h2D
`define AND_ABSX        9'h3D
`define AND_ABSY        9'h39
`define AND_RIND        9'h32
`define AND_I           9'h32
`define AND_DSP         9'h23
 
`define OR_IMM8         9'h05
`define OR_IMM16        9'h19
`define OR_IMM32        9'h09
`define OR_ZPX          9'h15
`define OR_IX           9'h01
`define OR_IY           9'h11
`define OR_ABS          9'h0D
`define OR_ABSX         9'h1D
`define OR_RIND         9'h12
`define OR_DSP          9'h03
 
`define ORA_IMM         9'h09
`define ORA_ZP          9'h05
`define ORA_ZPX         9'h15
`define ORA_IX          9'h01
`define ORA_IY          9'h11
`define ORA_ABS         9'h0D
`define ORA_ABSX        9'h1D
`define ORA_ABSY        9'h19
`define ORA_I           9'h12
 
`define EOR_IMM         9'h49
`define EOR_IMM8        9'h45
`define EOR_IMM16       9'h59
`define EOR_IMM32       9'h49
`define EOR_ZP          9'h45
`define EOR_ZPX         9'h55
`define EOR_IX          9'h41
`define EOR_IY          9'h51
`define EOR_ABS         9'h4D
`define EOR_ABSX        9'h5D
`define EOR_ABSY        9'h59
`define EOR_RIND        9'h52
`define EOR_I           9'h52
`define EOR_DSP         9'h43
 
// LD is OR rt,r0,....
 
`define ST_ZPX          9'h95
`define ST_IX           9'h81
`define ST_IY           9'h91
`define ST_ABS          9'h8D
`define ST_ABSX         9'h9D
`define ST_RIND         9'h92
`define ST_DSP          9'h83
 
`define ORB_ZPX         9'hB5
`define ORB_IX          9'hA1
`define ORB_IY          9'hB1
`define ORB_ABS         9'hAD
`define ORB_ABSX        9'hBD
 
`define STB_ZPX         9'h74
`define STB_ABS         9'h9C
`define STB_ABSX        9'h9E
 
 
//`define LDB_RIND      9'hB2   // Conflict with LDX #imm16
 
`define LDA_IMM         9'hA9
`define LDA_ZP          9'hA5
`define LDA_ZPX         9'hB5
`define LDA_IX          9'hA1
`define LDA_IY          9'hB1
`define LDA_ABS         9'hAD
`define LDA_ABSX        9'hBD
`define LDA_ABSY        9'hB9
`define LDA_I           9'hB2
 
`define STA_ZP          9'h85
`define STA_ZPX         9'h95
`define STA_IX          9'h81
`define STA_IY          9'h91
`define STA_ABS         9'h8D
`define STA_ABSX        9'h9D
`define STA_ABSY        9'h99
`define STA_I           9'h92
 
`define ASL_IMM8        9'h24
`define ASL_ACC         9'h0A
`define ASL_ZP          9'h06
`define ASL_RR          9'h06
`define ASL_ZPX         9'h16
`define ASL_ABS         9'h0E
`define ASL_ABSX        9'h1E
 
`define ROL_ACC         9'h2A
`define ROL_ZP          9'h26
`define ROL_RR          9'h26
`define ROL_ZPX         9'h36
`define ROL_ABS         9'h2E
`define ROL_ABSX        9'h3E
 
`define LSR_IMM8        9'h34
`define LSR_ACC         9'h4A
`define LSR_ZP          9'h46
`define LSR_RR          9'h46
`define LSR_ZPX         9'h56
`define LSR_ABS         9'h4E
`define LSR_ABSX        9'h5E
 
`define ROR_RR          9'h66
`define ROR_ZP          9'h66
`define ROR_ZPX         9'h76
`define ROR_ABS         9'h6E
`define ROR_ABSX        9'h7E
 
`define DEC_RR          9'hC6
`define DEC_ZP          9'hC6
`define DEC_ZPX         9'hD6
`define DEC_ABS         9'hCE
`define DEC_ABSX        9'hDE
`define INC_RR          9'hE6
`define INC_ZP          9'hE6
`define INC_ZPX         9'hF6
`define INC_ABS         9'hEE
`define INC_ABSX        9'hFE
 
`define BIT_IMM         9'h89
`define BIT_ZP          9'h24
`define BIT_ZPX         9'h34
`define BIT_ABS         9'h2C
`define BIT_ABSX        9'h3C
 
// CMP = SUB r0,...
// BIT = AND r0,...
`define BPL                     9'h10
`define BVC                     9'h50
`define BCC                     9'h90
`define BNE                     9'hD0
`define BMI                     9'h30
`define BVS                     9'h70
`define BCS                     9'hB0
`define BEQ                     9'hF0
`define BRL                     9'h82
`define BRA                     9'h80
`define BHI                     9'h13
`define BLS                     9'h33
`define BGE                     9'h93
`define BLT                     9'hB3
`define BGT                     9'hD3
`define BLE                     9'hF3
 
`define JML                     9'h5C
`define JMP                     9'h4C
`define JMP_IND         9'h6C
`define JMP_INDX        9'h7C
`define JMP_RIND        9'hD2
`define JSR                     9'h20
`define JSL                     9'h22
`define JSR_IND         9'h2C
`define JSR_INDX        9'hFC
`define JSR_RIND        9'hC2
`define RTS                     9'h60
`define RTL                     9'h6B
`define BSR                     9'h62
`define NOP                     9'hEA
 
`define BRK                     9'h00
`define PLX                     9'hFA
`define PLY                     9'h7A
`define PHX                     9'hDA
`define PHY                     9'h5A
`define WAI                     9'hCB
`define PUSH            9'h0B
`define POP                     9'h2B
 
`define LDX_IMM         9'hA2
`define LDX_ZP          9'hA6
`define LDX_ZPX         9'hB6
`define LDX_ZPY         9'hB6
`define LDX_ABS         9'hAE
`define LDX_ABSY        9'hBE
 
`define LDX_IMM32       9'hA2
`define LDX_IMM16       9'hB2
`define LDX_IMM8        9'hA6
 
`define LDY_IMM         9'hA0
`define LDY_ZP          9'hA4
`define LDY_ZPX         9'hB4
`define LDY_IMM32       9'hA0
`define LDY_ABS         9'hAC
`define LDY_ABSX        9'hBC
 
`define STX_ZP          9'h86
`define STX_ZPX         9'h96
`define STX_ZPY         9'h96
`define STX_ABS         9'h8E
 
`define STY_ZP          9'h84
`define STY_ZPX         9'h94
`define STY_ABS         9'h8C
 
`define STZ_ZP          9'h64
`define STZ_ZPX         9'h74
`define STZ_ABS         9'h9C
`define STZ_ABSX        9'h9E
 
`define CPX_IMM         9'hE0
`define CPX_IMM32       9'hE0
`define CPX_ZP          9'hE4
`define CPX_ZPX         9'hE4
`define CPX_ABS         9'hEC
`define CPY_IMM         9'hC0
`define CPY_IMM32       9'hC0
`define CPY_ZP          9'hC4
`define CPY_ZPX         9'hC4
`define CPY_ABS         9'hCC
 
`define TRB_ZP          9'h14
`define TRB_ZPX         9'h14
`define TRB_ABS         9'h1C
`define TSB_ZP          9'h04
`define TSB_ZPX         9'h04
`define TSB_ABS         9'h0C
 
`define BAZ                     9'hC1
`define BXZ                     9'hD1
`define BEQ_RR          9'hE2
`define INT0            9'hDC
`define INT1            9'hDD
`define SUB_SP8         9'h85
`define SUB_SP16        9'h99
`define SUB_SP32        9'h89
`define MVP                     9'h44
`define MVN                     9'h54
`define STS                     9'h64
`define EXEC            9'hEB
`define ATNI            9'h4B
 
// Page Two Oproces
`define PG2                     9'h42
 
`define TOFF            9'h118
`define TON                     9'h138
`define MUL_IMM8        9'h105
`define MUL_IMM16       9'h119
`define MUL_IMM32       9'h109
`define DIV_IMM8        9'h145
`define DIV_IMM16       9'h159
`define DIV_IMM32       9'h149
`define MOD_IMM8        9'h185
`define MOD_IMM16       9'h199
`define MOD_IMM32       9'h189
`define PUSHA           9'h10B
`define POPA            9'h12B
`define BMS_ZPX         9'h106
`define BMS_ABS         9'h10E
`define BMS_ABSX        9'h11E
`define BMC_ZPX         9'h126
`define BMC_ABS         9'h12E
`define BMC_ABSX        9'h13E
`define BMF_ZPX         9'h146
`define BMF_ABS         9'h14E
`define BMF_ABSX        9'h15E
`define BMT_ZPX         9'h166
`define BMT_ABS         9'h16E
`define BMT_ABSX        9'h17E
`define HOFF            9'h158
`define CMPS            9'h144
 
`define NOTHING         5'd0
`define SR_70           5'd1
`define SR_310          5'd2
`define BYTE_70         5'd3
`define WORD_310        5'd4
`define PC_70           5'd5
`define PC_158          5'd6
`define PC_2316         5'd7
`define PC_3124         5'd8
`define PC_310          5'd9
`define WORD_311        5'd10
`define IA_310          5'd11
`define IA_70           5'd12
`define IA_158          5'd13
`define BYTE_71         5'd14
`define WORD_312        5'd15
`define WORD_313        5'd16
`define WORD_314        5'd17
 
`define STW_DEF         6'h0
`define STW_ACC         6'd1
`define STW_X           6'd2
`define STW_Y           6'd3
`define STW_PC          6'd4
`define STW_PC2         6'd5
`define STW_PCHWI       6'd6
`define STW_SR          6'd7
`define STW_RFA         6'd8
`define STW_RFA8        6'd9
`define STW_RFA         6'd10
`define STW_RFA8        6'd11
`define STW_A           6'd12
`define STW_B           6'd13
`define STW_CALC        6'd14
`define STW_OPC         6'd15
`define STW_ACC8        6'd16
`define STW_X8          6'd17
`define STW_Y8          6'd18
`define STW_PC3124      6'd19
`define STW_PC2316      6'd20
`define STW_PC158       6'd21
`define STW_PC70        6'd22
`define STW_SR70        6'd23
`define STW_Z8          6'd24

Line No.	Rev	Author	Line
1	30	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch<remove>@opencores.org`
7			`// \|\|`
8			`//`
9			`// rtf65002.v`
10			`// - 32 bit CPU`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`// ============================================================================`
26			`//`
27			`define TRUE 1'b1
28			`define FALSE 1'b0
29
30	32	robfinch	`define SUPPORT_ICACHE 1'b1
31			`define ICACHE_4K 1'b1
32			//`define ICACHE_16K 1'b1
33			//`define ICACHE_2WAY 1'b1
34			//`define SUPPORT_DCACHE 1'b1
35	30	robfinch	`define SUPPORT_BCD 1'b1
36			`define SUPPORT_DIVMOD 1'b1
37	32	robfinch	`define SUPPORT_EM8 1'b1
38			//`define SUPPORT_EXEC 1'b1
39	30	robfinch	`define SUPPORT_BERR 1'b1
40			`define SUPPORT_STRING 1'b1
41			`define SUPPORT_SHIFT 1'b1
42
43			`define RST_VECT 34'h3FFFFFFF8
44			`define NMI_VECT 34'h3FFFFFFF4
45			`define IRQ_VECT 34'h3FFFFFFF0
46			`define BRK_VECTNO 9'd0
47			`define SLP_VECTNO 9'd1
48			`define BYTE_RST_VECT 34'h00000FFFC
49			`define BYTE_NMI_VECT 34'h00000FFFA
50			`define BYTE_IRQ_VECT 34'h00000FFFE
51
52	32	robfinch	`define BRK 9'h00
53			`define RTI 9'h40
54			`define RTS 9'h60
55			`define PHP 9'h08
56			`define CLC 9'h18
57			`define PLP 9'h28
58			`define SEC 9'h38
59			`define PHA 9'h48
60			`define CLI 9'h58
61			`define PLA 9'h68
62			`define SEI 9'h78
63			`define DEY 9'h88
64			`define TYA 9'h98
65			`define TAY 9'hA8
66			`define CLV 9'hB8
67			`define INY 9'hC8
68			`define CLD 9'hD8
69			`define INX 9'hE8
70			`define SED 9'hF8
71			`define ROR_ACC 9'h6A
72			`define TXA 9'h8A
73			`define TXS 9'h9A
74			`define TAX 9'hAA
75			`define TSX 9'hBA
76			`define DEX 9'hCA
77			`define NOP 9'hEA
78			`define TXY 9'h9B
79			`define TYX 9'hBB
80			`define TAS 9'h1B
81			`define TSA 9'h3B
82			`define TRS 9'h8B
83			`define TSR 9'hAB
84			`define STP 9'hDB
85			`define NAT 9'hFB
86			`define EMM 9'hFB
87			`define INA 9'h1A
88			`define DEA 9'h3A
89	30	robfinch
90	32	robfinch	`define RR 9'h02
91	30	robfinch	`define ADD_RR 4'd0
92			`define SUB_RR 4'd1
93			`define CMP_RR 4'd2
94			`define AND_RR 4'd3
95			`define EOR_RR 4'd4
96			`define OR_RR 4'd5
97			`define MUL_RR 4'd8
98			`define MULS_RR 4'd9
99			`define DIV_RR 4'd10
100			`define DIVS_RR 4'd11
101			`define MOD_RR 4'd12
102			`define MODS_RR 4'd13
103			`define ASL_RRR 4'd14
104			`define LSR_RRR 4'd15
105	32	robfinch	`define LD_RR 9'h7B
106	30	robfinch
107	32	robfinch	`define ADD_IMM8 9'h65 // 8 bit operand
108			`define ADD_IMM16 9'h79 // 16 bit operand
109			`define ADD_IMM32 9'h69 // 32 bit operand
110			`define ADD_ZPX 9'h75 // there is no ZP mode, use R0 to syntheisze
111			`define ADD_IX 9'h61
112			`define ADD_IY 9'h71
113			`define ADD_ABS 9'h6D
114			`define ADD_ABSX 9'h7D
115			`define ADD_RIND 9'h72
116			`define ADD_DSP 9'h63
117	30	robfinch
118	32	robfinch	`define SUB_IMM8 9'hE5
119			`define SUB_IMM16 9'hF9
120			`define SUB_IMM32 9'hE9
121			`define SUB_ZPX 9'hF5
122			`define SUB_IX 9'hE1
123			`define SUB_IY 9'hF1
124			`define SUB_ABS 9'hED
125			`define SUB_ABSX 9'hFD
126			`define SUB_RIND 9'hF2
127			`define SUB_DSP 9'hE3
128	30	robfinch
129			`// CMP = SUB r0,....`
130
131	32	robfinch	`define ADC_IMM 9'h69
132			`define ADC_ZP 9'h65
133			`define ADC_ZPX 9'h75
134			`define ADC_IX 9'h61
135			`define ADC_IY 9'h71
136			`define ADC_ABS 9'h6D
137			`define ADC_ABSX 9'h7D
138			`define ADC_ABSY 9'h79
139			`define ADC_I 9'h72
140	30	robfinch
141	32	robfinch	`define SBC_IMM 9'hE9
142			`define SBC_ZP 9'hE5
143			`define SBC_ZPX 9'hF5
144			`define SBC_IX 9'hE1
145			`define SBC_IY 9'hF1
146			`define SBC_ABS 9'hED
147			`define SBC_ABSX 9'hFD
148			`define SBC_ABSY 9'hF9
149			`define SBC_I 9'hF2
150	30	robfinch
151	32	robfinch	`define CMP_IMM8 9'hC5
152			`define CMP_IMM32 9'hC9
153			`define CMP_IMM 9'hC9
154			`define CMP_ZP 9'hC5
155			`define CMP_ZPX 9'hD5
156			`define CMP_IX 9'hC1
157			`define CMP_IY 9'hD1
158			`define CMP_ABS 9'hCD
159			`define CMP_ABSX 9'hDD
160			`define CMP_ABSY 9'hD9
161			`define CMP_I 9'hD2
162	30	robfinch
163
164	32	robfinch	`define LDA_IMM8 9'hA5
165			`define LDA_IMM16 9'hB9
166			`define LDA_IMM32 9'hA9
167	30	robfinch
168	32	robfinch	`define AND_IMM8 9'h25
169			`define AND_IMM16 9'h39
170			`define AND_IMM32 9'h29
171			`define AND_IMM 9'h29
172			`define AND_ZP 9'h25
173			`define AND_ZPX 9'h35
174			`define AND_IX 9'h21
175			`define AND_IY 9'h31
176			`define AND_ABS 9'h2D
177			`define AND_ABSX 9'h3D
178			`define AND_ABSY 9'h39
179			`define AND_RIND 9'h32
180			`define AND_I 9'h32
181			`define AND_DSP 9'h23
182	30	robfinch
183	32	robfinch	`define OR_IMM8 9'h05
184			`define OR_IMM16 9'h19
185			`define OR_IMM32 9'h09
186			`define OR_ZPX 9'h15
187			`define OR_IX 9'h01
188			`define OR_IY 9'h11
189			`define OR_ABS 9'h0D
190			`define OR_ABSX 9'h1D
191			`define OR_RIND 9'h12
192			`define OR_DSP 9'h03
193	30	robfinch
194	32	robfinch	`define ORA_IMM 9'h09
195			`define ORA_ZP 9'h05
196			`define ORA_ZPX 9'h15
197			`define ORA_IX 9'h01
198			`define ORA_IY 9'h11
199			`define ORA_ABS 9'h0D
200			`define ORA_ABSX 9'h1D
201			`define ORA_ABSY 9'h19
202			`define ORA_I 9'h12
203	30	robfinch
204	32	robfinch	`define EOR_IMM 9'h49
205			`define EOR_IMM8 9'h45
206			`define EOR_IMM16 9'h59
207			`define EOR_IMM32 9'h49
208			`define EOR_ZP 9'h45
209			`define EOR_ZPX 9'h55
210			`define EOR_IX 9'h41
211			`define EOR_IY 9'h51
212			`define EOR_ABS 9'h4D
213			`define EOR_ABSX 9'h5D
214			`define EOR_ABSY 9'h59
215			`define EOR_RIND 9'h52
216			`define EOR_I 9'h52
217			`define EOR_DSP 9'h43
218	30	robfinch
219			`// LD is OR rt,r0,....`
220
221	32	robfinch	`define ST_ZPX 9'h95
222			`define ST_IX 9'h81
223			`define ST_IY 9'h91
224			`define ST_ABS 9'h8D
225			`define ST_ABSX 9'h9D
226			`define ST_RIND 9'h92
227			`define ST_DSP 9'h83
228	30	robfinch
229	32	robfinch	`define ORB_ZPX 9'hB5
230			`define ORB_IX 9'hA1
231			`define ORB_IY 9'hB1
232			`define ORB_ABS 9'hAD
233			`define ORB_ABSX 9'hBD
234	30	robfinch
235	32	robfinch	`define STB_ZPX 9'h74
236			`define STB_ABS 9'h9C
237			`define STB_ABSX 9'h9E
238	30	robfinch
239
240	32	robfinch	//`define LDB_RIND 9'hB2 // Conflict with LDX #imm16
241	30	robfinch
242	32	robfinch	`define LDA_IMM 9'hA9
243			`define LDA_ZP 9'hA5
244			`define LDA_ZPX 9'hB5
245			`define LDA_IX 9'hA1
246			`define LDA_IY 9'hB1
247			`define LDA_ABS 9'hAD
248			`define LDA_ABSX 9'hBD
249			`define LDA_ABSY 9'hB9
250			`define LDA_I 9'hB2
251	30	robfinch
252	32	robfinch	`define STA_ZP 9'h85
253			`define STA_ZPX 9'h95
254			`define STA_IX 9'h81
255			`define STA_IY 9'h91
256			`define STA_ABS 9'h8D
257			`define STA_ABSX 9'h9D
258			`define STA_ABSY 9'h99
259			`define STA_I 9'h92
260	30	robfinch
261	32	robfinch	`define ASL_IMM8 9'h24
262			`define ASL_ACC 9'h0A
263			`define ASL_ZP 9'h06
264			`define ASL_RR 9'h06
265			`define ASL_ZPX 9'h16
266			`define ASL_ABS 9'h0E
267			`define ASL_ABSX 9'h1E
268	30	robfinch
269	32	robfinch	`define ROL_ACC 9'h2A
270			`define ROL_ZP 9'h26
271			`define ROL_RR 9'h26
272			`define ROL_ZPX 9'h36
273			`define ROL_ABS 9'h2E
274			`define ROL_ABSX 9'h3E
275	30	robfinch
276	32	robfinch	`define LSR_IMM8 9'h34
277			`define LSR_ACC 9'h4A
278			`define LSR_ZP 9'h46
279			`define LSR_RR 9'h46
280			`define LSR_ZPX 9'h56
281			`define LSR_ABS 9'h4E
282			`define LSR_ABSX 9'h5E
283	30	robfinch
284	32	robfinch	`define ROR_RR 9'h66
285			`define ROR_ZP 9'h66
286			`define ROR_ZPX 9'h76
287			`define ROR_ABS 9'h6E
288			`define ROR_ABSX 9'h7E
289	30	robfinch
290	32	robfinch	`define DEC_RR 9'hC6
291			`define DEC_ZP 9'hC6
292			`define DEC_ZPX 9'hD6
293			`define DEC_ABS 9'hCE
294			`define DEC_ABSX 9'hDE
295			`define INC_RR 9'hE6
296			`define INC_ZP 9'hE6
297			`define INC_ZPX 9'hF6
298			`define INC_ABS 9'hEE
299			`define INC_ABSX 9'hFE
300	30	robfinch
301	32	robfinch	`define BIT_IMM 9'h89
302			`define BIT_ZP 9'h24
303			`define BIT_ZPX 9'h34
304			`define BIT_ABS 9'h2C
305			`define BIT_ABSX 9'h3C
306	30	robfinch
307			`// CMP = SUB r0,...`
308			`// BIT = AND r0,...`
309	32	robfinch	`define BPL 9'h10
310			`define BVC 9'h50
311			`define BCC 9'h90
312			`define BNE 9'hD0
313			`define BMI 9'h30
314			`define BVS 9'h70
315			`define BCS 9'hB0
316			`define BEQ 9'hF0
317			`define BRL 9'h82
318			`define BRA 9'h80
319			`define BHI 9'h13
320			`define BLS 9'h33
321			`define BGE 9'h93
322			`define BLT 9'hB3
323			`define BGT 9'hD3
324			`define BLE 9'hF3
325	30	robfinch
326	32	robfinch	`define JML 9'h5C
327			`define JMP 9'h4C
328			`define JMP_IND 9'h6C
329			`define JMP_INDX 9'h7C
330			`define JMP_RIND 9'hD2
331			`define JSR 9'h20
332			`define JSL 9'h22
333			`define JSR_IND 9'h2C
334			`define JSR_INDX 9'hFC
335			`define JSR_RIND 9'hC2
336			`define RTS 9'h60
337			`define RTL 9'h6B
338			`define BSR 9'h62
339			`define NOP 9'hEA
340	30	robfinch
341	32	robfinch	`define BRK 9'h00
342			`define PLX 9'hFA
343			`define PLY 9'h7A
344			`define PHX 9'hDA
345			`define PHY 9'h5A
346			`define WAI 9'hCB
347			`define PUSH 9'h0B
348			`define POP 9'h2B
349	30	robfinch
350	32	robfinch	`define LDX_IMM 9'hA2
351			`define LDX_ZP 9'hA6
352			`define LDX_ZPX 9'hB6
353			`define LDX_ZPY 9'hB6
354			`define LDX_ABS 9'hAE
355			`define LDX_ABSY 9'hBE
356	30	robfinch
357	32	robfinch	`define LDX_IMM32 9'hA2
358			`define LDX_IMM16 9'hB2
359			`define LDX_IMM8 9'hA6
360	30	robfinch
361	32	robfinch	`define LDY_IMM 9'hA0
362			`define LDY_ZP 9'hA4
363			`define LDY_ZPX 9'hB4
364			`define LDY_IMM32 9'hA0
365			`define LDY_ABS 9'hAC
366			`define LDY_ABSX 9'hBC
367	30	robfinch
368	32	robfinch	`define STX_ZP 9'h86
369			`define STX_ZPX 9'h96
370			`define STX_ZPY 9'h96
371			`define STX_ABS 9'h8E
372	30	robfinch
373	32	robfinch	`define STY_ZP 9'h84
374			`define STY_ZPX 9'h94
375			`define STY_ABS 9'h8C
376	30	robfinch
377	32	robfinch	`define STZ_ZP 9'h64
378			`define STZ_ZPX 9'h74
379			`define STZ_ABS 9'h9C
380			`define STZ_ABSX 9'h9E
381	30	robfinch
382	32	robfinch	`define CPX_IMM 9'hE0
383			`define CPX_IMM32 9'hE0
384			`define CPX_ZP 9'hE4
385			`define CPX_ZPX 9'hE4
386			`define CPX_ABS 9'hEC
387			`define CPY_IMM 9'hC0
388			`define CPY_IMM32 9'hC0
389			`define CPY_ZP 9'hC4
390			`define CPY_ZPX 9'hC4
391			`define CPY_ABS 9'hCC
392	30	robfinch
393	32	robfinch	`define TRB_ZP 9'h14
394			`define TRB_ZPX 9'h14
395			`define TRB_ABS 9'h1C
396			`define TSB_ZP 9'h04
397			`define TSB_ZPX 9'h04
398			`define TSB_ABS 9'h0C
399	30	robfinch
400	32	robfinch	`define BAZ 9'hC1
401			`define BXZ 9'hD1
402			`define BEQ_RR 9'hE2
403			`define INT0 9'hDC
404			`define INT1 9'hDD
405			`define SUB_SP8 9'h85
406			`define SUB_SP16 9'h99
407			`define SUB_SP32 9'h89
408			`define MVP 9'h44
409			`define MVN 9'h54
410			`define STS 9'h64
411			`define EXEC 9'hEB
412			`define ATNI 9'h4B
413	30	robfinch
414	32	robfinch	`// Page Two Oproces`
415			`define PG2 9'h42
416	30	robfinch
417	32	robfinch	`define TOFF 9'h118
418			`define TON 9'h138
419			`define MUL_IMM8 9'h105
420			`define MUL_IMM16 9'h119
421			`define MUL_IMM32 9'h109
422			`define DIV_IMM8 9'h145
423			`define DIV_IMM16 9'h159
424			`define DIV_IMM32 9'h149
425			`define MOD_IMM8 9'h185
426			`define MOD_IMM16 9'h199
427			`define MOD_IMM32 9'h189
428			`define PUSHA 9'h10B
429			`define POPA 9'h12B
430			`define BMS_ZPX 9'h106
431			`define BMS_ABS 9'h10E
432			`define BMS_ABSX 9'h11E
433			`define BMC_ZPX 9'h126
434			`define BMC_ABS 9'h12E
435			`define BMC_ABSX 9'h13E
436			`define BMF_ZPX 9'h146
437			`define BMF_ABS 9'h14E
438			`define BMF_ABSX 9'h15E
439			`define BMT_ZPX 9'h166
440			`define BMT_ABS 9'h16E
441			`define BMT_ABSX 9'h17E
442			`define HOFF 9'h158
443			`define CMPS 9'h144
444	30	robfinch
445	32	robfinch	`define NOTHING 5'd0
446			`define SR_70 5'd1
447			`define SR_310 5'd2
448			`define BYTE_70 5'd3
449			`define WORD_310 5'd4
450			`define PC_70 5'd5
451			`define PC_158 5'd6
452			`define PC_2316 5'd7
453			`define PC_3124 5'd8
454			`define PC_310 5'd9
455			`define WORD_311 5'd10
456			`define IA_310 5'd11
457			`define IA_70 5'd12
458			`define IA_158 5'd13
459			`define BYTE_71 5'd14
460			`define WORD_312 5'd15
461			`define WORD_313 5'd16
462			`define WORD_314 5'd17
463
464	30	robfinch	`define STW_DEF 6'h0
465			`define STW_ACC 6'd1
466			`define STW_X 6'd2
467			`define STW_Y 6'd3
468			`define STW_PC 6'd4
469			`define STW_PC2 6'd5
470			`define STW_PCHWI 6'd6
471			`define STW_SR 6'd7
472			`define STW_RFA 6'd8
473			`define STW_RFA8 6'd9
474			`define STW_RFA 6'd10
475			`define STW_RFA8 6'd11
476			`define STW_A 6'd12
477			`define STW_B 6'd13
478			`define STW_CALC 6'd14
479	32	robfinch	`define STW_OPC 6'd15
480	30	robfinch	`define STW_ACC8 6'd16
481			`define STW_X8 6'd17
482			`define STW_Y8 6'd18
483			`define STW_PC3124 6'd19
484			`define STW_PC2316 6'd20
485			`define STW_PC158 6'd21
486			`define STW_PC70 6'd22
487			`define STW_SR70 6'd23
488	32	robfinch	`define STW_Z8 6'd24

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