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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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`include "rtf65002_defines.v"
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// This table being setup to set the pc increment. It should synthesize to a ROM.
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module rtf65002_pcinc(opcode,suppress_pcinc,inc);
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input [7:0] opcode;
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input [3:0] suppress_pcinc;
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output reg [3:0] inc;
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always @(opcode)
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if (suppress_pcinc==4'hF)
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case(opcode)
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`BRK: inc <= 4'd0;
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`INT0,`INT1: inc <= 4'd0;
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`BPL,`BMI,`BCS,`BCC,`BVS,`BVC,`BEQ,`BNE,`BRA,`BGT,`BLE,`BGE,`BLT,`BHI,`BLS: inc <= 4'd2;
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`BRL: inc <= 4'd3;
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`EXEC,`ATNI: inc <= 4'd2;
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`CLC,`SEC,`CLD,`SED,`CLV,`CLI,`SEI: inc <= 4'd1;
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`TAS,`TSA,`TAY,`TYA,`TAX,`TXA,`TSX,`TXS,`TYX,`TXY: inc <= 4'd1;
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`TRS,`TSR: inc <= 4'd2;
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`INY,`DEY,`INX,`DEX,`INA,`DEA: inc <= 4'd1;
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`EMM: inc <= 4'd1;
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`PHA,`PHX,`PHY,`PHP: inc <= 4'd1;
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`PLA,`PLX,`PLY,`PLP: inc <= 4'd1;
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`PUSH,`POP: inc <= 4'd2;
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`STP,`WAI: inc <= 4'd1;
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`JMP,`JML,`JMP_IND,`JMP_INDX,`JMP_RIND,
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`JSR,`JSR_RIND,`JSL,`BSR,`JSR_INDX,`RTS,`RTL,`RTI: inc <= 4'd0;
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`JML,`JSL,`JMP_IND,`JMP_INDX,`JSR_INDX: inc <= 4'd5;
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`JMP_RIND,`JSR_RIND: inc <= 4'd2;
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`NOP: inc <= 4'd1;
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`BSR: inc <= 4'd3;
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`RR: inc <= 4'd3;
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`LD_RR: inc <= 4'd2;
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`ADD_IMM8,`SUB_IMM8,`AND_IMM8,`OR_IMM8,`EOR_IMM8,`ASL_IMM8,`LSR_IMM8: inc <= 4'd3;
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`LDX_IMM8,`LDA_IMM8,`CMP_IMM8,`SUB_SP8: inc <= 4'd2;
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`ADD_IMM16,`SUB_IMM16,`AND_IMM16,`OR_IMM16,`EOR_IMM16: inc <= 4'd4;
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`LDX_IMM16,`LDA_IMM16,`SUB_SP16: inc <= 4'd3;
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`ADD_IMM32,`SUB_IMM32,`AND_IMM32,`OR_IMM32,`EOR_IMM32: inc <= 4'd6;
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`LDX_IMM32,`LDY_IMM32,`LDA_IMM32,`SUB_SP32,`CPX_IMM32,`CPY_IMM32: inc <= 4'd5;
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`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`OR_ZPX,`EOR_ZPX: inc <= 4'd4;
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`ADD_IX,`SUB_IX,`AND_IX,`OR_IX,`EOR_IX: inc <= 4'd4;
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`ADD_IY,`SUB_IY,`AND_IY,`OR_IY,`EOR_IY: inc <= 4'd4;
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`ADD_ABS,`SUB_ABS,`AND_ABS,`OR_ABS,`EOR_ABS: inc <= 4'd6;
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`ADD_ABSX,`SUB_ABSX,`AND_ABSX,`OR_ABSX,`EOR_ABSX: inc <= 4'd7;
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`ADD_RIND,`SUB_RIND,`AND_RIND,`OR_RIND,`EOR_RIND: inc <= 4'd3;
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`ADD_DSP,`SUB_DSP,`AND_DSP,`OR_DSP,`EOR_DSP: inc <= 4'd3;
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`ASL_ACC,`LSR_ACC,`ROR_ACC,`ROL_ACC: inc <= 4'd1;
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`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,`INC_RR,`DEC_RR: inc <= 4'd2;
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`ST_RIND: inc <= 4'd2;
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`LDX_ZPX,`LDY_ZPX,`ST_DSP,`STX_ZPX,`STY_ZPX,`CPX_ZPX,`CPY_ZPX,
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`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX,
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`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP,
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`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND: inc <= 4'd3;
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`ORB_ZPX,`ST_ZPX,`STB_ZPX,`ADD_ZPX,`SUB_ZPX,`OR_ZPX,`AND_ZPX,`EOR_ZPX,
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`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,
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`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY: inc <= 4'd4;
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`LDX_ABS,`LDY_ABS,`STX_ABS,`STY_ABS,
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`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`CPX_ABS,`CPY_ABS: inc <= 4'd5;
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`ORB_ABS,`LDX_ABSY,`LDY_ABSX,`ST_ABS,`STB_ABS,
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`ADD_ABS,`SUB_ABS,`OR_ABS,`AND_ABS,`EOR_ABS,
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`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX: inc <= 4'd6;
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`ORB_ABSX,`ST_ABSX,`STB_ABSX,
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`ADD_ABSX,`SUB_ABSX,`OR_ABSX,`AND_ABSX,`EOR_ABSX: inc <= 4'd7;
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`PHP,`PHA,`PHX,`PHY,`PLP,`PLA,`PLX,`PLY: inc <= 4'd1;
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`PUSH,`POP: inc <= 4'd2;
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`MVN,`MVP,`STS: inc <= 4'd1;
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default: inc <= 4'd0; // unimplemented instruction
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endcase
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else
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inc <= 4'd0;
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endmodule
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