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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// rtf65002.v
//  - 32 bit CPU
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
`include "rtf65002_defines.v"
 
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);
parameter IDLE = 3'd0;
parameter LOAD_DCACHE = 3'd1;
parameter LOAD_ICACHE = 3'd2;
parameter LOAD_IBUF1 = 3'd3;
parameter LOAD_IBUF2 = 3'd4;
parameter LOAD_IBUF3 = 3'd5;
parameter RESET1 = 6'd0;
parameter IFETCH = 6'd1;
parameter DECODE = 6'd2;
parameter STORE1 = 6'd3;
parameter STORE2 = 6'd4;
parameter IRQ0 = 6'd5;
parameter IRQ1 = 6'd6;
parameter IRQ2 = 6'd7;
parameter IRQ3 = 6'd8;
parameter CALC = 6'd9;
parameter JSR_INDX1 = 6'd10;
parameter JSR161 = 6'd11;
parameter RTS1 = 6'd12;
parameter IY3 = 6'd13;
parameter BSR1 = 6'd14;
parameter BYTE_IX5 = 6'd15;
parameter BYTE_IY5 = 6'd16;
parameter BYTE_JSR1 = 6'd17;
parameter BYTE_JSR2 = 6'd18;
parameter BYTE_JSR3 = 6'd19;
parameter BYTE_IRQ1 = 6'd20;
parameter BYTE_IRQ2 = 6'd21;
parameter BYTE_IRQ3 = 6'd22;
parameter BYTE_IRQ4 = 6'd23;
parameter BYTE_IRQ5 = 6'd24;
parameter BYTE_IRQ6 = 6'd25;
parameter BYTE_IRQ7 = 6'd26;
parameter BYTE_IRQ8 = 6'd27;
parameter BYTE_IRQ9 = 6'd28;
parameter BYTE_JSR_INDX1 = 6'd29;
parameter BYTE_JSR_INDX2 = 6'd30;
parameter BYTE_JSR_INDX3 = 6'd31;
parameter BYTE_JSL1 = 6'd32;
parameter BYTE_JSL2 = 6'd33;
parameter BYTE_JSL3 = 6'd34;
parameter BYTE_JSL4 = 6'd35;
parameter BYTE_JSL5 = 6'd36;
parameter BYTE_JSL6 = 6'd37;
parameter BYTE_JSL7 = 6'd38;
parameter BYTE_PLP1 = 6'd39;
parameter BYTE_PLP2 = 6'd40;
parameter BYTE_PLA1 = 6'd41;
parameter BYTE_PLA2 = 6'd42;
parameter WAIT_DHIT = 6'd43;
parameter RESET2 = 6'd44;
parameter MULDIV1 = 6'd45;
parameter MULDIV2 = 6'd46;
parameter BYTE_DECODE = 6'd47;
parameter BYTE_CALC = 6'd48;
parameter BUS_ERROR = 6'd49;
parameter INSN_BUS_ERROR = 6'd50;
parameter LOAD_MAC1 = 6'd51;
parameter LOAD_MAC2 = 6'd52;
parameter MVN1 = 6'd53;
parameter MVN2 = 6'd54;
parameter MVN3 = 6'd55;
parameter MVP1 = 6'd56;
parameter MVP2 = 6'd57;
parameter STS1 = 6'd58;
 
input rst_md;           // reset mode, 1=emulation mode, 0=native mode
input rst_i;
input clk_i;
input nmi_i;
input irq_i;
input [8:0] irq_vect;
output reg [1:0] bte_o;
output reg [2:0] cti_o;
output reg [5:0] bl_o;
output reg lock_o;
output reg cyc_o;
output reg stb_o;
input ack_i;
input err_i;
output reg we_o;
output reg [3:0] sel_o;
output reg [33:0] adr_o;
input [31:0] dat_i;
output reg [31:0] dat_o;
 
reg [5:0] state;
reg [5:0] retstate;
reg [2:0] cstate;
wire [63:0] insn;
reg [63:0] ibuf;
reg [31:0] bufadr;
reg [63:0] exbuf;
 
reg cf,nf,zf,vf,bf,im,df,em;
reg em1;
reg gie;
reg hwi;        // hardware interrupt indicator
reg nmoi;       // native mode on interrupt
wire [31:0] sr = {nf,vf,em,24'b0,bf,df,im,zf,cf};
wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
reg nmi1,nmi_edge;
reg wai;
reg [31:0] acc;
reg [31:0] x;
reg [31:0] y;
reg [7:0] sp;
reg [31:0] spage;        // stack page
wire [7:0] acc8 = acc[7:0];
wire [7:0] x8 = x[7:0];
wire [7:0] y8 = y[7:0];
reg [31:0] isp;          // interrupt stack pointer
wire [63:0] prod;
wire [31:0] q,r;
reg [31:0] tick;
wire [7:0] sp_dec = sp - 8'd1;
wire [7:0] sp_inc = sp + 8'd1;
wire [31:0] isp_dec = isp - 32'd1;
wire [31:0] isp_inc = isp + 32'd1;
reg [3:0] suppress_pcinc;
reg [31:0] pc;
reg [31:0] opc;
wire [3:0] pc_inc;
wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc);        // for branches
wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc);        // for branches
wire [31:0] pcp8 = pc + 32'd8;                                           // cache controller needs this
reg [31:0] abs8; // 8 bit mode absolute address register
reg [31:0] vbr;          // vector table base register
wire bhit=pc==bufadr;
reg [31:0] regfile [15:0];
reg [63:0] ir;
wire [3:0] Ra = ir[11:8];
wire [3:0] Rb = ir[15:12];
reg [31:0] rfoa;
reg [31:0] rfob;
always @(Ra or x or y or acc)
case(Ra)
4'h0:   rfoa <= 32'd0;
4'h1:   rfoa <= acc;
4'h2:   rfoa <= x;
4'h3:   rfoa <= y;
default:        rfoa <= regfile[Ra];
endcase
always @(Rb or x or y or acc)
case(Rb)
4'h0:   rfob <= 32'd0;
4'h1:   rfob <= acc;
4'h2:   rfob <= x;
4'h3:   rfob <= y;
default:        rfob <= regfile[Rb];
endcase
reg [3:0] Rt;
reg [33:0] ea;
reg first_ifetch;
reg [31:0] lfsr;
wire lfsr_fb;
xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);
reg [31:0] a, b;
`ifdef SUPPORT_SHIFT
wire [31:0] shlo = a << b[4:0];
wire [31:0] shro = a >> b[4:0];
`else
wire [31:0] shlo = 32'd0;
wire [31:0] shro = 32'd0;
`endif
reg [7:0] b8;
reg [32:0] res;
reg [8:0] res8;
wire resv8,resv32;
wire resc8 = res8[8];
wire resc32 = res[32];
wire resz8 = res8[7:0]==8'h00;
wire resz32 = res[31:0]==32'd0;
wire resn8 = res8[7];
wire resn32 = res[31];
 
reg [31:0] vect;
reg [31:0] ia;                   // temporary reg to hold indirect address
wire [31:0] iapy8 = abs8 + ia + y[7:0];
reg isInsnCacheLoad;
reg isDataCacheLoad;
reg isCacheReset;
wire hit0,hit1;
`ifdef SUPPORT_DCACHE
wire dhit;
`else
wire dhit = 1'b0;
`endif
reg write_allocate;
reg wr;
reg [3:0] wrsel;
reg [31:0] radr;
reg [1:0] radr2LSB;
wire [33:0] radr34 = {radr,radr2LSB};
wire [33:0] radr34p1 = radr34 + 34'd1;
reg [31:0] wadr;
reg [1:0] wadr2LSB;
reg [31:0] wdat;
wire [31:0] rdat;
reg [3:0] load_what;
reg [3:0] store_what;
reg [31:0] derr_address;
reg imiss;
reg dmiss;
reg icacheOn,dcacheOn;
`ifdef SUPPORT_DCACHE
wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn;  // I/O area is uncached
`else
wire unCachedData = 1'b1;
`endif
`ifdef SUPPORT_ICACHE
wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn;              // The lowest 8kB is uncached.
`else
wire unCachedInsn = 1'b1;
`endif
 
reg [31:0] history_buf [63:0];
reg [5:0] history_ndx;
reg hist_capture;
 
reg isBrk,isMove,isSts;
reg isRTI,isRTL,isRTS;
reg isOrb,isStb;
reg isRMW;
reg isSub,isSub8;
 
 
wire isCmp = ir[7:0]==`CPX_ZPX || ir[7:0]==`CPX_ABS || ir[7:0]==`CPX_IMM32 ||
                         ir[7:0]==`CPY_ZPX || ir[7:0]==`CPY_ABS || ir[7:0]==`CPY_IMM32;
wire isRMW32 =
                         ir[7:0]==`ASL_ZPX || ir[7:0]==`ROL_ZPX || ir[7:0]==`LSR_ZPX || ir[7:0]==`ROR_ZPX || ir[7:0]==`INC_ZPX || ir[7:0]==`DEC_ZPX ||
                         ir[7:0]==`ASL_ABS || ir[7:0]==`ROL_ABS || ir[7:0]==`LSR_ABS || ir[7:0]==`ROR_ABS || ir[7:0]==`INC_ABS || ir[7:0]==`DEC_ABS ||
                         ir[7:0]==`ASL_ABSX || ir[7:0]==`ROL_ABSX || ir[7:0]==`LSR_ABSX || ir[7:0]==`ROR_ABSX || ir[7:0]==`INC_ABSX || ir[7:0]==`DEC_ABSX ||
                         ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
                         ;
wire isRMW8 =
                         ir[7:0]==`ASL_ZP || ir[7:0]==`ROL_ZP || ir[7:0]==`LSR_ZP || ir[7:0]==`ROR_ZP || ir[7:0]==`INC_ZP || ir[7:0]==`DEC_ZP ||
                         ir[7:0]==`ASL_ZPX || ir[7:0]==`ROL_ZPX || ir[7:0]==`LSR_ZPX || ir[7:0]==`ROR_ZPX || ir[7:0]==`INC_ZPX || ir[7:0]==`DEC_ZPX ||
                         ir[7:0]==`ASL_ABS || ir[7:0]==`ROL_ABS || ir[7:0]==`LSR_ABS || ir[7:0]==`ROR_ABS || ir[7:0]==`INC_ABS || ir[7:0]==`DEC_ABS ||
                         ir[7:0]==`ASL_ABSX || ir[7:0]==`ROL_ABSX || ir[7:0]==`LSR_ABSX || ir[7:0]==`ROR_ABSX || ir[7:0]==`INC_ABSX || ir[7:0]==`DEC_ABSX ||
                         ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
                         ;
 
// Registerable decodes
// The following decodes can be registered because they aren't needed until at least the cycle after
// the DECODE stage.
 
always @(posedge clk)
        if (state==DECODE) begin
                isSub <= ir[7:0]==`SUB_ZPX || ir[7:0]==`SUB_IX || ir[7:0]==`SUB_IY ||
                         ir[7:0]==`SUB_ABS || ir[7:0]==`SUB_ABSX || ir[7:0]==`SUB_IMM8 || ir[7:0]==`SUB_IMM16 || ir[7:0]==`SUB_IMM32;
                isSub8 <= ir[7:0]==`SBC_ZP || ir[7:0]==`SBC_ZPX || ir[7:0]==`SBC_IX || ir[7:0]==`SBC_IY || ir[7:0]==`SBC_I ||
                         ir[7:0]==`SBC_ABS || ir[7:0]==`SBC_ABSX || ir[7:0]==`SBC_ABSY || ir[7:0]==`SBC_IMM;
                isRMW <= em ? isRMW8 : isRMW32;
                isOrb <= ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
                isStb <= ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
                isRTI <= ir[7:0]==`RTI;
                isRTL <= ir[7:0]==`RTL;
                isRTS <= ir[7:0]==`RTS;
                isBrk <= ir[7:0]==`BRK;
                isMove <= ir[7:0]==`MVP || ir[7:0]==`MVN;
                isSts <= ir[7:0]==`STS;
        end
 
`ifdef SUPPORT_EXEC
wire isExec = ir[7:0]==`EXEC;
wire isAtni = ir[7:0]==`ATNI;
`else
wire isExec = 1'b0;
wire isAtni = 1'b0;
`endif
wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
wire md_done;
wire clk;
reg isIY;
 
rtf65002_pcinc upci1
(
        .opcode(ir[7:0]),
        .suppress_pcinc(suppress_pcinc),
        .inc(pc_inc)
);
 
mult_div umd1
(
        .rst(rst_i),
        .clk(clk),
        .ld(ld_muldiv),
        .op(ir[23:20]),
        .a(rfoa),
        .b(rfob),
        .p(prod),
        .q(q),
        .r(r),
        .done(md_done)
);
 
`ifdef SUPPORT_ICACHE
rtf65002_icachemem icm0 (
        .wclk(clk),
        .wr(ack_i & isInsnCacheLoad),
        .adr(adr_o),
        .dat(dat_i),
        .rclk(~clk),
        .pc(pc),
        .insn(insn)
);
 
rtf65002_itagmem tgm0 (
        .wclk(clk),
        .wr((ack_i & isInsnCacheLoad)|isCacheReset),
        .adr({adr_o[31:1],!isCacheReset}),
        .rclk(~clk),
        .pc(pc),
        .hit0(hit0),
        .hit1(hit1)
);
 
wire ihit = (hit0 & hit1);//(pc[2:0] > 3'd1 ? hit1 : 1'b1));
`else
wire ihit = 1'b0;
`endif
 
`ifdef SUPPORT_DCACHE
rtf65002_dcachemem dcm0 (
        .wclk(clk),
        .wr(wr | (ack_i & isDataCacheLoad)),
        .sel(wr ? wrsel : sel_o),
        .wadr(wr ? wadr : adr_o[33:2]),
        .wdat(wr ? wdat : dat_i),
        .rclk(~clk),
        .radr(radr),
        .rdat(rdat)
);
 
rtf65002_dtagmem dtm0 (
        .wclk(clk),
        .wr(wr | (ack_i & isDataCacheLoad)),
        .wadr(wr ? wadr : adr_o[33:2]),
        .rclk(~clk),
        .radr(radr),
        .hit(dhit)
);
`endif
 
overflow uovr1 (
        .op(isSub),
        .a(a[31]),
        .b(b[31]),
        .s(res[31]),
        .v(resv32)
);
 
overflow uovr2 (
        .op(isSub8),
        .a(acc8[7]),
        .b(b8[7]),
        .s(res8[7]),
        .v(resv8)
);
 
wire [7:0] bcaio;
wire [7:0] bcao;
wire [7:0] bcsio;
wire [7:0] bcso;
wire bcaico,bcaco,bcsico,bcsco;
 
`ifdef SUPPORT_BCD
BCDAdd ubcdai1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcaio),.c(bcaico));
BCDAdd ubcda2 (.ci(cf),.a(acc8),.b(b8),.o(bcao),.c(bcaco));
BCDSub ubcdsi1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcsio),.c(bcsico));
BCDSub ubcds2 (.ci(cf),.a(acc8),.b(b8),.o(bcso),.c(bcsco));
`endif
 
reg [7:0] dati;
always @(radr2LSB or dat_i)
case(radr2LSB)
2'd0:   dati <= dat_i[7:0];
2'd1:   dati <= dat_i[15:8];
2'd2:   dati <= dat_i[23:16];
2'd3:   dati <= dat_i[31:24];
endcase
reg [7:0] rdat8;
always @(radr2LSB or rdat)
case(radr2LSB)
2'd0:   rdat8 <= rdat[7:0];
2'd1:   rdat8 <= rdat[15:8];
2'd2:   rdat8 <= rdat[23:16];
2'd3:   rdat8 <= rdat[31:24];
endcase
 
reg takb;
always @(ir or cf or vf or nf or zf)
case(ir[7:0])
`BEQ:   takb <= zf;
`BNE:   takb <= !zf;
`BPL:   takb <= !nf;
`BMI:   takb <= nf;
`BCS:   takb <= cf;
`BCC:   takb <= !cf;
`BVS:   takb <= vf;
`BVC:   takb <= !vf;
`BRA:   takb <= 1'b1;
`BRL:   takb <= 1'b1;
`BHI:   takb <= cf & !zf;
`BLS:   takb <= !cf | zf;
`BGE:   takb <= (nf & vf)|(!nf & !vf);
`BLT:   takb <= (nf & !vf)|(!nf & vf);
`BGT:   takb <= (nf & vf & !zf) + (!nf & !vf & !zf);
`BLE:   takb <= zf | (nf & !vf)|(!nf & vf);
//`BAZ: takb <= acc8==8'h00;
//`BXZ: takb <= x8==8'h00;
default:        takb <= 1'b0;
endcase
 
wire [31:0] zp_address           = {abs8[31:12],4'h0,ir[15:8]};
wire [31:0] zpx_address  = {abs8[31:12],4'h0,ir[15:8]} + x8;
wire [31:0] zpy_address          = {abs8[31:12],4'h0,ir[15:8]} + y8;
wire [31:0] abs_address  = {abs8[31:12],12'h00} + {16'h0,ir[23:8]};
wire [31:0] absx_address         = {abs8[31:12],12'h00} + {16'h0,ir[23:8] + {8'h0,x8}};  // simulates 64k bank wrap-around
wire [31:0] absy_address         = {abs8[31:12],12'h00} + {16'h0,ir[23:8] + {8'h0,y8}};
wire [31:0] zpx32xy_address      = ir[23:12] + rfoa;
wire [31:0] absx32xy_address     = ir[47:16] + rfob;
wire [31:0] zpx32_address                = ir[31:20] + rfob;
wire [31:0] absx32_address               = ir[55:24] + rfob;
 
reg [32:0] calc_res;
always @(a or b or b8 or x or y or df or cf or Rt or shlo or shro)
begin
        case(ir[7:0])
        `RR:
                case(ir[23:20])
                `ASL_RRR:       calc_res <= shlo;
                `LSR_RRR:       calc_res <= shro;
                default:        calc_res <= 33'd0;
                endcase
        `ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:  calc_res <= a + b + {31'b0,df&cf};
        `SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:  calc_res <= a - b - {31'b0,df&~cf&|Rt}; // Also CMP
        `AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:  calc_res <= a & b;      // Also BIT
        `OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND:                calc_res <= a | b;      // Also LD
        `EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:  calc_res <= a ^ b;
        `LDX_ZPY,`LDX_ABS,`LDX_ABSY:    calc_res <= b;
        `LDY_ZPX,`LDY_ABS,`LDY_ABSX:    calc_res <= b;
        `CPX_ZPX,`CPX_ABS:      calc_res <= x - b;
        `CPY_ZPX,`CPY_ABS:      calc_res <= y - b;
        `ASL_IMM8:      calc_res <= shlo;
        `LSR_IMM8:      calc_res <= shro;
        `ASL_ZPX,`ASL_ABS,`ASL_ABSX:    calc_res <= {b,1'b0};
        `ROL_ZPX,`ROL_ABS,`ROL_ABSX:    calc_res <= {b,cf};
        `LSR_ZPX,`LSR_ABS,`LSR_ABSX:    calc_res <= {b[0],1'b0,b[31:1]};
        `ROR_ZPX,`ROR_ABS,`ROR_ABSX:    calc_res <= {b[0],cf,b[31:1]};
        `INC_ZPX,`INC_ABS,`INC_ABSX:    calc_res <= b + 32'd1;
        `DEC_ZPX,`DEC_ABS,`DEC_ABSX:    calc_res <= b - 32'd1;
        `ORB_ZPX,`ORB_ABS,`ORB_ABSX:    calc_res <= a | {24'h0,b8};
        default:        calc_res <= 33'd0;
        endcase
end
 
 
//-----------------------------------------------------------------------------
// Clock control
// - reset or NMI reenables the clock
// - this circuit must be under the clk_i domain
//-----------------------------------------------------------------------------
//
reg cpu_clk_en;
reg clk_en;
BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );
 
always @(posedge clk_i)
if (rst_i) begin
        cpu_clk_en <= 1'b1;
        nmi1 <= 1'b0;
end
else begin
        nmi1 <= nmi_i;
        if (nmi_i)
                cpu_clk_en <= 1'b1;
        else
                cpu_clk_en <= clk_en;
end
 
always @(posedge clk)
if (rst_i) begin
        bte_o <= 2'b00;
        cti_o <= 3'b000;
        bl_o <= 6'd0;
        cyc_o <= 1'b0;
        stb_o <= 1'b0;
        we_o <= 1'b0;
        sel_o <= 4'h0;
        adr_o <= 34'd0;
        dat_o <= 32'd0;
        nmi_edge <= 1'b0;
        wai <= 1'b0;
        first_ifetch <= `TRUE;
        wr <= 1'b0;
        cf <= 1'b0;
        ir <= 64'hEAEAEAEAEAEAEAEA;
        imiss <= `FALSE;
        dmiss <= `FALSE;
        dcacheOn <= 1'b0;
        icacheOn <= 1'b1;
        write_allocate <= 1'b0;
        nmoi <= 1'b1;
        state <= RESET1;
        cstate <= IDLE;
        if (rst_md) begin
                pc <= 32'h0000FFF0;             // set high-order pc to zero
                vect <= `BYTE_RST_VECT;
                em <= 1'b1;
        end
        else begin
                vect <= `RST_VECT;
                em <= 1'b0;
                pc <= 32'hFFFFFFF0;
        end
        suppress_pcinc <= 4'hF;
        exbuf <= 64'd0;
        spage <= 32'h00000100;
        bufadr <= 32'd0;
        abs8 <= 32'd0;
        clk_en <= 1'b1;
        isCacheReset <= `TRUE;
        gie <= 1'b0;
        tick <= 32'd0;
        isIY <= 1'b0;
        load_what <= `NOTHING;
        hist_capture <= `TRUE;
        history_ndx <= 6'd0;
end
else begin
tick <= tick + 32'd1;
wr <= 1'b0;
if (nmi_i & !nmi1)
        nmi_edge <= 1'b1;
if (nmi_i|nmi1)
        clk_en <= 1'b1;
case(state)
RESET1:
        begin
                adr_o <= adr_o + 32'd4;
                if (adr_o[13:4]==10'h3FF) begin
                        state <= RESET2;
                        isCacheReset <= `FALSE;
                end
        end
RESET2:
        begin
                radr <= vect[31:2];
                radr2LSB <= vect[1:0];
                load_what <= em ? `PC_70 : `PC_310;
                state <= LOAD_MAC1;
        end
 
`include "ifetch.v"
`include "decode.v"
`ifdef SUPPORT_EM8
`include "byte_decode.v"
`include "byte_calc.v"
`include "byte_jsr.v"
`include "byte_jsl.v"
`ifdef SUPPORT_BYTE_IRQ
`include "byte_irq.v"
`endif
`endif
 
`include "load_mac.v"
`include "store.v"
 
WAIT_DHIT:
        if (dhit)
                state <= retstate;
 
`include "calc.v"
 
JSR_INDX1:
        if (ack_i) begin
                load_what <= `PC_310;
                state <= LOAD_MAC1;
                retstate <= LOAD_MAC1;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'd0;
                dat_o <= 32'd0;
                radr <= ir[39:8] + x;
                isp <= isp_dec;
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        dmiss <= `TRUE;
                        state <= WAIT_DHIT;
                end
        end
 
JSR161:
        if (ack_i) begin
                state <= IFETCH;
                retstate <= IFETCH;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                pc <= {{16{ir[23]}},ir[23:8]};
                isp <= isp_dec;
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        state <= WAIT_DHIT;
                        dmiss <= `TRUE;
                end
        end
/*
IRQ0:
        begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {wadr,2'b00};
                dat_o <= wdat;
                state <= IRQ1;
        end
IRQ1:
        if (ack_i) begin
                ir <= 64'd0;            // Force instruction decoder to BRK
                state <= IRQ2;
                retstate <= IRQ2;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                isp <= isp_dec;
`ifdef SUPPORT_DCACHE
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        state <= WAIT_DHIT;
                        dmiss <= `TRUE;
                end
`endif
        end
IRQ2:
        begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'hF;
                radr <= isp_dec;
                wadr <= isp_dec;
                wdat <= sr;
                adr_o <= {isp_dec,2'b00};
                dat_o <= sr;
                state <= IRQ3;
        end
IRQ3:
        if (ack_i) begin
                load_what <= `PC_310;
                state <= LOAD_MAC1;
                retstate <= LOAD_MAC1;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                isp <= isp_dec;
`ifdef SUPPORT_DCACHE
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        dmiss <= `TRUE;
                        state <= WAIT_DHIT;
                end
`endif
                radr <= vect[31:2];
                if (hwi)
                        im <= 1'b1;
                em <= 1'b0;                     // make sure we process in native mode; we might have been called up during emulation mode
        end
*/
MULDIV1:
        if (md_done) begin
                state <= IFETCH;
                case(ir[23:20])
                `MUL_RR:        begin res <= prod[31:0]; end
                `MULS_RR:       begin res <= prod[31:0]; end
                `DIV_RR:        begin res <= q; end
                `DIVS_RR:       begin res <= q; end
                `MOD_RR:        begin res <= r; end
                `MODS_RR:       begin res <= r; end
                endcase
        end
 
`ifdef SUPPORT_BERR
BUS_ERROR:
        begin
                radr <= isp_dec;
                wadr <= isp_dec;
                wdat <= opc;
                if (em | isOrb | isStb)
                        derr_address <= adr_o[31:0];
                else
                        derr_address <= adr_o[33:2];
                vect <= {vbr[31:9],9'd508,2'b00};
                hwi <= `TRUE;
                state <= IRQ0;
        end
INSN_BUS_ERROR:
        begin
                radr <= isp_dec;
                wadr <= isp_dec;
                wdat <= opc;
                vect <= {vbr[31:9],9'd509,2'b00};
                hwi <= `TRUE;
                state <= IRQ0;
        end
`endif
 
`ifdef SUPPORT_STRING
MVN1:
        begin
                radr <= x;
                res <= x + 32'd1;
                retstate <= MVN2;
                load_what <= `WORD_312;
                state <= LOAD_MAC1;
        end
MVN2:
        begin
                radr <= y;
                wadr <= y;
                store_what <= `STW_B;
                x <= res;
                res <= y + 32'd1;
                acc <= acc - 32'd1;
                state <= STORE1;
        end
MVN3:
        begin
                state <= IFETCH;
                y <= res;
                if (acc==32'hFFFFFFFF)
                        pc <= pc + 32'd1;
        end
MVP1:
        begin
                radr <= x;
                res <= x - 32'd1;
                retstate <= MVP2;
                load_what <= `WORD_312;
                state <= LOAD_MAC1;
        end
MVP2:
        begin
                radr <= y;
                wadr <= y;
                store_what <= `STW_B;
                x <= res;
                res <= y - 32'd1;
                acc <= acc - 32'd1;
                state <= STORE1;
        end
STS1:
        begin
                radr <= y;
                wadr <= y;
                store_what <= `STW_X;
                res <= y + 32'd1;
                acc <= acc - 32'd1;
                state <= STORE1;
        end
`endif
 
endcase
 
`include "cache_controller.v"
 
end
endmodule

Line No.	Rev	Author	Line
1	10	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch<remove>@opencores.org`
7			`// \|\|`
8			`//`
9			`// rtf65002.v`
10			`// - 32 bit CPU`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`// ============================================================================`
26			`//`
27	30	robfinch	`include "rtf65002_defines.v"
28	5	robfinch
29	21	robfinch	`module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);`
30	5	robfinch	`parameter IDLE = 3'd0;`
31			`parameter LOAD_DCACHE = 3'd1;`
32			`parameter LOAD_ICACHE = 3'd2;`
33			`parameter LOAD_IBUF1 = 3'd3;`
34			`parameter LOAD_IBUF2 = 3'd4;`
35			`parameter LOAD_IBUF3 = 3'd5;`
36	30	robfinch	`parameter RESET1 = 6'd0;`
37			`parameter IFETCH = 6'd1;`
38			`parameter DECODE = 6'd2;`
39			`parameter STORE1 = 6'd3;`
40			`parameter STORE2 = 6'd4;`
41			`parameter IRQ0 = 6'd5;`
42			`parameter IRQ1 = 6'd6;`
43			`parameter IRQ2 = 6'd7;`
44			`parameter IRQ3 = 6'd8;`
45			`parameter CALC = 6'd9;`
46			`parameter JSR_INDX1 = 6'd10;`
47			`parameter JSR161 = 6'd11;`
48			`parameter RTS1 = 6'd12;`
49			`parameter IY3 = 6'd13;`
50			`parameter BSR1 = 6'd14;`
51			`parameter BYTE_IX5 = 6'd15;`
52			`parameter BYTE_IY5 = 6'd16;`
53			`parameter BYTE_JSR1 = 6'd17;`
54			`parameter BYTE_JSR2 = 6'd18;`
55			`parameter BYTE_JSR3 = 6'd19;`
56			`parameter BYTE_IRQ1 = 6'd20;`
57			`parameter BYTE_IRQ2 = 6'd21;`
58			`parameter BYTE_IRQ3 = 6'd22;`
59			`parameter BYTE_IRQ4 = 6'd23;`
60			`parameter BYTE_IRQ5 = 6'd24;`
61			`parameter BYTE_IRQ6 = 6'd25;`
62			`parameter BYTE_IRQ7 = 6'd26;`
63			`parameter BYTE_IRQ8 = 6'd27;`
64			`parameter BYTE_IRQ9 = 6'd28;`
65			`parameter BYTE_JSR_INDX1 = 6'd29;`
66			`parameter BYTE_JSR_INDX2 = 6'd30;`
67			`parameter BYTE_JSR_INDX3 = 6'd31;`
68			`parameter BYTE_JSL1 = 6'd32;`
69			`parameter BYTE_JSL2 = 6'd33;`
70			`parameter BYTE_JSL3 = 6'd34;`
71			`parameter BYTE_JSL4 = 6'd35;`
72			`parameter BYTE_JSL5 = 6'd36;`
73			`parameter BYTE_JSL6 = 6'd37;`
74			`parameter BYTE_JSL7 = 6'd38;`
75			`parameter BYTE_PLP1 = 6'd39;`
76			`parameter BYTE_PLP2 = 6'd40;`
77			`parameter BYTE_PLA1 = 6'd41;`
78			`parameter BYTE_PLA2 = 6'd42;`
79			`parameter WAIT_DHIT = 6'd43;`
80			`parameter RESET2 = 6'd44;`
81			`parameter MULDIV1 = 6'd45;`
82			`parameter MULDIV2 = 6'd46;`
83			`parameter BYTE_DECODE = 6'd47;`
84			`parameter BYTE_CALC = 6'd48;`
85			`parameter BUS_ERROR = 6'd49;`
86			`parameter INSN_BUS_ERROR = 6'd50;`
87			`parameter LOAD_MAC1 = 6'd51;`
88			`parameter LOAD_MAC2 = 6'd52;`
89			`parameter MVN1 = 6'd53;`
90			`parameter MVN2 = 6'd54;`
91			`parameter MVN3 = 6'd55;`
92			`parameter MVP1 = 6'd56;`
93			`parameter MVP2 = 6'd57;`
94			`parameter STS1 = 6'd58;`
95	5	robfinch
96	21	robfinch	`input rst_md; // reset mode, 1=emulation mode, 0=native mode`
97	5	robfinch	`input rst_i;`
98			`input clk_i;`
99			`input nmi_i;`
100			`input irq_i;`
101	13	robfinch	`input [8:0] irq_vect;`
102	5	robfinch	`output reg [1:0] bte_o;`
103			`output reg [2:0] cti_o;`
104			`output reg [5:0] bl_o;`
105			`output reg lock_o;`
106			`output reg cyc_o;`
107			`output reg stb_o;`
108			`input ack_i;`
109	21	robfinch	`input err_i;`
110	5	robfinch	`output reg we_o;`
111			`output reg [3:0] sel_o;`
112			`output reg [33:0] adr_o;`
113			`input [31:0] dat_i;`
114			`output reg [31:0] dat_o;`
115
116	30	robfinch	`reg [5:0] state;`
117			`reg [5:0] retstate;`
118	5	robfinch	`reg [2:0] cstate;`
119	21	robfinch	`wire [63:0] insn;`
120			`reg [63:0] ibuf;`
121	5	robfinch	`reg [31:0] bufadr;`
122	25	robfinch	`reg [63:0] exbuf;`
123	5	robfinch
124			`reg cf,nf,zf,vf,bf,im,df,em;`
125			`reg em1;`
126	10	robfinch	`reg gie;`
127	25	robfinch	`reg hwi; // hardware interrupt indicator`
128	5	robfinch	`reg nmoi; // native mode on interrupt`
129			`wire [31:0] sr = {nf,vf,em,24'b0,bf,df,im,zf,cf};`
130			`wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};`
131			`reg nmi1,nmi_edge;`
132			`reg wai;`
133			`reg [31:0] acc;`
134			`reg [31:0] x;`
135			`reg [31:0] y;`
136			`reg [7:0] sp;`
137	13	robfinch	`reg [31:0] spage; // stack page`
138	5	robfinch	`wire [7:0] acc8 = acc[7:0];`
139			`wire [7:0] x8 = x[7:0];`
140			`wire [7:0] y8 = y[7:0];`
141			`reg [31:0] isp; // interrupt stack pointer`
142	12	robfinch	`wire [63:0] prod;`
143			`wire [31:0] q,r;`
144			`reg [31:0] tick;`
145	5	robfinch	`wire [7:0] sp_dec = sp - 8'd1;`
146			`wire [7:0] sp_inc = sp + 8'd1;`
147			`wire [31:0] isp_dec = isp - 32'd1;`
148			`wire [31:0] isp_inc = isp + 32'd1;`
149	25	robfinch	`reg [3:0] suppress_pcinc;`
150	5	robfinch	`reg [31:0] pc;`
151	23	robfinch	`reg [31:0] opc;`
152	30	robfinch	`wire [3:0] pc_inc;`
153			`wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc); // for branches`
154			`wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc); // for branches`
155			`wire [31:0] pcp8 = pc + 32'd8; // cache controller needs this`
156	13	robfinch	`reg [31:0] abs8; // 8 bit mode absolute address register`
157			`reg [31:0] vbr; // vector table base register`
158	5	robfinch	`wire bhit=pc==bufadr;`
159			`reg [31:0] regfile [15:0];`
160	21	robfinch	`reg [63:0] ir;`
161	5	robfinch	`wire [3:0] Ra = ir[11:8];`
162			`wire [3:0] Rb = ir[15:12];`
163			`reg [31:0] rfoa;`
164			`reg [31:0] rfob;`
165			`always @(Ra or x or y or acc)`
166			`case(Ra)`
167			`4'h0: rfoa <= 32'd0;`
168			`4'h1: rfoa <= acc;`
169			`4'h2: rfoa <= x;`
170			`4'h3: rfoa <= y;`
171			`default: rfoa <= regfile[Ra];`
172			`endcase`
173			`always @(Rb or x or y or acc)`
174			`case(Rb)`
175			`4'h0: rfob <= 32'd0;`
176			`4'h1: rfob <= acc;`
177			`4'h2: rfob <= x;`
178			`4'h3: rfob <= y;`
179			`default: rfob <= regfile[Rb];`
180			`endcase`
181			`reg [3:0] Rt;`
182			`reg [33:0] ea;`
183			`reg first_ifetch;`
184	12	robfinch	`reg [31:0] lfsr;`
185			`wire lfsr_fb;`
186			`xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);`
187	5	robfinch	`reg [31:0] a, b;`
188	30	robfinch	`ifdef SUPPORT_SHIFT
189	19	robfinch	`wire [31:0] shlo = a << b[4:0];`
190			`wire [31:0] shro = a >> b[4:0];`
191	30	robfinch	`else
192			`wire [31:0] shlo = 32'd0;`
193			`wire [31:0] shro = 32'd0;`
194			`endif
195	5	robfinch	`reg [7:0] b8;`
196			`reg [32:0] res;`
197			`reg [8:0] res8;`
198			`wire resv8,resv32;`
199			`wire resc8 = res8[8];`
200			`wire resc32 = res[32];`
201			`wire resz8 = res8[7:0]==8'h00;`
202			`wire resz32 = res[31:0]==32'd0;`
203			`wire resn8 = res8[7];`
204			`wire resn32 = res[31];`
205
206			`reg [31:0] vect;`
207			`reg [31:0] ia; // temporary reg to hold indirect address`
208	20	robfinch	`wire [31:0] iapy8 = abs8 + ia + y[7:0];`
209	5	robfinch	`reg isInsnCacheLoad;`
210			`reg isDataCacheLoad;`
211	10	robfinch	`reg isCacheReset;`
212	5	robfinch	`wire hit0,hit1;`
213	30	robfinch	`ifdef SUPPORT_DCACHE
214	5	robfinch	`wire dhit;`
215	30	robfinch	`else
216			`wire dhit = 1'b0;`
217			`endif
218	10	robfinch	`reg write_allocate;`
219	5	robfinch	`reg wr;`
220			`reg [3:0] wrsel;`
221			`reg [31:0] radr;`
222			`reg [1:0] radr2LSB;`
223			`wire [33:0] radr34 = {radr,radr2LSB};`
224			`wire [33:0] radr34p1 = radr34 + 34'd1;`
225			`reg [31:0] wadr;`
226			`reg [1:0] wadr2LSB;`
227			`reg [31:0] wdat;`
228			`wire [31:0] rdat;`
229	21	robfinch	`reg [3:0] load_what;`
230			`reg [3:0] store_what;`
231	23	robfinch	`reg [31:0] derr_address;`
232	5	robfinch	`reg imiss;`
233			`reg dmiss;`
234			`reg icacheOn,dcacheOn;`
235	30	robfinch	`ifdef SUPPORT_DCACHE
236	20	robfinch	`wire unCachedData = radr[31:20]==12'hFFD \|\| !dcacheOn; // I/O area is uncached`
237	30	robfinch	`else
238			`wire unCachedData = 1'b1;`
239			`endif
240			`ifdef SUPPORT_ICACHE
241	20	robfinch	`wire unCachedInsn = pc[31:13]==19'h0 \|\| !icacheOn; // The lowest 8kB is uncached.`
242	30	robfinch	`else
243			`wire unCachedInsn = 1'b1;`
244			`endif
245	5	robfinch
246	30	robfinch	`reg [31:0] history_buf [63:0];`
247			`reg [5:0] history_ndx;`
248			`reg hist_capture;`
249
250			`reg isBrk,isMove,isSts;`
251			`reg isRTI,isRTL,isRTS;`
252			`reg isOrb,isStb;`
253			`reg isRMW;`
254			`reg isSub,isSub8;`
255
256
257	5	robfinch	wire isCmp = ir[7:0]==`CPX_ZPX \|\| ir[7:0]==`CPX_ABS \|\| ir[7:0]==`CPX_IMM32 \|\|
258			ir[7:0]==`CPY_ZPX \|\| ir[7:0]==`CPY_ABS \|\| ir[7:0]==`CPY_IMM32;
259			`wire isRMW32 =`
260			ir[7:0]==`ASL_ZPX \|\| ir[7:0]==`ROL_ZPX \|\| ir[7:0]==`LSR_ZPX \|\| ir[7:0]==`ROR_ZPX \|\| ir[7:0]==`INC_ZPX \|\| ir[7:0]==`DEC_ZPX \|\|
261			ir[7:0]==`ASL_ABS \|\| ir[7:0]==`ROL_ABS \|\| ir[7:0]==`LSR_ABS \|\| ir[7:0]==`ROR_ABS \|\| ir[7:0]==`INC_ABS \|\| ir[7:0]==`DEC_ABS \|\|
262			ir[7:0]==`ASL_ABSX \|\| ir[7:0]==`ROL_ABSX \|\| ir[7:0]==`LSR_ABSX \|\| ir[7:0]==`ROR_ABSX \|\| ir[7:0]==`INC_ABSX \|\| ir[7:0]==`DEC_ABSX \|\|
263			ir[7:0]==`TRB_ZP \|\| ir[7:0]==`TRB_ZPX \|\| ir[7:0]==`TRB_ABS \|\| ir[7:0]==`TSB_ZP \|\| ir[7:0]==`TSB_ZPX \|\| ir[7:0]==`TSB_ABS;
264			`;`
265			`wire isRMW8 =`
266			ir[7:0]==`ASL_ZP \|\| ir[7:0]==`ROL_ZP \|\| ir[7:0]==`LSR_ZP \|\| ir[7:0]==`ROR_ZP \|\| ir[7:0]==`INC_ZP \|\| ir[7:0]==`DEC_ZP \|\|
267			ir[7:0]==`ASL_ZPX \|\| ir[7:0]==`ROL_ZPX \|\| ir[7:0]==`LSR_ZPX \|\| ir[7:0]==`ROR_ZPX \|\| ir[7:0]==`INC_ZPX \|\| ir[7:0]==`DEC_ZPX \|\|
268			ir[7:0]==`ASL_ABS \|\| ir[7:0]==`ROL_ABS \|\| ir[7:0]==`LSR_ABS \|\| ir[7:0]==`ROR_ABS \|\| ir[7:0]==`INC_ABS \|\| ir[7:0]==`DEC_ABS \|\|
269			ir[7:0]==`ASL_ABSX \|\| ir[7:0]==`ROL_ABSX \|\| ir[7:0]==`LSR_ABSX \|\| ir[7:0]==`ROR_ABSX \|\| ir[7:0]==`INC_ABSX \|\| ir[7:0]==`DEC_ABSX \|\|
270			ir[7:0]==`TRB_ZP \|\| ir[7:0]==`TRB_ZPX \|\| ir[7:0]==`TRB_ABS \|\| ir[7:0]==`TSB_ZP \|\| ir[7:0]==`TSB_ZPX \|\| ir[7:0]==`TSB_ABS;
271			`;`
272	30	robfinch
273			`// Registerable decodes`
274			`// The following decodes can be registered because they aren't needed until at least the cycle after`
275			`// the DECODE stage.`
276
277			`always @(posedge clk)`
278			`if (state==DECODE) begin`
279			isSub <= ir[7:0]==`SUB_ZPX \|\| ir[7:0]==`SUB_IX \|\| ir[7:0]==`SUB_IY \|\|
280			ir[7:0]==`SUB_ABS \|\| ir[7:0]==`SUB_ABSX \|\| ir[7:0]==`SUB_IMM8 \|\| ir[7:0]==`SUB_IMM16 \|\| ir[7:0]==`SUB_IMM32;
281			isSub8 <= ir[7:0]==`SBC_ZP \|\| ir[7:0]==`SBC_ZPX \|\| ir[7:0]==`SBC_IX \|\| ir[7:0]==`SBC_IY \|\| ir[7:0]==`SBC_I \|\|
282			ir[7:0]==`SBC_ABS \|\| ir[7:0]==`SBC_ABSX \|\| ir[7:0]==`SBC_ABSY \|\| ir[7:0]==`SBC_IMM;
283			`isRMW <= em ? isRMW8 : isRMW32;`
284			isOrb <= ir[7:0]==`ORB_ZPX \|\| ir[7:0]==`ORB_IX \|\| ir[7:0]==`ORB_IY \|\| ir[7:0]==`ORB_ABS \|\| ir[7:0]==`ORB_ABSX;
285			isStb <= ir[7:0]==`STB_ZPX \|\| ir[7:0]==`STB_ABS \|\| ir[7:0]==`STB_ABSX;
286			isRTI <= ir[7:0]==`RTI;
287			isRTL <= ir[7:0]==`RTL;
288			isRTS <= ir[7:0]==`RTS;
289			isBrk <= ir[7:0]==`BRK;
290			isMove <= ir[7:0]==`MVP \|\| ir[7:0]==`MVN;
291			isSts <= ir[7:0]==`STS;
292			`end`
293
294			`ifdef SUPPORT_EXEC
295	25	robfinch	wire isExec = ir[7:0]==`EXEC;
296			wire isAtni = ir[7:0]==`ATNI;
297	30	robfinch	`else
298			`wire isExec = 1'b0;`
299			`wire isAtni = 1'b0;`
300			`endif
301	12	robfinch	wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
302			`wire md_done;`
303			`wire clk;`
304	21	robfinch	`reg isIY;`
305	12	robfinch
306	30	robfinch	`rtf65002_pcinc upci1`
307			`(`
308			`.opcode(ir[7:0]),`
309			`.suppress_pcinc(suppress_pcinc),`
310			`.inc(pc_inc)`
311			`);`
312
313	12	robfinch	`mult_div umd1`
314			`(`
315	30	robfinch	`.rst(rst_i),`
316	12	robfinch	`.clk(clk),`
317			`.ld(ld_muldiv),`
318			`.op(ir[23:20]),`
319			`.a(rfoa),`
320			`.b(rfob),`
321			`.p(prod),`
322			`.q(q),`
323			`.r(r),`
324			`.done(md_done)`
325			`);`
326	30	robfinch
327			`ifdef SUPPORT_ICACHE
328			`rtf65002_icachemem icm0 (`
329	12	robfinch	`.wclk(clk),`
330	5	robfinch	`.wr(ack_i & isInsnCacheLoad),`
331			`.adr(adr_o),`
332			`.dat(dat_i),`
333	30	robfinch	`.rclk(~clk),`
334	5	robfinch	`.pc(pc),`
335			`.insn(insn)`
336			`);`
337
338	30	robfinch	`rtf65002_itagmem tgm0 (`
339	12	robfinch	`.wclk(clk),`
340	10	robfinch	`.wr((ack_i & isInsnCacheLoad)\|isCacheReset),`
341			`.adr({adr_o[31:1],!isCacheReset}),`
342	30	robfinch	`.rclk(~clk),`
343	5	robfinch	`.pc(pc),`
344			`.hit0(hit0),`
345			`.hit1(hit1)`
346			`);`
347
348			`wire ihit = (hit0 & hit1);//(pc[2:0] > 3'd1 ? hit1 : 1'b1));`
349	30	robfinch	`else
350			`wire ihit = 1'b0;`
351			`endif
352	5	robfinch
353	30	robfinch	`ifdef SUPPORT_DCACHE
354			`rtf65002_dcachemem dcm0 (`
355	12	robfinch	`.wclk(clk),`
356	5	robfinch	`.wr(wr \| (ack_i & isDataCacheLoad)),`
357			`.sel(wr ? wrsel : sel_o),`
358			`.wadr(wr ? wadr : adr_o[33:2]),`
359			`.wdat(wr ? wdat : dat_i),`
360	30	robfinch	`.rclk(~clk),`
361	5	robfinch	`.radr(radr),`
362			`.rdat(rdat)`
363			`);`
364
365	30	robfinch	`rtf65002_dtagmem dtm0 (`
366	12	robfinch	`.wclk(clk),`
367	5	robfinch	`.wr(wr \| (ack_i & isDataCacheLoad)),`
368			`.wadr(wr ? wadr : adr_o[33:2]),`
369	30	robfinch	`.rclk(~clk),`
370	5	robfinch	`.radr(radr),`
371			`.hit(dhit)`
372			`);`
373	30	robfinch	`endif
374	5	robfinch
375			`overflow uovr1 (`
376			`.op(isSub),`
377			`.a(a[31]),`
378			`.b(b[31]),`
379			`.s(res[31]),`
380			`.v(resv32)`
381			`);`
382
383			`overflow uovr2 (`
384			`.op(isSub8),`
385			`.a(acc8[7]),`
386			`.b(b8[7]),`
387			`.s(res8[7]),`
388			`.v(resv8)`
389			`);`
390
391			`wire [7:0] bcaio;`
392			`wire [7:0] bcao;`
393			`wire [7:0] bcsio;`
394			`wire [7:0] bcso;`
395			`wire bcaico,bcaco,bcsico,bcsco;`
396
397	30	robfinch	`ifdef SUPPORT_BCD
398	5	robfinch	`BCDAdd ubcdai1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcaio),.c(bcaico));`
399			`BCDAdd ubcda2 (.ci(cf),.a(acc8),.b(b8),.o(bcao),.c(bcaco));`
400			`BCDSub ubcdsi1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcsio),.c(bcsico));`
401			`BCDSub ubcds2 (.ci(cf),.a(acc8),.b(b8),.o(bcso),.c(bcsco));`
402	30	robfinch	`endif
403	5	robfinch
404			`reg [7:0] dati;`
405			`always @(radr2LSB or dat_i)`
406			`case(radr2LSB)`
407			`2'd0: dati <= dat_i[7:0];`
408			`2'd1: dati <= dat_i[15:8];`
409			`2'd2: dati <= dat_i[23:16];`
410			`2'd3: dati <= dat_i[31:24];`
411			`endcase`
412			`reg [7:0] rdat8;`
413			`always @(radr2LSB or rdat)`
414			`case(radr2LSB)`
415			`2'd0: rdat8 <= rdat[7:0];`
416			`2'd1: rdat8 <= rdat[15:8];`
417			`2'd2: rdat8 <= rdat[23:16];`
418			`2'd3: rdat8 <= rdat[31:24];`
419			`endcase`
420
421			`reg takb;`
422			`always @(ir or cf or vf or nf or zf)`
423			`case(ir[7:0])`
424			`BEQ: takb <= zf;
425			`BNE: takb <= !zf;
426			`BPL: takb <= !nf;
427			`BMI: takb <= nf;
428			`BCS: takb <= cf;
429			`BCC: takb <= !cf;
430			`BVS: takb <= vf;
431			`BVC: takb <= !vf;
432			`BRA: takb <= 1'b1;
433			`BRL: takb <= 1'b1;
434	30	robfinch	`BHI: takb <= cf & !zf;
435			`BLS: takb <= !cf \| zf;
436			`BGE: takb <= (nf & vf)\|(!nf & !vf);
437			`BLT: takb <= (nf & !vf)\|(!nf & vf);
438			`BGT: takb <= (nf & vf & !zf) + (!nf & !vf & !zf);
439			`BLE: takb <= zf \| (nf & !vf)\|(!nf & vf);
440	10	robfinch	//`BAZ: takb <= acc8==8'h00;
441			//`BXZ: takb <= x8==8'h00;
442	5	robfinch	`default: takb <= 1'b0;`
443			`endcase`
444
445	30	robfinch	`wire [31:0] zp_address = {abs8[31:12],4'h0,ir[15:8]};`
446			`wire [31:0] zpx_address = {abs8[31:12],4'h0,ir[15:8]} + x8;`
447			`wire [31:0] zpy_address = {abs8[31:12],4'h0,ir[15:8]} + y8;`
448			`wire [31:0] abs_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8]};`
449			`wire [31:0] absx_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8] + {8'h0,x8}}; // simulates 64k bank wrap-around`
450			`wire [31:0] absy_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8] + {8'h0,y8}};`
451			`wire [31:0] zpx32xy_address = ir[23:12] + rfoa;`
452			`wire [31:0] absx32xy_address = ir[47:16] + rfob;`
453			`wire [31:0] zpx32_address = ir[31:20] + rfob;`
454			`wire [31:0] absx32_address = ir[55:24] + rfob;`
455	5	robfinch
456	30	robfinch	`reg [32:0] calc_res;`
457			`always @(a or b or b8 or x or y or df or cf or Rt or shlo or shro)`
458			`begin`
459			`case(ir[7:0])`
460			`RR:
461			`case(ir[23:20])`
462			`ASL_RRR: calc_res <= shlo;
463			`LSR_RRR: calc_res <= shro;
464			`default: calc_res <= 33'd0;`
465			`endcase`
466			`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: calc_res <= a + b + {31'b0,df&cf};
467			`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: calc_res <= a - b - {31'b0,df&~cf&\|Rt}; // Also CMP
468			`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: calc_res <= a & b; // Also BIT
469			`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: calc_res <= a \| b; // Also LD
470			`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: calc_res <= a ^ b;
471			`LDX_ZPY,`LDX_ABS,`LDX_ABSY: calc_res <= b;
472			`LDY_ZPX,`LDY_ABS,`LDY_ABSX: calc_res <= b;
473			`CPX_ZPX,`CPX_ABS: calc_res <= x - b;
474			`CPY_ZPX,`CPY_ABS: calc_res <= y - b;
475			`ASL_IMM8: calc_res <= shlo;
476			`LSR_IMM8: calc_res <= shro;
477			`ASL_ZPX,`ASL_ABS,`ASL_ABSX: calc_res <= {b,1'b0};
478			`ROL_ZPX,`ROL_ABS,`ROL_ABSX: calc_res <= {b,cf};
479			`LSR_ZPX,`LSR_ABS,`LSR_ABSX: calc_res <= {b[0],1'b0,b[31:1]};
480			`ROR_ZPX,`ROR_ABS,`ROR_ABSX: calc_res <= {b[0],cf,b[31:1]};
481			`INC_ZPX,`INC_ABS,`INC_ABSX: calc_res <= b + 32'd1;
482			`DEC_ZPX,`DEC_ABS,`DEC_ABSX: calc_res <= b - 32'd1;
483			`ORB_ZPX,`ORB_ABS,`ORB_ABSX: calc_res <= a \| {24'h0,b8};
484			`default: calc_res <= 33'd0;`
485			`endcase`
486			`end`
487
488
489	5	robfinch	`//-----------------------------------------------------------------------------`
490			`// Clock control`
491			`// - reset or NMI reenables the clock`
492			`// - this circuit must be under the clk_i domain`
493			`//-----------------------------------------------------------------------------`
494			`//`
495			`reg cpu_clk_en;`
496			`reg clk_en;`
497			`BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );`
498
499			`always @(posedge clk_i)`
500			`if (rst_i) begin`

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