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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [store.v] - Blame information for rev 30

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                            
// Memory store states
// The store states work for either eight bit or 32 bit mode              
// ============================================================================
//
// Stores always write through to memory, then optionally update the cache if
// there was a write hit.
STORE1:
        begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                if (em || isStb) begin
                        case(wadr2LSB)
                        2'd0:   sel_o <= 4'b0001;
                        2'd1:   sel_o <= 4'b0010;
                        2'd2:   sel_o <= 4'b0100;
                        2'd3:   sel_o <= 4'b1000;
                        endcase
                end
                else
                        sel_o <= 4'hf;
                adr_o <= {wadr,2'b00};
                case(store_what)
                `STW_ACC:       dat_o <= acc;
                `STW_X:         dat_o <= x;
                `STW_Y:         dat_o <= y;
                `STW_PC:        dat_o <= pc;
                `STW_PC2:       dat_o <= pc + 32'd2;
                `STW_PCHWI:     dat_o <= pc+{30'b0,~hwi,1'b0};
                `STW_SR:        dat_o <= sr;
                `STW_RFA:       dat_o <= rfoa;
                `STW_RFA8:      dat_o <= {4{rfoa[7:0]}};
                `STW_A:         dat_o <= a;
                `STW_B:         dat_o <= b;
                `STW_CALC:      dat_o <= calc_res;
`ifdef SUPPORT_EM8
                `STW_ACC8:      dat_o <= {4{acc8}};
                `STW_X8:        dat_o <= {4{x8}};
                `STW_Y8:        dat_o <= {4{y8}};
                `STW_PC3124:    dat_o <= {4{pc[31:24]}};
                `STW_PC2316:    dat_o <= {4{pc[23:16]}};
                `STW_PC158:             dat_o <= {4{pc[15:8]}};
                `STW_PC70:              dat_o <= {4{pc[7:0]}};
                `STW_SR70:              dat_o <= {4{sr8}};
`endif
                default:        dat_o <= wdat;
                endcase
`ifdef SUPPORT_DCACHE
                radr <= wadr;           // Do a cache read to test the hit
`endif
                state <= STORE2;
        end
 
// Terminal state for stores. Update the data cache if there was a cache hit.
// Clear any previously set lock status
STORE2:
        if (ack_i) begin
                wdat <= dat_o;
                if (isMove|isSts) begin
                        state <= MVN3;
                        retstate <= MVN3;
                end
                else begin
                        state <= IFETCH;
                        retstate <= IFETCH;
                end
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                case(store_what)
                `STW_PC,`STW_PC2,`STW_PCHWI:
                        if (isBrk) begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_SR;
                                state <= STORE1;
                                retstate <= STORE1;
                        end
                `STW_SR:
                        if (isBrk) begin
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                retstate <= LOAD_MAC1;
                                radr <= vect[31:2];
                                if (hwi)
                                        im <= 1'b1;
                                em <= 1'b0;                     // make sure we process in native mode; we might have been called up during emulation mode
                        end
`ifdef SUPPORT_EM8
                `STW_PC3124:
                        begin
                                store_what <= `STW_PC2316;
                                state <= STORE1;
                        end
                `STW_PC2316:
                        begin
                                store_what <= `STW_PC158;
                                state <= STORE1;
                        end
                `STW_PC158:
                        begin
                                store_what <= `STW_PC70;
                                state <= STORE1;
                        end
                `STW_PC70:
                        begin
                                if (ir[7:0]==`BRK) begin
                                        store_what <= `STW_SR70;
                                        state <= STORE1;
                                end
                        end
`endif
                endcase
`ifdef SUPPORT_DCACHE
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        dmiss <= `TRUE;
                        state <= WAIT_DHIT;
                end
`endif
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
`endif
 
 

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// Memory store states`
22			`// The store states work for either eight bit or 32 bit mode`
23			`// ============================================================================`
24			`//`
25			`// Stores always write through to memory, then optionally update the cache if`
26			`// there was a write hit.`
27			`STORE1:`
28			`begin`
29			`cyc_o <= 1'b1;`
30			`stb_o <= 1'b1;`
31			`we_o <= 1'b1;`
32	25	robfinch	`if (em \|\| isStb) begin`
33	20	robfinch	`case(wadr2LSB)`
34			`2'd0: sel_o <= 4'b0001;`
35			`2'd1: sel_o <= 4'b0010;`
36			`2'd2: sel_o <= 4'b0100;`
37			`2'd3: sel_o <= 4'b1000;`
38			`endcase`
39	25	robfinch	`end`
40	20	robfinch	`else`
41			`sel_o <= 4'hf;`
42			`adr_o <= {wadr,2'b00};`
43	30	robfinch	`case(store_what)`
44			`STW_ACC: dat_o <= acc;
45			`STW_X: dat_o <= x;
46			`STW_Y: dat_o <= y;
47			`STW_PC: dat_o <= pc;
48			`STW_PC2: dat_o <= pc + 32'd2;
49			`STW_PCHWI: dat_o <= pc+{30'b0,~hwi,1'b0};
50			`STW_SR: dat_o <= sr;
51			`STW_RFA: dat_o <= rfoa;
52			`STW_RFA8: dat_o <= {4{rfoa[7:0]}};
53			`STW_A: dat_o <= a;
54			`STW_B: dat_o <= b;
55			`STW_CALC: dat_o <= calc_res;
56			`ifdef SUPPORT_EM8
57			`STW_ACC8: dat_o <= {4{acc8}};
58			`STW_X8: dat_o <= {4{x8}};
59			`STW_Y8: dat_o <= {4{y8}};
60			`STW_PC3124: dat_o <= {4{pc[31:24]}};
61			`STW_PC2316: dat_o <= {4{pc[23:16]}};
62			`STW_PC158: dat_o <= {4{pc[15:8]}};
63			`STW_PC70: dat_o <= {4{pc[7:0]}};
64			`STW_SR70: dat_o <= {4{sr8}};
65			`endif
66			`default: dat_o <= wdat;`
67			`endcase`
68			`ifdef SUPPORT_DCACHE
69	20	robfinch	`radr <= wadr; // Do a cache read to test the hit`
70	30	robfinch	`endif
71	20	robfinch	`state <= STORE2;`
72			`end`
73
74			`// Terminal state for stores. Update the data cache if there was a cache hit.`
75			`// Clear any previously set lock status`
76			`STORE2:`
77			`if (ack_i) begin`
78	30	robfinch	`wdat <= dat_o;`
79			`if (isMove\|isSts) begin`
80	23	robfinch	`state <= MVN3;`
81	30	robfinch	`retstate <= MVN3;`
82			`end`
83			`else begin`
84	23	robfinch	`state <= IFETCH;`
85	30	robfinch	`retstate <= IFETCH;`
86			`end`
87	20	robfinch	`lock_o <= 1'b0;`
88			`cyc_o <= 1'b0;`
89			`stb_o <= 1'b0;`
90			`we_o <= 1'b0;`
91			`sel_o <= 4'h0;`
92			`adr_o <= 34'h0;`
93			`dat_o <= 32'h0;`
94	30	robfinch	`case(store_what)`
95			`STW_PC,`STW_PC2,`STW_PCHWI:
96			`if (isBrk) begin`
97			`radr <= isp_dec;`
98			`wadr <= isp_dec;`
99			`isp <= isp_dec;`
100			store_what <= `STW_SR;
101			`state <= STORE1;`
102			`retstate <= STORE1;`
103			`end`
104			`STW_SR:
105			`if (isBrk) begin`
106			load_what <= `PC_310;
107			`state <= LOAD_MAC1;`
108			`retstate <= LOAD_MAC1;`
109			`radr <= vect[31:2];`
110			`if (hwi)`
111			`im <= 1'b1;`
112			`em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode`
113			`end`
114			`ifdef SUPPORT_EM8
115			`STW_PC3124:
116			`begin`
117			store_what <= `STW_PC2316;
118			`state <= STORE1;`
119			`end`
120			`STW_PC2316:
121			`begin`
122			store_what <= `STW_PC158;
123			`state <= STORE1;`
124			`end`
125			`STW_PC158:
126			`begin`
127			store_what <= `STW_PC70;
128			`state <= STORE1;`
129			`end`
130			`STW_PC70:
131			`begin`
132			if (ir[7:0]==`BRK) begin
133			store_what <= `STW_SR70;
134			`state <= STORE1;`
135			`end`
136			`end`
137			`endif
138			`endcase`
139			`ifdef SUPPORT_DCACHE
140	20	robfinch	`if (dhit) begin`
141			`wrsel <= sel_o;`
142			`wr <= 1'b1;`
143			`end`
144			`else if (write_allocate) begin`
145			dmiss <= `TRUE;
146			`state <= WAIT_DHIT;`
147			`end`
148	30	robfinch	`endif
149	20	robfinch	`end`
150	30	robfinch	`ifdef SUPPORT_BERR
151	21	robfinch	`else if (err_i) begin`
152			`lock_o <= 1'b0;`
153			`cyc_o <= 1'b0;`
154			`stb_o <= 1'b0;`
155			`we_o <= 1'b0;`
156			`sel_o <= 4'h0;`
157			`dat_o <= 32'h0;`
158			`state <= BUS_ERROR;`
159			`end`
160	30	robfinch	`endif
161	21	robfinch
162	20	robfinch

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [store.v] - Blame information for rev 30