OpenCores
URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [BRANCH.v] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch
//============================================================================
2
//  BRANCH.v
3
//  Jcc disp8
4
//  - conditional branches
5
//  - fetch an 8 bit displacement and add into IP
6
//
7
//
8
//  (C) 2009-2012 Robert Finch
9
//  Stratford
10 7 robfinch
//  robfinch<remove>@finitron.ca
11 2 robfinch
//
12
//
13
// This source file is free software: you can redistribute it and/or modify 
14
// it under the terms of the GNU Lesser General Public License as published 
15
// by the Free Software Foundation, either version 3 of the License, or     
16
// (at your option) any later version.                                      
17
//                                                                          
18
// This source file is distributed in the hope that it will be useful,      
19
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
20
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
21
// GNU General Public License for more details.                             
22
//                                                                          
23
// You should have received a copy of the GNU General Public License        
24
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
25
//
26
//
27
//=============================================================================
28
//
29
// Fetch branch displacement if taking branch, otherwise skip
30
//
31
BRANCH1:
32
        if (take_br) begin
33 7 robfinch
                code_read();
34 2 robfinch
                state <= BRANCH2;
35
        end
36
        else begin
37
                ip <= ip_inc;
38
                state <= IFETCH;
39
        end
40
BRANCH2:
41
        if (ack_i) begin
42 7 robfinch
                term_code_read();
43 2 robfinch
                disp16 <= {{8{dat_i[7]}},dat_i};
44
                state <= BRANCH3;
45
        end
46
BRANCH3:
47
        begin
48
                ip <= ip + disp16;
49
                state <= IFETCH;
50
        end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.