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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [DIVIDE.v] - Blame information for rev 6

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//============================================================================
//  DIVIDE.v
//
//  (C) 2009-2012 Robert Finch
//  Stratford
//  robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//=============================================================================
//
// Check for divide by zero
// Load the divider
DIVIDE1:
        begin
                state <= DIVIDE2;
                // Check for divide by zero
                if (w) begin
                        if (b[15:0]==16'h0000) begin
                                $display("Divide by zero");
                                int_num <= 8'h00;
                                state <= INT2;
                        end
                        else
                                ld_div32 <= 1'b1;
                end
                else begin
                        if (b[7:0]==8'h00) begin
                                $display("Divide by zero");
                                int_num <= 8'h00;
                                state <= INT2;
                        end
                        else
                                ld_div16 <= 1'b1;
                end
        end
DIVIDE2:
        begin
                ld_div32 <= 1'b0;
                ld_div16 <= 1'b0;
                state <= DIVIDE2a;
        end
DIVIDE2a:
        begin
                if (w & div32_done)
                        state <= DIVIDE3;
                else if (!w & div16_done)
                        state <= DIVIDE3;
        end
 
// Assign results to registers
// Trap on divider overflow
DIVIDE3:
        begin
                state <= IFETCH;
                if (w) begin
                        ax <= q32[15:0];
                        dx <= r32[15:0];
                        if (TTT[0]) begin
                                if (q32[31:16]!={16{q32[15]}}) begin
                                        int_num <= 8'h00;
                                        state <= INT2;
                                end
                        end
                        else begin
                                if (q32[31:16]!=16'h0000) begin
                                        int_num <= 8'h00;
                                        state <= INT2;
                                end
                        end
                end
                else begin
                        ax[ 7:0] <= q16[7:0];
                        ax[15:8] <= r16;
                        if (TTT[0]) begin
                                if (q16[15:8]!={8{q16[7]}}) begin
                                        int_num <= 8'h00;
                                        state <= INT2;
                                end
                        end
                        else begin
                                if (q16[15:8]!=8'h00) begin
                                        int_num <= 8'h00;
                                        state <= INT2;
                                end
                        end
                end
        end

Line No.	Rev	Author	Line
1	6	robfinch	`//============================================================================`
2			`// DIVIDE.v`
3			`//`
4			`// (C) 2009-2012 Robert Finch`
5			`// Stratford`
6			`// robfinch<remove>@opencores.org`
7			`//`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`//`
23			`//=============================================================================`
24			`//`
25			`// Check for divide by zero`
26			`// Load the divider`
27			`DIVIDE1:`
28			`begin`
29			`state <= DIVIDE2;`
30			`// Check for divide by zero`
31			`if (w) begin`
32			`if (b[15:0]==16'h0000) begin`
33			`$display("Divide by zero");`
34			`int_num <= 8'h00;`
35			`state <= INT2;`
36			`end`
37			`else`
38			`ld_div32 <= 1'b1;`
39			`end`
40			`else begin`
41			`if (b[7:0]==8'h00) begin`
42			`$display("Divide by zero");`
43			`int_num <= 8'h00;`
44			`state <= INT2;`
45			`end`
46			`else`
47			`ld_div16 <= 1'b1;`
48			`end`
49			`end`
50			`DIVIDE2:`
51			`begin`
52			`ld_div32 <= 1'b0;`
53			`ld_div16 <= 1'b0;`
54			`state <= DIVIDE2a;`
55			`end`
56			`DIVIDE2a:`
57			`begin`
58			`if (w & div32_done)`
59			`state <= DIVIDE3;`
60			`else if (!w & div16_done)`
61			`state <= DIVIDE3;`
62			`end`
63
64			`// Assign results to registers`
65			`// Trap on divider overflow`
66			`DIVIDE3:`
67			`begin`
68			`state <= IFETCH;`
69			`if (w) begin`
70			`ax <= q32[15:0];`
71			`dx <= r32[15:0];`
72			`if (TTT[0]) begin`
73			`if (q32[31:16]!={16{q32[15]}}) begin`
74			`int_num <= 8'h00;`
75			`state <= INT2;`
76			`end`
77			`end`
78			`else begin`
79			`if (q32[31:16]!=16'h0000) begin`
80			`int_num <= 8'h00;`
81			`state <= INT2;`
82			`end`
83			`end`
84			`end`
85			`else begin`
86			`ax[ 7:0] <= q16[7:0];`
87			`ax[15:8] <= r16;`
88			`if (TTT[0]) begin`
89			`if (q16[15:8]!={8{q16[7]}}) begin`
90			`int_num <= 8'h00;`
91			`state <= INT2;`
92			`end`
93			`end`
94			`else begin`
95			`if (q16[15:8]!=8'h00) begin`
96			`int_num <= 8'h00;`
97			`state <= INT2;`
98			`end`
99			`end`
100			`end`
101			`end`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [DIVIDE.v] - Blame information for rev 6