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// ============================================================================
//  (C) 2009,2010,2012  Robert Finch
//  robfinch<remove>@opencores.org
//
//  EXECUTE
//  - execute instruction
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// ============================================================================
//
EXECUTE:
        begin
                casex(ir)
 
                `EXTOP:
                        casex(ir2)
                        `LxDT: state <= FETCH_DESC;
                        endcase
 
                `DAA:
                        begin
                                state <= IFETCH;
                        end
 
                `ALU_I2R8,`ALU_I2R16,`ADD,`ADD_ALI8,`ADD_AXI16,`ADC,`ADC_ALI8,`ADC_AXI16:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                cf <= carry   (1'b0,amsb,bmsb,resn);
                                vf <= overflow(1'b0,amsb,bmsb,resn);
                                sf <= resn;
                                zf <= resz;
                        end
 
                `AND,`OR,`XOR,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`AND_AXI16,`OR_AXI16,`XOR_AXI16:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                cf <= 1'b0;
                                vf <= 1'b0;
                                sf <= resn;
                                zf <= resz;
                        end
 
                `TEST:
                        begin
                                state <= IFETCH;
                                res <= alu_o;
                                pf <= pres;
                                cf <= 1'b0;
                                vf <= 1'b0;
                                sf <= resn;
                                zf <= resz;
                        end
 
                `CMP,`CMP_ALI8,`CMP_AXI16:
                        begin
                                state <= IFETCH;
                                pf <= pres;
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                cf <= carry   (1'b1,amsb,bmsb,resn);
                                vf <= overflow(1'b1,amsb,bmsb,resn);
                                sf <= resn;
                                zf <= resz;
                        end
 
                `SBB,`SUB,`SBB_ALI8,`SUB_ALI8,`SBB_AXI16,`SUB_AXI16:
                        begin
                                wrregs <= 1'b1;
                                state <= IFETCH;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                cf <= carry   (1'b1,amsb,bmsb,resn);
                                vf <= overflow(1'b1,amsb,bmsb,resn);
                                sf <= resn;
                                zf <= resz;
                        end
 
                8'hF6,8'hF7:
                        begin
                                state <= IFETCH;
                                res <= alu_o;
                                case(TTT)
                                3'd0:   // TEST
                                        begin
                                                pf <= pres;
                                                cf <= 1'b0;
                                                vf <= 1'b0;
                                                sf <= resn;
                                                zf <= resz;
                                        end
                                3'd2:   // NOT
                                        begin
                                                wrregs <= 1'b1;
                                        end
                                3'd3:   // NEG
                                        begin
                                                pf <= pres;
                                                af <= carry   (1'b1,1'b0,b[3],alu_o[3]);
                                                cf <= carry   (1'b1,1'b0,bmsb,resn);
                                                vf <= overflow(1'b1,1'b0,bmsb,resn);
                                                sf <= resn;
                                                zf <= resz;
                                                wrregs <= 1'b1;
                                        end
                                // Normally only a single register update is required, however with 
                                // multiply word both AX and DX need to be updated. So we bypass the
                                // regular update here.
                                3'd4:
                                        begin
                                                if (w) begin
                                                        ax <= p32[15:0];
                                                        dx <= p32[31:16];
                                                        cf <= p32[31:16]!=16'd0;
                                                        vf <= p32[31:16]!=16'd0;
                                                end
                                                else begin
                                                        ax <= p16;
                                                        cf <= p16[15:8]!=8'd0;
                                                        vf <= p16[15:8]!=8'd0;
                                                end
                                        end
                                3'd5:
                                        begin
                                                if (w) begin
                                                        ax <= wp[15:0];
                                                        dx <= wp[31:16];
                                                        cf <= p32[31:16]!=16'd0;
                                                        vf <= p32[31:16]!=16'd0;
                                                end
                                                else begin
                                                        ax <= p;
                                                        cf <= p[15:8]!=8'd0;
                                                        vf <= p[15:8]!=8'd0;
                                                end
                                        end
                                3'd6,3'd7:
                                        begin
                                                state <= DIVIDE1;
                                        end
                                default:        ;
                                endcase
                        end
 
                `INC_REG:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                vf <= overflow(1'b0,a[15],b[15],resnw);
                                sf <= resnw;
                                zf <= reszw;
                        end
                `DEC_REG:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                vf <= overflow(1'b1,a[15],b[15],resnw);
                                sf <= resnw;
                                zf <= reszw;
                        end
                `IMUL:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                rrr <= 3'd0;
                                res <= alu_o;
                                if (w) begin
                                        cf <= wp[31:16]!={16{resnw}};
                                        vf <= wp[31:16]!={16{resnw}};
                                        dx <= wp[31:16];
                                end
                                else begin
                                        cf <= ah!={8{resnb}};
                                        vf <= ah!={8{resnb}};
                                end
                        end
 
 
                //-----------------------------------------------------------------
                // Memory Operations
                //-----------------------------------------------------------------
 
                // registers not allowed on LEA
                // invalid opcode
                //
                `LEA:
                        begin
                                w <= 1'b1;
                                res <= ea;
                                if (mod==2'b11) begin
                                        int_num <= 8'h06;
                                        state <= INT;
                                end
                                else begin
                                        state <= IFETCH;
                                        wrregs <= 1'b1;
                                end
                        end
                `LDS:
                        begin
                                wrsregs <= 1'b1;
                                res <= alu_o;
                                rrr <= 3'd3;
                                state <= IFETCH;
                        end
                `LES:
                        begin
                                wrsregs <= 1'b1;
                                res <= alu_o;
                                rrr <= 3'd0;
                                state <= IFETCH;
                        end
 
                `MOV_RR8,`MOV_RR16,
                `MOV_MR,
                `MOV_M2AL,`MOV_M2AX,
                `MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
                `MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                res <= alu_o;
                        end
                `XCHG_MEM:
                        begin
                                wrregs <= 1'b1;
                                if (mod==2'b11) rrr <= rm;
                                res <= alu_o;
                                b <= rrro;
                                state <= mod==2'b11 ? IFETCH : XCHG_MEM;
                        end
                `MOV_I8M,`MOV_I16M:
                        begin
                                res <= alu_o;
                                state <= rrr==3'd0 ? STORE_DATA : INVALID_OPCODE;
                        end
 
                `MOV_S2R:
                        begin
                                w <= 1'b1;
                                rrr <= rm;
                                res <= b;
                                if (mod==2'b11) begin
                                        state <= IFETCH;
                                        wrregs <= 1'b1;
                                end
                                else
                                        state <= STORE_DATA;
                        end
                `MOV_R2S:
                        begin
                                wrsregs <= 1'b1;
                                res <= alu_o;
                                state <= IFETCH;
                        end
 
                `LODSB:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b0;
                                rrr <= 3'd0;
                                res <= a[7:0];
                                if ( df) si <= si_dec;
                                if (!df) si <= si_inc;
                        end
                `LODSW:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                rrr <= 3'd0;
                                res <= a;
                                if ( df) si <= si - 16'd2;
                                if (!df) si <= si + 16'd2;
                        end
 
                8'hD0,8'hD1,8'hD2,8'hD3,8'hC0,8'hC1:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                rrr <= rm;
                                if (w)
                                        case(rrr)
                                        3'b000: // ROL
                                                begin
                                                        res <= shlo[15:0]|shlo[31:16];
                                                        cf <= bmsb;
                                                        vf <= bmsb^b[14];
                                                end
                                        3'b001: // ROR
                                                begin
                                                        res <= shruo[15:0]|shruo[31:16];
                                                        cf <= b[0];
                                                        vf <= cf^b[15];
                                                end
                                        3'b010: // RCL
                                                begin
                                                        res <= shlco[16:1]|shlco[32:17];
                                                        cf <= b[15];
                                                        vf <= b[15]^b[14];
                                                end
                                        3'b011: // RCR
                                                begin
                                                        res <= shrcuo[15:0]|shrcuo[31:16];
                                                        cf <= b[0];
                                                        vf <= cf^b[15];
                                                end
                                        3'b100: // SHL
                                                begin
                                                        res <= shlo[15:0];
                                                        cf <= shlo[16];
                                                        vf <= b[15]^b[14];
                                                end
                                        3'b101: // SHR
                                                begin
                                                        res <= shruo[31:16];
                                                        cf <= shruo[15];
                                                        vf <= b[15];
                                                end
                                        3'b111: // SAR
                                                begin
                                                        res <= shro;
                                                        cf <= b[0];
                                                        vf <= 1'b0;
                                                end
                                        endcase
                                else
                                        case(rrr)
                                        3'b000: // ROL
                                                begin
                                                        res <= shlo8[7:0]|shlo8[15:8];
                                                        cf <= b[7];
                                                        vf <= b[7]^b[6];
                                                end
                                        3'b001: // ROR
                                                begin
                                                        res <= shruo8[15:8]|shruo8[7:0];
                                                        cf <= b[0];
                                                        vf <= cf^b[7];
                                                end
                                        3'b010: // RCL
                                                begin
                                                        res <= shlco8[8:1]|shlco8[16:9];
                                                        cf <= b[7];
                                                        vf <= b[7]^b[6];
                                                end
                                        3'b011: // RCR
                                                begin
                                                        res <= shrcuo8[15:8]|shrcuo8[7:0];
                                                        cf <= b[0];
                                                        vf <= cf^b[7];
                                                end
                                        3'b100: // SHL
                                                begin
                                                        res <= shlo8[7:0];
                                                        cf <= shlo8[8];
                                                        vf <= b[7]^b[6];
                                                end
                                        3'b101: // SHR
                                                begin
                                                        res <= shruo8[15:8];
                                                        cf <= shruo8[7];
                                                        vf <= b[7];
                                                end
                                        3'b111: // SAR
                                                begin
                                                        res <= shro8;
                                                        cf <= b[0];
                                                        vf <= 1'b0;
                                                end
                                        endcase
                        end
 
                //-----------------------------------------------------------------
                //-----------------------------------------------------------------
                `GRPFF:
                        begin
                                case(rrr)
                                3'b000:         // INC
                                        begin
                                                state <= IFETCH;
                                                wrregs <= 1'b1;
                                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                                vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
                                                w <= 1'b1;
                                                res <= alu_o;
                                                rrr <= rm;
                                                pf <= pres;
                                                sf <= resnw;
                                                zf <= reszw;
                                        end
                                3'b001:         // DEC
                                        begin
                                                state <= IFETCH;
                                                wrregs <= 1'b1;
                                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                                vf <= overflow(1'b1,a[15],b[15],alu_o[15]);
                                                w <= 1'b1;
                                                res <= alu_o;
                                                rrr <= rm;
                                                pf <= pres;
                                                sf <= resnw;
                                                zf <= reszw;
                                        end
                                3'b010: begin sp <= sp_dec; state <= CALL_IN; end
                                // These two should not be reachable here, as they would
                                // be trapped by the EACALC.
                                3'b011: state <= CALL_FIN;      // CALL FAR indirect
                                3'b101: // JMP FAR indirect
                                        begin
                                                ip <= offset;
                                                cs <= selector;
                                                state <= IFETCH;
                                        end
                                3'b110: begin sp <= sp_dec; state <= PUSH; end
                                default:
                                        begin
                                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                                vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
                                        end
                                endcase
                        end
 
                //-----------------------------------------------------------------
                //-----------------------------------------------------------------
                default:
                        state <= IFETCH;
                endcase
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2009,2010,2012 Robert Finch`
3			`// robfinch<remove>@opencores.org`
4			`//`
5			`// EXECUTE`
6			`// - execute instruction`
7			`//`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`//`
23			`// Verilog`
24			`//`
25			`// ============================================================================`
26			`//`
27			`EXECUTE:`
28			`begin`
29			`casex(ir)`
30
31			`EXTOP:
32			`casex(ir2)`
33			`LxDT: state <= FETCH_DESC;
34			`endcase`
35
36			`DAA:
37			`begin`
38			`state <= IFETCH;`
39			`end`
40
41			`ALU_I2R8,`ALU_I2R16,`ADD,`ADD_ALI8,`ADD_AXI16,`ADC,`ADC_ALI8,`ADC_AXI16:
42			`begin`
43			`state <= IFETCH;`
44			`wrregs <= 1'b1;`
45			`res <= alu_o;`
46			`pf <= pres;`
47			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
48			`cf <= carry (1'b0,amsb,bmsb,resn);`
49			`vf <= overflow(1'b0,amsb,bmsb,resn);`
50			`sf <= resn;`
51			`zf <= resz;`
52			`end`
53
54			`AND,`OR,`XOR,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`AND_AXI16,`OR_AXI16,`XOR_AXI16:
55			`begin`
56			`state <= IFETCH;`
57			`wrregs <= 1'b1;`
58			`res <= alu_o;`
59			`pf <= pres;`
60			`cf <= 1'b0;`
61			`vf <= 1'b0;`
62			`sf <= resn;`
63			`zf <= resz;`
64			`end`
65
66			`TEST:
67			`begin`
68			`state <= IFETCH;`
69			`res <= alu_o;`
70			`pf <= pres;`
71			`cf <= 1'b0;`
72			`vf <= 1'b0;`
73			`sf <= resn;`
74			`zf <= resz;`
75			`end`
76
77			`CMP,`CMP_ALI8,`CMP_AXI16:
78			`begin`
79			`state <= IFETCH;`
80			`pf <= pres;`
81			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
82			`cf <= carry (1'b1,amsb,bmsb,resn);`
83			`vf <= overflow(1'b1,amsb,bmsb,resn);`
84			`sf <= resn;`
85			`zf <= resz;`
86			`end`
87
88			`SBB,`SUB,`SBB_ALI8,`SUB_ALI8,`SBB_AXI16,`SUB_AXI16:
89			`begin`
90			`wrregs <= 1'b1;`
91			`state <= IFETCH;`
92			`res <= alu_o;`
93			`pf <= pres;`
94			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
95			`cf <= carry (1'b1,amsb,bmsb,resn);`
96			`vf <= overflow(1'b1,amsb,bmsb,resn);`
97			`sf <= resn;`
98			`zf <= resz;`
99			`end`
100
101			`8'hF6,8'hF7:`
102			`begin`
103			`state <= IFETCH;`
104	6	robfinch	`res <= alu_o;`
105			`case(TTT)`
106			`3'd0: // TEST`
107			`begin`
108			`pf <= pres;`
109			`cf <= 1'b0;`
110			`vf <= 1'b0;`
111			`sf <= resn;`
112			`zf <= resz;`
113			`end`
114			`3'd2: // NOT`
115			`begin`
116			`wrregs <= 1'b1;`
117			`end`
118			`3'd3: // NEG`
119			`begin`
120			`pf <= pres;`
121			`af <= carry (1'b1,1'b0,b[3],alu_o[3]);`
122			`cf <= carry (1'b1,1'b0,bmsb,resn);`
123			`vf <= overflow(1'b1,1'b0,bmsb,resn);`
124			`sf <= resn;`
125			`zf <= resz;`
126			`wrregs <= 1'b1;`
127			`end`
128			`// Normally only a single register update is required, however with`
129			`// multiply word both AX and DX need to be updated. So we bypass the`
130			`// regular update here.`
131			`3'd4:`
132			`begin`
133			`if (w) begin`
134			`ax <= p32[15:0];`
135			`dx <= p32[31:16];`
136			`cf <= p32[31:16]!=16'd0;`
137			`vf <= p32[31:16]!=16'd0;`
138			`end`
139			`else begin`
140			`ax <= p16;`
141			`cf <= p16[15:8]!=8'd0;`
142			`vf <= p16[15:8]!=8'd0;`
143			`end`
144			`end`
145			`3'd5:`
146			`begin`
147			`if (w) begin`
148			`ax <= wp[15:0];`
149			`dx <= wp[31:16];`
150			`cf <= p32[31:16]!=16'd0;`
151			`vf <= p32[31:16]!=16'd0;`
152			`end`
153			`else begin`
154			`ax <= p;`
155			`cf <= p[15:8]!=8'd0;`
156			`vf <= p[15:8]!=8'd0;`
157			`end`
158			`end`
159			`3'd6,3'd7:`
160			`begin`
161			`state <= DIVIDE1;`
162			`end`
163			`default: ;`
164	2	robfinch	`endcase`
165			`end`
166	6	robfinch
167	2	robfinch	`INC_REG:
168			`begin`
169			`state <= IFETCH;`
170			`wrregs <= 1'b1;`
171			`w <= 1'b1;`
172			`res <= alu_o;`
173			`pf <= pres;`
174			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
175			`vf <= overflow(1'b0,a[15],b[15],resnw);`
176			`sf <= resnw;`
177			`zf <= reszw;`
178			`end`
179			`DEC_REG:
180			`begin`
181			`state <= IFETCH;`
182			`wrregs <= 1'b1;`
183			`w <= 1'b1;`
184			`res <= alu_o;`
185			`pf <= pres;`
186			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
187			`vf <= overflow(1'b1,a[15],b[15],resnw);`
188			`sf <= resnw;`
189			`zf <= reszw;`
190			`end`
191			`IMUL:
192			`begin`
193			`state <= IFETCH;`
194			`wrregs <= 1'b1;`
195			`w <= 1'b1;`
196			`rrr <= 3'd0;`
197			`res <= alu_o;`
198			`if (w) begin`
199			`cf <= wp[31:16]!={16{resnw}};`
200			`vf <= wp[31:16]!={16{resnw}};`
201			`dx <= wp[31:16];`
202			`end`
203			`else begin`
204			`cf <= ah!={8{resnb}};`
205			`vf <= ah!={8{resnb}};`
206			`end`
207			`end`
208
209
210			`//-----------------------------------------------------------------`
211			`// Memory Operations`
212			`//-----------------------------------------------------------------`
213
214			`// registers not allowed on LEA`
215			`// invalid opcode`
216			`//`
217			`LEA:
218			`begin`
219			`w <= 1'b1;`
220			`res <= ea;`
221			`if (mod==2'b11) begin`
222			`int_num <= 8'h06;`
223			`state <= INT;`
224			`end`
225			`else begin`
226			`state <= IFETCH;`
227			`wrregs <= 1'b1;`
228			`end`
229			`end`
230			`LDS:
231			`begin`
232			`wrsregs <= 1'b1;`
233			`res <= alu_o;`
234			`rrr <= 3'd3;`
235			`state <= IFETCH;`
236			`end`
237			`LES:
238			`begin`
239			`wrsregs <= 1'b1;`
240			`res <= alu_o;`
241			`rrr <= 3'd0;`
242			`state <= IFETCH;`
243			`end`
244
245			`MOV_RR8,`MOV_RR16,
246			`MOV_MR,
247			`MOV_M2AL,`MOV_M2AX,
248			`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
249			`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
250			`begin`
251			`state <= IFETCH;`
252			`wrregs <= 1'b1;`
253			`res <= alu_o;`
254			`end`
255			`XCHG_MEM:
256			`begin`
257			`wrregs <= 1'b1;`
258			`if (mod==2'b11) rrr <= rm;`
259			`res <= alu_o;`
260			`b <= rrro;`
261			`state <= mod==2'b11 ? IFETCH : XCHG_MEM;`
262			`end`
263			`MOV_I8M,`MOV_I16M:
264			`begin`
265			`res <= alu_o;`
266			`state <= rrr==3'd0 ? STORE_DATA : INVALID_OPCODE;`
267			`end`
268
269			`MOV_S2R:
270			`begin`
271			`w <= 1'b1;`
272			`rrr <= rm;`
273			`res <= b;`
274			`if (mod==2'b11) begin`
275			`state <= IFETCH;`
276			`wrregs <= 1'b1;`
277			`end`
278			`else`
279			`state <= STORE_DATA;`
280			`end`
281			`MOV_R2S:
282			`begin`
283			`wrsregs <= 1'b1;`
284			`res <= alu_o;`
285			`state <= IFETCH;`
286			`end`
287
288			`LODSB:
289			`begin`
290			`state <= IFETCH;`
291			`wrregs <= 1'b1;`
292			`w <= 1'b0;`
293			`rrr <= 3'd0;`
294			`res <= a[7:0];`
295			`if ( df) si <= si_dec;`
296			`if (!df) si <= si_inc;`
297			`end`
298			`LODSW:
299			`begin`
300			`state <= IFETCH;`
301			`wrregs <= 1'b1;`
302			`w <= 1'b1;`
303			`rrr <= 3'd0;`
304			`res <= a;`
305			`if ( df) si <= si - 16'd2;`
306			`if (!df) si <= si + 16'd2;`
307			`end`
308
309			`8'hD0,8'hD1,8'hD2,8'hD3,8'hC0,8'hC1:`
310			`begin`
311			`state <= IFETCH;`
312			`wrregs <= 1'b1;`
313	5	robfinch	`rrr <= rm;`
314	2	robfinch	`if (w)`
315			`case(rrr)`
316			`3'b000: // ROL`
317			`begin`
318	4	robfinch	`res <= shlo[15:0]\|shlo[31:16];`
319	2	robfinch	`cf <= bmsb;`
320			`vf <= bmsb^b[14];`
321			`end`
322			`3'b001: // ROR`
323			`begin`
324	4	robfinch	`res <= shruo[15:0]\|shruo[31:16];`
325	2	robfinch	`cf <= b[0];`
326			`vf <= cf^b[15];`
327			`end`
328			`3'b010: // RCL`
329			`begin`
330	4	robfinch	`res <= shlco[16:1]\|shlco[32:17];`
331	2	robfinch	`cf <= b[15];`
332			`vf <= b[15]^b[14];`
333			`end`
334			`3'b011: // RCR`
335			`begin`
336	4	robfinch	`res <= shrcuo[15:0]\|shrcuo[31:16];`
337	2	robfinch	`cf <= b[0];`
338			`vf <= cf^b[15];`
339			`end`
340			`3'b100: // SHL`
341			`begin`
342	4	robfinch	`res <= shlo[15:0];`
343			`cf <= shlo[16];`
344	2	robfinch	`vf <= b[15]^b[14];`
345			`end`
346			`3'b101: // SHR`
347			`begin`
348	4	robfinch	`res <= shruo[31:16];`
349			`cf <= shruo[15];`
350	2	robfinch	`vf <= b[15];`
351			`end`
352			`3'b111: // SAR`
353			`begin`
354	4	robfinch	`res <= shro;`
355	2	robfinch	`cf <= b[0];`
356			`vf <= 1'b0;`
357			`end`
358			`endcase`
359			`else`
360			`case(rrr)`
361			`3'b000: // ROL`
362			`begin`
363	4	robfinch	`res <= shlo8[7:0]\|shlo8[15:8];`
364	2	robfinch	`cf <= b[7];`
365			`vf <= b[7]^b[6];`
366			`end`
367			`3'b001: // ROR`
368			`begin`
369	4	robfinch	`res <= shruo8[15:8]\|shruo8[7:0];`
370	2	robfinch	`cf <= b[0];`
371			`vf <= cf^b[7];`
372			`end`
373			`3'b010: // RCL`
374			`begin`
375	4	robfinch	`res <= shlco8[8:1]\|shlco8[16:9];`
376	2	robfinch	`cf <= b[7];`
377			`vf <= b[7]^b[6];`
378			`end`
379			`3'b011: // RCR`
380			`begin`
381	4	robfinch	`res <= shrcuo8[15:8]\|shrcuo8[7:0];`
382	2	robfinch	`cf <= b[0];`
383			`vf <= cf^b[7];`
384			`end`
385			`3'b100: // SHL`
386			`begin`
387	4	robfinch	`res <= shlo8[7:0];`
388			`cf <= shlo8[8];`
389	2	robfinch	`vf <= b[7]^b[6];`
390			`end`
391			`3'b101: // SHR`
392			`begin`
393	4	robfinch	`res <= shruo8[15:8];`
394			`cf <= shruo8[7];`
395	2	robfinch	`vf <= b[7];`
396			`end`
397			`3'b111: // SAR`
398			`begin`
399	4	robfinch	`res <= shro8;`
400	2	robfinch	`cf <= b[0];`
401			`vf <= 1'b0;`
402			`end`
403			`endcase`
404			`end`
405
406			`//-----------------------------------------------------------------`
407			`//-----------------------------------------------------------------`
408			`GRPFF:
409			`begin`
410			`case(rrr)`
411			`3'b000: // INC`
412			`begin`
413			`state <= IFETCH;`
414			`wrregs <= 1'b1;`
415			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
416			`vf <= overflow(1'b0,a[15],b[15],alu_o[15]);`
417			`w <= 1'b1;`
418			`res <= alu_o;`
419			`rrr <= rm;`
420			`pf <= pres;`
421			`sf <= resnw;`
422			`zf <= reszw;`
423			`end`
424			`3'b001: // DEC`
425			`begin`
426			`state <= IFETCH;`
427			`wrregs <= 1'b1;`
428			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
429			`vf <= overflow(1'b1,a[15],b[15],alu_o[15]);`
430			`w <= 1'b1;`
431			`res <= alu_o;`
432			`rrr <= rm;`
433			`pf <= pres;`
434			`sf <= resnw;`
435			`zf <= reszw;`
436			`end`
437			`3'b010: begin sp <= sp_dec; state <= CALL_IN; end`
438			`// These two should not be reachable here, as they would`
439			`// be trapped by the EACALC.`
440			`3'b011: state <= CALL_FIN; // CALL FAR indirect`
441			`3'b101: // JMP FAR indirect`
442			`begin`
443			`ip <= offset;`
444			`cs <= selector;`
445			`state <= IFETCH;`
446			`end`
447			`3'b110: begin sp <= sp_dec; state <= PUSH; end`
448			`default:`
449			`begin`
450			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
451			`vf <= overflow(1'b0,a[15],b[15],alu_o[15]);`
452			`end`
453			`endcase`
454			`end`
455
456			`//-----------------------------------------------------------------`
457			`//-----------------------------------------------------------------`
458			`default:`
459			`state <= IFETCH;`
460			`endcase`
461			`end`
462

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