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[/] [rtfsimpleuart/] [trunk/] [rtl/] [verilog/] [rtfSimpleUartRx.v] - Blame information for rev 14

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// ============================================================================
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//      (C) 2011,2013  Robert Finch
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//  All rights reserved.
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//      robfinch@<remove>finitron.ca
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//
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//      rtfSimpleUartRx.v
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the <organization> nor the
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//       names of its contributors may be used to endorse or promote products
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//       derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//      Simple UART receiver core
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//              Features:
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//                      false start bit detection
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//                      framing error detection
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//                      overrun state detection
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//                      resynchronization on every character
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//                      fixed format 1 start - 8 data - 1 stop bits
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//                      uses 16x clock rate
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//                      
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//              This core may be used as a standalone peripheral
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//      on a SoC bus if all that is desired is recieve
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//      capability. It requires a 16x baud rate clock.
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//      
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |WISHBONE Datasheet
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//      |WISHBONE SoC Architecture Specification, Revision B.3
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//      |
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//      |Description:                                           Specifications:
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |General Description:                           simple serial UART receiver
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |Supported Cycles:                                      SLAVE,READ
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//      |                                                                       SLAVE,BLOCK READ
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |Data port, size:                                       8 bit
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//      |Data port, granularity:                        8 bit
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//      |Data port, maximum operand size:       8 bit
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//      |Data transfer ordering:                        Undefined
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//      |Data transfer sequencing:                      Undefined
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |Clock frequency constraints:           none
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |Supported signal list and                      Signal Name             WISHBONE equiv.
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//      |cross reference to equivalent          ack_o                   ACK_O
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//      |WISHBONE signals                                       
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//      |                                                                       clk_i                   CLK_I
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//      |                                   rst_i           RST_I
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//      |                                                                       dat_o(7:0)              DAT_O()
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//      |                                                                       cyc_i                   CYC_I
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//      |                                                                       stb_i                   STB_I
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//      |                                                                       we_i                    WE_I
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//      |
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |Special requirements:
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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//      Ref: Spartan3 -4
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//      27 LUTs / 24 slices / 170 MHz
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//==============================================================================
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`define IDLE    0
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`define CNT             1
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module rtfSimpleUartRx(
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        // WISHBONE SoC bus interface
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        input rst_i,                    // reset
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        input clk_i,                    // clock
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        input cyc_i,                    // cycle is valid
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        input stb_i,                    // strobe
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        output ack_o,                   // data is ready
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        input we_i,                             // write (this signal is used to qualify reads)
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        output [7:0] dat_o,              // data out
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        //------------------------
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        input cs_i,                             // chip select
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        input baud16x_ce,               // baud rate clock enable
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    input tri0 baud8x,       // switches to mode baudX8
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        input clear,                    // clear reciever
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        input rxd,                              // external serial input
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        output reg data_present,        // data present in fifo
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        output reg frame_err,           // framing error
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        output reg overrun                      // receiver overrun
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);
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//0 - simple sampling at middle of symbol period
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//>0 - sampling of 3 middle ticks of sumbol perion and results as majority
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parameter SamplerStyle = 0;
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// variables
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reg [7:0] cnt;                   // sample bit rate counter
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reg [9:0] rx_data;               // working receive data register
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reg state;                              // state machine
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reg wf;                                 // buffer write
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reg [7:0] dat;
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wire isX8;
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buf(isX8, baud8x);
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reg modeX8;
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assign ack_o = cyc_i & stb_i & cs_i;
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assign dat_o = ack_o ? dat : 8'b0;
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// update data register
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always @(posedge clk_i)
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        if (wf) dat <= rx_data[8:1];
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// on a read clear the data present status
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// but set the status when the data register
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// is updated by the receiver           
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always @(posedge clk_i)
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    if (rst_i)
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        data_present <= 0;
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    else if (wf)
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        data_present <= 1;
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        else if (ack_o & ~we_i) data_present <= 0;
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// Three stage synchronizer to synchronize incoming data to
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// the local clock (avoids metastability).
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reg [5:0] rxdd          /* synthesis ramstyle = "logic" */; // synchronizer flops
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reg rxdsmp;             // majority samples
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reg rdxstart;           // for majority style sample solid 3tik-wide sample
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reg [1:0] rxdsum;
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always @(posedge clk_i)
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if (baud16x_ce) begin
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        rxdd <= {rxdd[4:0],rxd};
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    if (SamplerStyle == 0) begin
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        rxdsmp <= rxdd[3];
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        rdxstart <= rxdd[4]&~rxdd[3];
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    end
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    else begin
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        rxdsum[1] <= rxdsum[0];
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        rxdsum[0] <= {1'b0,rxdd[3]} + {1'b0,rxdd[4]} + {1'b0,rxdd[5]};
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        rxdsmp <= rxdsum[1];
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        rdxstart <= (rxdsum[0] == 2'b00) & ((rxdsum[1] == 2'b11));
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    end
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end
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`define CNT_FRAME  (8'h97)
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`define CNT_FINISH (8'h9D)
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always @(posedge clk_i) begin
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        if (rst_i) begin
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                state <= `IDLE;
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                wf <= 1'b0;
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                overrun <= 1'b0;
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        frame_err <= 1'b0;
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        end
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        else begin
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                // Clear write flag
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                wf <= 1'b0;
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                if (clear) begin
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                        wf <= 1'b0;
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                        state <= `IDLE;
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                        overrun <= 1'b0;
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            frame_err <= 1'b0;
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                end
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                else if (baud16x_ce) begin
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                        case (state)
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                        // Sit in the idle state until a start bit is
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                        // detected.
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                        `IDLE:
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                                // look for start bit
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                                if (rdxstart)
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                                        state <= `CNT;
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                        `CNT:
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                                begin
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                                        // End of the frame ?
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                                        // - check for framing error
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                                        // - write data to read buffer
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                                        if (cnt==`CNT_FRAME)
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                                                begin
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                                                        frame_err <= ~rxdsmp;
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                            overrun <= data_present;
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                                                        if (!data_present)
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                                                                wf <= 1'b1;
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                            state <= `IDLE;
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                                                end
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                                        // Switch back to the idle state a little
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                                        // bit too soon.
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                                        //if (cnt==`CNT_FINISH) begin
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                                        //      state <= `IDLE;
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                    //end
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                                        // On start bit check make sure the start
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                                        // bit is low, otherwise go back to the
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                                        // idle state because it's a false start.
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                                        if (cnt==8'h07 && rxdsmp)
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                                                state <= `IDLE;
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                                        if (cnt[3:0]==4'h7)
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                                                rx_data <= {rxdsmp,rx_data[9:1]};
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                                end
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                        endcase
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                end
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        end
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end
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// bit rate counter
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always @(posedge clk_i)
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        if (baud16x_ce) begin
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                if (state == `IDLE) begin
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                        cnt <= modeX8;
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            modeX8 <= isX8;
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        end
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        else begin
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            cnt[7:1] <= cnt[7:1] + cnt[0];
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            cnt[0] <= ~cnt[0] | (modeX8);
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        end
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        end
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endmodule
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