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[/] [rtftextcontroller/] [trunk/] [rtl/] [verilog/] [FT_VIC.v] - Blame information for rev 28

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1 28 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2017  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
6
//       ||
7
//
8
//
9
//      FT_VIC.v
10
//
11
// This source file is free software: you can redistribute it and/or modify 
12
// it under the terms of the GNU Lesser General Public License as published 
13
// by the Free Software Foundation, either version 3 of the License, or     
14
// (at your option) any later version.                                      
15
//                                                                          
16
// This source file is distributed in the hope that it will be useful,      
17
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
18
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
19
// GNU General Public License for more details.                             
20
//                                                                          
21
// You should have received a copy of the GNU General Public License        
22
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
23
//                                                                          
24
//
25
// ============================================================================
26
 
27
`define TRUE    1'b1
28
`define FALSE   1'b0
29
`define HIGH    1'b1
30
`define LOW             1'b0
31
 
32
`define M0X             7'h00
33
`define M0Y             7'h01
34
`define M1X             7'h02
35
`define M1Y             7'h03
36
`define M2X             7'h04
37
`define M2Y             7'h05
38
`define M3X             7'h06
39
`define M3Y             7'h07
40
`define M4X             7'h08
41
`define M4Y             7'h09
42
`define M5X             7'h0A
43
`define M5Y             7'h0B
44
`define M6X             7'h0C
45
`define M6Y             7'h0D
46
`define M7X             7'h0E
47
`define M7Y             7'h0F
48
`define M8X             7'h10
49
`define M8Y             7'h11
50
`define M9X             7'h12
51
`define M9Y             7'h13
52
`define M10X    7'h14
53
`define M10Y    7'h15
54
`define M11X    7'h16
55
`define M11Y    7'h17
56
`define RASTER  7'h18
57
`define LPX             7'h19
58
`define LPY             7'h1A
59
`define SE              7'h1B
60
`define CTRL1   7'h1C
61
`define SYE             7'h1D
62
`define MEMPTR  7'h1E
63
`define IRQ             7'h1F
64
`define IRQEN   7'h20
65
`define MXE             7'h23
66
`define MMC             7'h24
67
`define MDC             7'h25
68
`define EC              7'h27
69
`define M0C1    7'h28
70
`define M1C1    7'h29
71
`define M2C1    7'h2A
72
`define M3C1    7'h2B
73
`define M4C1    7'h2C
74
`define M5C1    7'h2D
75
`define M6C1    7'h2E
76
`define M7C1    7'h2F
77
`define M8C1    7'h30
78
`define M9C1    7'h31
79
`define M10C1   7'h32
80
`define M11C1   7'h33
81
`define M0C2    7'h34
82
`define M1C2    7'h35
83
`define M2C2    7'h36
84
`define M3C2    7'h37
85
`define M4C2    7'h38
86
`define M5C2    7'h39
87
`define M6C2    7'h3A
88
`define M7C2    7'h3B
89
`define M8C2    7'h3C
90
`define M9C2    7'h3D
91
`define M10C2   7'h3E
92
`define M11C2   7'h3F
93
 
94
module FT_VIC(
95
        ws_rst_i, ws_clk_i, ws_cyc_i, ws_stb_i, ws_ack_o, ws_we_i, ws_adr_i, ws_dat_i, ws_dat_o,
96
        cs_i, rdy_o, irq_o,
97
        v_clk_i, v_adr_o, v_dat_i,
98
        rst,
99
        hSync, vSync, color_o,
100
        lp_n
101
);
102
parameter MIBCNT = 12;
103
parameter VIC_IDLE = 0;   // idle cycle
104
parameter VIC_SPRITE_PTR = 1;
105
parameter VIC_SPRITE_PTR2 = 2;
106
parameter VIC_SPRITE = 2; // sprite cycle
107
parameter VIC_CHAR = 3;  // character acccess cycle
108
parameter VIC_CHAR2 = 4;
109
parameter VIC_CHAR_BMP = 5;
110
parameter VIC_BMP1 = 3;
111
parameter VIC_BMP2 = 4;
112
parameter VIC_BMP3 = 6;
113
parameter VIC_BMP4 = 7;
114
 
115
parameter phSyncOn  = 8;                //   8 front porch
116
parameter phSyncOff = 104;              //  96 sync
117
parameter phBlankOff = 144;             //  40 back porch
118
parameter phBorderOff = 152;    //   8 border
119
parameter phBorderOn = 792;             // 640 display
120
parameter phBorderOff2 = 168;
121
parameter phBorderOn2 = 776;
122
parameter phBlankOn = 800;              //    8 border
123
parameter phTotal = 800;                // 800 total clocks
124
//
125
parameter pvSyncOn  = 5;                //    5 front porch
126
parameter pvSyncOff = 7;                //    2 vertical sync
127
parameter pvBlankOff = 35;              //   28 back porch
128
parameter pvBorderOff = 42;             //    7 border  0
129
parameter pvBorderOn = 442;             //  400 display
130
parameter pvBorderOff2 = 50;
131
parameter pvBorderOn2 = 434;
132
parameter pvBlankOn = 449;      //    7 border  0
133
parameter pvTotal = 449;                //  449 total scan lines
134
 
135
input ws_rst_i;
136
input ws_clk_i;
137
input ws_cyc_i;
138
input ws_stb_i;
139
output ws_ack_o;
140
input ws_we_i;
141
input [7:0] ws_adr_i;
142
input [15:0] ws_dat_i;
143
output [15:0] ws_dat_o;
144
input cs_i;
145
output rdy_o;
146
output irq_o;
147
 
148
input v_clk_i;
149
output [19:0] v_adr_o;
150
input [31:0] v_dat_i;
151
 
152
input rst;
153
output hSync;
154
output vSync;
155
input lp_n;
156
 
157
integer n,i;
158
 
159
wire cs = ws_cyc_i & ws_stb_i & cs_i;
160
reg rdy;
161
always @(posedge ws_clk_i)
162
        rdy <= cs;
163
assign ws_ack_o = cs ? rdy : 1'b0;
164
assign rdy_o = cs ? rdy : 1'b1;
165
 
166
wire badline;
167
reg [3:0] vicCycle;
168
reg [3:0] sprite;
169
reg [13:0] vmndx;                        // video matrix index
170
reg [19:0] bmndx;                                        // bitmap mode index
171
reg [31:0] nextChar;
172
reg [31:0] charbuf [78:0];
173
reg [31:0] bmpData;
174
reg [2:0] scanline;
175
reg [MIBCNT-1:0] MActive;
176
reg MPtr [10:0];
177
reg [8:0] MCnt [0:MIBCNT-1];
178
reg [8:0] mx [0:MIBCNT-1];
179
reg [7:0] my [0:MIBCNT-1];
180
reg [7:0] mtc [0:MIBCNT-1];
181
reg [7:0] mc1 [0:MIBCNT-1];
182
reg [7:0] mc2 [0:MIBCNT-1];
183
reg [7:0] mc3 [0:MIBCNT-1];
184
reg [MIBCNT-1:0] me;
185
reg [MIBCNT-1:0] mye, mye_ff;
186
reg [MIBCNT-1:0] mxe, mxe_ff;
187
reg [MIBCNT-1:0] mdp;
188
reg [MIBCNT-1:0] MShift;
189
reg [95:0] MPixels [MIBCNT-1:0];
190
reg [1:0] MCurrentPixel [MIBCNT-1:0];
191
reg [MIBCNT-1:0] m2m, m2d;
192
reg m2mhit, m2dhit;
193
reg [19:0] cb;
194
reg [19:0] vm;
195
reg [19:0] bma;
196
reg [7:0] regno;
197
 
198
// Interrupt bits
199
reg irst;
200
reg ilp;
201
reg immc;
202
reg imbc;
203
 
204
reg irst_clr;
205
reg imbc_clr;
206
reg immc_clr;
207
reg ilp_clr;
208
reg irq_clr;
209
 
210
reg erst;
211
reg embc;
212
reg emmc;
213
reg elp;
214
 
215
assign irq = (ilp & elp) | (immc & emmc) | (imbc & embc) | (irst & erst);
216
assign irq_o = irq;
217
 
218
reg rasterIRQDone;
219
reg [9:0] rasterCmp;
220
 
221
wire [9:0] hCtr, vCtr;
222
reg rsel,csel;
223
reg [2:0] xscroll,yscroll;
224
 
225
//------------------------------------------------------------------------------
226
// Set the memory access cycle type
227
//------------------------------------------------------------------------------
228
 
229
always @(hCtr)
230
begin
231
        if (hCtr >= 10'd0 && hCtr < 10'd096)
232
                case(hCtr[2:0])
233
                3'b001: vicCycle <= VIC_SPRITE_PTR;
234
                3'b010: vicCycle <= VIC_SPRITE_PTR2;
235
                3'b011: vicCycle <= VIC_SPRITE_DAT;
236
                3'b100: vicCycle <= VIC_SPRITE_DAT;
237
                3'b101: vicCycle <= VIC_SPRITE_DAT;
238
                default:                        vicCycle <= VIC_IDLE;
239
                endcase
240
        else if (hCtr >= 10'd144 && hCtr < 10'd784)
241
                case(hCtr[2:0])
242
                3'b000: vicCycle <= (bmm || badline) ? VIC_CHAR : VIC_IDLE;
243
                3'b001: vicCycle <= (bmm || badline) ? VIC_CHAR2 : VIC_IDLE;
244
                3'b010: vicCycle <= !bmm ? VIC_CHAR_BMP : VIC_IDLE;
245
                3'b011: vicCycle <= !bmm ? VIC_CHAR_BMP2 : VIC_IDLE;
246
                3'b100: vicCycle <= bmm ? VIC_BMP3 : VIC_IDLE;
247
                3'b101: vicCycle <= bmm ? VIC_BMP4 : VIC_IDLE;
248
                3'b110: vicCycle <= VIC_IDLE;
249
                3'b111: vicCycle <= VIC_IDLE;
250
                endcase
251
        else
252
                vicCycle <= VIC_IDLE;
253
end
254
 
255
always @(posedge v_clk_i)
256
case(hCtr)
257
10'd008: sprite <= 4'd1;
258
10'd016: sprite <= 4'd2;
259
10'd024: sprite <= 4'd3;
260
10'd032: sprite <= 4'd4;
261
10'd040: sprite <= 4'd5;
262
10'd048: sprite <= 4'd6;
263
10'd056: sprite <= 4'd7;
264
10'd064: sprite <= 4'd8;
265
10'd072: sprite <= 4'd9;
266
10'd080: sprite <= 4'd10;
267
10'd088: sprite <= 4'd11;
268
default:        sprite <= 4'h0;
269
endcase
270
 
271
//------------------------------------------------------------------------------
272
//------------------------------------------------------------------------------
273
 
274
assign badline = vCtr[2:0]==yscroll && den && (vCtr >= (SIM ? 12'd1 : pvBlankOff) && vCtr <= pvBlankOn);
275
 
276
//------------------------------------------------------------------------------
277
// Databus loading
278
//------------------------------------------------------------------------------
279
 
280
always @(posedge v_clk_i)
281
begin
282
        case(vicCycle)
283
        VIC_SPRITE_PTR2:
284
                MPtr <= v_dat_i[19:9];
285
        VIC_CHAR:
286
                begin
287
                        waitingPixels <= readPixels;
288
                        waitingChar <= readChar;
289
                end
290
        VIC_CHAR2:      // also VIC_BMP2
291
                begin
292
                        bmpData <= v_dat_i;
293
                        if (badline)
294
                                nextChar <= v_dat_i;
295
                        else
296
                                nextChar <= charbuf[78];
297
                        for (n = 78; n > 0; n = n -1)
298
                                charbuf[n] = charbuf[n-1];
299
                        charbuf[0] <= nextChar;
300
                end
301
        VIC_CHAR_BMP2:
302
                begin
303
                        case(scanline[1:0])
304
                        2'd0:   readPixels <= v_dat_i[7:0];
305
                        2'd1:   readPixels <= v_dat_i[15:8];
306
                        2'd2:   readPixels <= v_dat_i[23:16];
307
                        2'd3:   readPixels <= v_dat_i[31:24];
308
                        endcase
309
                        readChar <= nextChar;
310
                end
311
        VIC_BMP4:
312
                bmpData <= v_dat_i;
313
        default:        ;
314
        endcase
315
end
316
 
317
//------------------------------------------------------------------------------
318
// Video matrix counter
319
//------------------------------------------------------------------------------
320
reg [13:0] vmndxStart;
321
 
322
always @(posedge v_clk_i)
323
if (rst) begin
324
  vmndx <= 14'd0;
325
  vmndxStart <= 14'd0;
326
end
327
else begin
328
        if (vCtr==pVTotal)
329
                vmndx <= 10'd0;
330
        if (vicCycle==VIC_CHAR && badline)
331
                vmndx <= vmndx + 14'd4;
332
        if (hCtr==10'd120) begin
333
                if (scanline==3'd7)
334
                        vmndxStart <= vmndx;
335
                else
336
                        vmndx <= vmndxStart;
337
        end
338
end
339
 
340
//------------------------------------------------------------------------------
341
// Scanline counter
342
//
343
// The scanline counter provides the three LSB's of the character bitmap data.
344
//------------------------------------------------------------------------------
345
 
346
always @(posedge v_clk_i)
347
if (rst)
348
        scanline <= 3'd0;
349
else begin
350
        if (hCtr==10'd128) begin
351
                if (badline)
352
                        scanline <= 3'd0;
353
                else
354
                        scanline <= scanline + 3'd1;
355
        end
356
end
357
 
358
//------------------------------------------------------------------------------
359
// Bitmapped mode counter.
360
//------------------------------------------------------------------------------
361
 
362
always @(posedge v_clk_i)
363
if (rst)
364
        bmndx <= 20'd0;
365
else begin
366
        if (vCtr < pvBlankOn)
367
                bmndx = bma;
368
        else begin
369
                if (hCtr > phBlankOff && hCtr <= phBlankOn)
370
                        bmndx <= bmndx + 20'd4;
371
        end
372
end
373
 
374
//------------------------------------------------------------------------------
375
// Collision detect logic.
376
//------------------------------------------------------------------------------
377
 
378
always @*
379
  for (n = 0; n < MIBCNT; n = n + 1)
380
    MActive[n] <= MCnt[n] != 9'd504;
381
 
382
reg [MIBCNT-1:0] collision;
383
always @*
384
  for (n = 0; n < MIBCNT; n = n + 1)
385
    collision[n] = MCurrentPixel[n]!=2'h0;
386
 
387
// Sprite-sprite collision logic
388
always @(posedge v_clk_i)
389
if (rst)
390
        m2mhit <= `FALSE;
391
else begin
392
        if (immc_clr)
393
                immc <= `FALSE;
394
        if (ws_adr_i[7:0]==7'h48 && cs) begin
395
                m2m[11:0] <= 12'h000;
396
                m2mhit <= `FALSE;
397
        end
398
        case(collision)
399
        12'b000000000000,
400
        12'b000000000001,
401
        12'b000000000010,
402
        12'b000000000100,
403
        12'b000000001000,
404
        12'b000000010000,
405
        12'b000000100000,
406
        12'b000001000000,
407
        12'b000010000000,
408
        12'b000100000000,
409
        12'b001000000000,
410
        12'b010000000000,
411
        12'b100000000000,
412
        ;
413
        default:
414
        begin
415
                m2m <= m2m | collision;
416
                if (!m2mhit) begin
417
                        immc <= `TRUE;
418
                        m2mhit <= `TRUE;
419
                end
420
        end
421
        endcase
422
end
423
 
424
// Sprite-background collision logic
425
always @(posedge v_clk_i)
426
if (rst)
427
        m2dhit <= `FALSE;
428
else begin
429
        if (imbc_clr)
430
                imbc <= `FALSE;
431
        if (ws_adr_i[7:0]==7'h4A && cs) begin
432
                m2d[MIBCNT-1:0] <= 12'h0;
433
                m2dhit <= `FALSE;
434
        end
435
        for (n = 0; n < MIBCNT; n = n + 1) begin
436
                if (collision[n] & pixelBgFlag & ~border) begin
437
                        m2d[n] <= `TRUE;
438
                        if (!m2dhit) begin
439
                                m2dhit <= `TRUE;
440
                                imbc <= `TRUE;
441
                        end
442
                end
443
        end
444
end
445
 
446
//------------------------------------------------------------------------------
447
//------------------------------------------------------------------------------
448
 
449
always @(posedge v_clk_i)
450
begin
451
        for (n = 0; n < MIBCNT; n = n + 1) begin
452
                if (hCtr == 10'd10)
453
                        MShift[n] <= `FALSE;
454
                else if (hCtr == mx[n])
455
                        MShift[n] <= `TRUE;
456
        end
457
end
458
 
459
//------------------------------------------------------------------------------
460
// Manage MCnt and sprite Y expansion.
461
//------------------------------------------------------------------------------
462
 
463
always @(posedge v_clk_i)
464
if (rst & SIM) begin
465
        for (n = 0; n < MIBCNT; n = n + 1) begin
466
                MCnt[n] <= 9'd504;
467
        end
468
end
469
else begin
470
        // Trigger sprite accesses
471
        // if the sprite Y coordinate matches.
472
        if (hCtr==10'd120) begin
473
                for (n = 0; n < MIBCNT; n = n + 1) begin
474
                        if (!MActive[n] && me[n] && vCtr == my[n])
475
                                MCnt[n] <= 9'd000;
476
                end
477
        end
478
 
479
        // Reset expansion flipflop once sprite becomes deactivated or
480
        // if no sprite Y expansion.
481
        for (n = 0; n < MIBCNT; n = n + 1) begin
482
                if (!mye[n] || !MActive[n])
483
                        mye_ff[n] <= 1'b0;
484
        end
485
 
486
        // If Y expansion is on, backup the MIB data counter by twelve every
487
        // other scanline.
488
        if (hCtr==phTotal) begin
489
                for (n = 0; n < MIBCNT; n = n + 1) begin
490
                        if (MActive[n] & mye[n]) begin
491
                                mye_ff[n] <= !mye_ff[n];
492
                                if (!mye_ff[n])
493
                                        MCnt[n] <= MCnt[n] - 9'd12;
494
                        end
495
                end
496
        end
497
 
498
        if (vicCycle==VIC_SPRITE) begin
499
                if (MActive[sprite])
500
                        MCnt[sprite] <= MCnt[sprite] + 9'd4;
501
        end
502
end
503
 
504
reg [3:0] sprdat;
505
 
506
always @(posedge v_clk_i)
507
begin
508
        for (n = 0; n < MIBCNT; n = n + 1) begin
509
                if (MShift[n]) begin
510
                        mxe_ff[n] <= !mxe_ff[n] & mxe[n];
511
                        if (!mxe_ff[n]) begin
512
                                MCurrentPixel[n] <= MPixels[n][95:94];
513
                                MPixels[n] <= {MPixels[n][93:0],2'h0};
514
                        end
515
                end
516
                else begin
517
                        mxe_ff[n] <= 1'b0;
518
                        MCurrentPixel[n] <= 2'h0;
519
                end
520
        end
521
        if (vicCycle==VIC_SPRITE_PTR2)
522
                sprdat <= 4'b0111;
523
        else
524
                sprdat <= {sprdat[2:0],1'b0};
525
        if (sprdat[3]) begin
526
                if (MActive[sprite])
527
                        MPixels[sprite] <= {MPixels[sprite][63:0],v_dat_i};
528
        end
529
end
530
 
531
//------------------------------------------------------------------------------
532
// Address Generation
533
//------------------------------------------------------------------------------
534
 
535
always @(posedge v_clk_i)
536
begin
537
        v_adr_o <= 20'hFFFFC;
538
        if (bmm) begin
539
                case(vicCycle)
540
                VIC_BMP1,VIC_BMP3:
541
                        v_adr_o <= bmndx;
542
                VIC_SPRITE_PTR:
543
                        if (MActive[sprite])
544
                                v_adr_o <= {vm[19:14],8'b11111111,sprite,2'b00};
545
                VIC_SPRITE_DAT:
546
                        if (MActive[sprite])
547
                                v_adr_o <= {MPtr,MCnt[sprite]};
548
                default: ;
549
                endcase
550
        end
551
        else begin
552
                case(vicCycle)
553
                VIC_CHAR:
554
                        v_adr_o <= {vm[19:14],vmndx};
555
                VIC_CHAR_BMP:
556
                        v_adr_o <= {cb[19:12],nextChar[8:0],scanline[2],2'b00};
557
                VIC_SPRITE_PTR:
558
                        if (MActive[sprite])
559
                                v_adr_o <= {vm[19:14],8'b11111111,sprite,2'b00};
560
                VIC_SPRITE_DAT:
561
                        if (MActive[sprite])
562
                                v_adr_o <= {MPtr,MCnt[sprite]};
563
                default: ;
564
                endcase
565
        end
566
end
567
 
568
//------------------------------------------------------------------------------
569
//------------------------------------------------------------------------------
570
always @(posedge v_clk_i)
571
begin
572
        if (hCtr==10'd192)
573
                rasterIRQDone <= `FALSE;
574
        if (irst_clr)
575
                irst <= 1'b0;
576
        if (rasterIRQDone == 1'b0 && vCtr == rasterCmp) begin
577
                rasterIRQDone <= `TRUE;
578
                irst <= 1'b1;
579
        end
580
end
581
 
582
//------------------------------------------------------------------------------
583
// Light pen
584
//
585
// The light pen only allows one hit per frame. It's the first hit that counts.
586
//------------------------------------------------------------------------------
587
 
588
reg lightPenHit;
589
always @(posedge v_clk_i)
590
begin
591
    if (ilp_clr)
592
                ilp <= `LOW;
593
    if (vCtr == pvTotal)
594
                lightPenHit <= `FALSE;
595
    else if (!lightPenHit && lp_n == `LOW) begin
596
                lightPenHit <= `TRUE;
597
                ilp <= `HIGH;
598
                lpx <= hCtr;
599
                lpy <= vCtr;
600
    end
601
end
602
 
603
 
604
//------------------------------------------------------------------------------
605
// Graphics mode pixel calc.
606
//------------------------------------------------------------------------------
607
reg [31:0] shiftingChar,waitingChar,readChar;
608
reg [7:0] shiftingPixels,waitingPixels,readPixels;
609
 
610
always @(posedge v_clk_i)
611
begin
612
        begin
613
        if (xscroll==hCtr[2:0]) begin
614
                shiftingChar <= waitingChar;
615
                shiftingPixels <= waitingPixels;
616
        end
617
        else
618
                shiftingPixels <= {shiftingPixels[6:0],1'b0};
619
        pixelColor <= 8'h00; // black
620
        if (bmm) begin
621
                pixelBgFlag <= bmpData[31];
622
                pixelColor <= bmpData[31:24];
623
                bmpData <= {bmpData[23:0],8'h00};
624
        end
625
        else begin
626
                pixelBgFlag <= shiftingChar[15];
627
                pixelColor <= shiftingPixels[7] ? shiftingChar[31:24] : shiftingChar[23:16];
628
        end
629
end
630
 
631
//------------------------------------------------------------------------------
632
// Output color selection
633
//------------------------------------------------------------------------------
634
 
635
reg [7:0] color_code;
636
 
637
always @(posedge v_clk_i)
638
begin
639
        color_code <= pixelColor;
640
        // See if the mib overrides the output
641
        for (n = 0; n < MIBCNT; n = n + 1) begin
642
                if (!mdp[n] || !pixelBgFlag) begin
643
                        case(MCurrentPixel[n])
644
                        2'd0:   ;
645
                        2'd1:   color_code <= mc1[n];
646
                        2'd2:   color_code <= mc2[n];
647
                        2'd3:   color_code <= mc3[n];
648
                        endcase
649
                end
650
        end
651
end
652
 
653
reg [7:0] ec;
654
always @(posedge v_clk_i)
655
begin
656
    if (border)
657
                color_o <= ec[6:0];
658
    else
659
                color_o <= color_code[6:0];
660
end
661
 
662
//------------------------------------------------------------------------------
663
// Register Interface
664
//
665
// VIC-II offers register feedback on all registers.
666
//------------------------------------------------------------------------------
667
reg [15:0] regShadow [127:0];
668
 
669
always @(posedge ws_clk_i)
670
if (ws_rst_i) begin
671
end
672
else begin
673
        if (cs) begin
674
                if (ws_we_i) begin
675
                        regShadow[ws_adr_i[7:1]] <= ws_dat_i;
676
                        case(ws_adr_i[7:1])
677
                        `M0X:   mx[0] <= ws_dat_i[9:0];
678
                        `M0Y:   my[0] <= ws_dat_i[8:0];
679
                        `M1X:   mx[1] <= ws_dat_i[9:0];
680
                        `M1Y:   my[1] <= ws_dat_i[8:0];
681
                        `M2X:   mx[2] <= ws_dat_i[9:0];
682
                        `M2Y:   my[2] <= ws_dat_i[8:0];
683
                        `M3X:   mx[3] <= ws_dat_i[9:0];
684
                        `M3Y:   my[3] <= ws_dat_i[8:0];
685
                        `M4X:   mx[4] <= ws_dat_i[9:0];
686
                        `M4Y:   my[4] <= ws_dat_i[8:0];
687
                        `M5X:   mx[5] <= ws_dat_i[9:0];
688
                        `M5Y:   my[5] <= ws_dat_i[8:0];
689
                        `M6X:   mx[6] <= ws_dat_i[9:0];
690
                        `M6Y:   my[6] <= ws_dat_i[8:0];
691
                        `M7X:   mx[7] <= ws_dat_i[9:0];
692
                        `M7Y:   my[7] <= ws_dat_i[8:0];
693
                        `M8X:   mx[8] <= ws_dat_i[9:0];
694
                        `M8Y:   my[8] <= ws_dat_i[8:0];
695
                        `M9X:   mx[9] <= ws_dat_i[9:0];
696
                        `M9Y:   my[9] <= ws_dat_i[8:0];
697
                        `M10X:  mx[10] <= ws_dat_i[9:0];
698
                        `M10Y:  my[10] <= ws_dat_i[8:0];
699
                        `M11X:  mx[11] <= ws_dat_i[9:0];
700
                        `M11Y:  my[11] <= ws_dat_i[8:0];
701
                        `RASTER:        rasterCmp <= {1'b0,ws_dat_i[8:0]};
702
                        `SE:    me <= ws_dat_i[11:0];
703
                        `CTRL1:
704
                                begin
705
                                        xscroll <= ws_dat_i[2:0];
706
                                        csel <= ws_dat_i[3];
707
                                        yscroll <= ws_dat_i[10:8];
708
                                        rsel <= ws_dat_i[11];
709
                                        den <= ws_dat_i[12];
710
                                        bmm <= ws_dat_i[13];
711
                                        bma <= {ws_dat_i[15:14],18'h00000};
712
                                end
713
                        `SYE:   mye <= ws_dat_i[11:0];
714
                        `MEMPTR:
715
                                begin
716
                                        cb <= {ws_dat_i[7:0],12'h000};
717
                                        vm <= {ws_dat_i[15:10],14'h0000};
718
                                end
719
                        `IRQEN:
720
                                begin
721
                                        erst <= ws_dat_i[0];
722
                                        embc <= ws_dat_i[1];
723
                                        emmc <= ws_dat_i[2];
724
                                        elp <= ws_dat_i[3];
725
                                end
726
                        `MXE:   mxe <= ws_dat_i[11:0];
727
                        `EC:    ec <= ws_dat_i[7:0];
728
                        `M0C1:  mc1[0] <= ws_dat_i[15:8];
729
                        `M1C1:  mc1[1] <= ws_dat_i[15:8];
730
                        `M2C1:  mc1[2] <= ws_dat_i[15:8];
731
                        `M3C1:  mc1[3] <= ws_dat_i[15:8];
732
                        `M4C1:  mc1[4] <= ws_dat_i[15:8];
733
                        `M5C1:  mc1[5] <= ws_dat_i[15:8];
734
                        `M6C1:  mc1[6] <= ws_dat_i[15:8];
735
                        `M7C1:  mc1[7] <= ws_dat_i[15:8];
736
                        `M8C1:  mc1[8] <= ws_dat_i[15:8];
737
                        `M9C1:  mc1[9] <= ws_dat_i[15:8];
738
                        `M10C1: mc1[10] <= ws_dat_i[15:8];
739
                        `M11C1: mc1[11] <= ws_dat_i[15:8];
740
                        `M0C2:  begin   mc2[0] <= ws_dat_i[7:0]; mc3[0] <= ws_dat_i[15:8]; end
741
                        `M1C2:  begin   mc2[1] <= ws_dat_i[7:0]; mc3[1] <= ws_dat_i[15:8]; end
742
                        `M2C2:  begin   mc2[2] <= ws_dat_i[7:0]; mc3[2] <= ws_dat_i[15:8]; end
743
                        `M3C2:  begin   mc2[3] <= ws_dat_i[7:0]; mc3[3] <= ws_dat_i[15:8]; end
744
                        `M4C2:  begin   mc2[4] <= ws_dat_i[7:0]; mc3[4] <= ws_dat_i[15:8]; end
745
                        `M5C2:  begin   mc2[5] <= ws_dat_i[7:0]; mc3[5] <= ws_dat_i[15:8]; end
746
                        `M6C2:  begin   mc2[6] <= ws_dat_i[7:0]; mc3[6] <= ws_dat_i[15:8]; end
747
                        `M7C2:  begin   mc2[7] <= ws_dat_i[7:0]; mc3[7] <= ws_dat_i[15:8]; end
748
                        `M8C2:  begin   mc2[8] <= ws_dat_i[7:0]; mc3[8] <= ws_dat_i[15:8]; end
749
                        `M9C2:  begin   mc2[9] <= ws_dat_i[7:0]; mc3[9] <= ws_dat_i[15:8]; end
750
                        `M10C2: begin   mc2[10] <= ws_dat_i[7:0]; mc3[10] <= ws_dat_i[15:8]; end
751
                        `M11C2: begin   mc2[11] <= ws_dat_i[7:0]; mc3[11] <= ws_dat_i[15:8]; end
752
                        endcase
753
                end
754
                else begin
755
                        ws_dat_o <= regShadow[ws_adr_i[7:1]];
756
                        case(ws_adr_i[7:1])
757
                        `RASTER:        ws_dat_o <= {7'd0,vCtr};
758
                        `IRQ:
759
                                begin
760
                                        ws_dat_o[0] <= irst;
761
                                        ws_dat_o[1] <= imbc;
762
                                        ws_dat_o[2] <= immc;
763
                                        ws_dat_o[3] <= ilp;
764
                                        ws_dat_o[7] <= irq;
765
                                end
766
                        `MMC:   ws_dat_o <= {4'h0,m2m};
767
                        `MDC:   ws_dat_o <= {4'h0,m2d};
768
                        endcase
769
                end
770
        end
771
end
772
 
773
SyncGen640x400_70Hz sg1
774
(
775
        .rst(rst),
776
        .clk(v_clk_i),
777
        .hSync(hSync),
778
        .vSync(vSync),
779
        .hCtr(hCtr),
780
        .vCtr(vCtr),
781
        .blank(blank),
782
        .border(border),
783
        .csel(csel),
784
        .rsel(rsel)
785
);
786
 
787
endmodule
788
 

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