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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2016-2017 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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//
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// SyncGen640x400_70Hz.v
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// sync generator
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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// WXGA video sync generator.
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//
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// Input clock: 25.00 MHz (100 MHz * 2/8)
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// Horizontal freq: 31.25 kHz (generated) (31.250KHz)
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// Vertical freq: 69.60 Hz (generated) (69.599 Hz)
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//
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// This module generates the basic sync timing signals required for a
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// WXGA display.
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//
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// ============================================================================
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module SyncGen640x400_70Hz(rst, clk, hSync, vSync, hCtr, vCtr, blank, border, csel, rsel);
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parameter phSyncOn = 8; // 8 front porch
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parameter phSyncOff = 104; // 96 sync
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parameter phBlankOff = 144; // 40 back porch
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parameter phBorderOff = 152; // 8 border
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parameter phBorderOn = 792; // 640 display
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parameter phBorderOff2 = 168;
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parameter phBorderOn2 = 776;
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parameter phBlankOn = 800; // 8 border
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parameter phTotal = 800; // 800 total clocks
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//
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parameter pvSyncOn = 5; // 5 front porch
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parameter pvSyncOff = 7; // 2 vertical sync
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parameter pvBlankOff = 35; // 28 back porch
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parameter pvBorderOff = 42; // 7 border 0
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parameter pvBorderOn = 442; // 400 display
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parameter pvBorderOff2 = 50;
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parameter pvBorderOn2 = 434;
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parameter pvBlankOn = 449; // 7 border 0
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parameter pvTotal = 449; // 449 total scan lines
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// 70 Hz
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// 640x400
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input rst; // reset
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input clk; // video clock
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output reg hSync, vSync; // sync outputs
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output [9:0] hCtr;
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output [9:0] vCtr;
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output blank; // blanking output
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output border;
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input csel; // column select
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input rsel; // row select
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//---------------------------------------------------------------------
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//---------------------------------------------------------------------
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wire vBlank, hBlank;
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wire vBorder,hBorder;
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wire hSync1,vSync1;
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reg blank;
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reg border;
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wire eol = hCtr==phTotal;
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wire eof = vCtr==pvTotal && eol;
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assign vSync1 = vCtr >= pvSyncOn && vCtr < pvSyncOff;
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assign hSync1 = !(hCtr >= phSyncOn && hCtr < phSyncOff);
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assign vBlank = vCtr >= pvBlankOn || vCtr < pvBlankOff;
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assign hBlank = hCtr >= phBlankOn || hCtr < phBlankOff;
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wire vBorder1 = vCtr >= pvBorderOn || vCtr < pvBorderOff;
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wire hBorder1 = hCtr >= phBorderOn || hCtr < phBorderOff;
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wire vBorder2 = vCtr >= pvBorderOn2 || vCtr < pvBorderOff2;
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wire hBorder2 = hCtr >= phBorderOn2 || hCtr < phBorderOff2;
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assign vBorder = rsel ? vBorder2 : vBorder1;
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assign hBorder = csel ? hBorder2 : hBorder1;
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counter #(10) u1 (.rst(rst), .clk(clk), .ce(1'b1), .ld(eol), .d(12'd1), .q(hCtr), .tc() );
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counter #(10) u2 (.rst(rst), .clk(clk), .ce(eol), .ld(eof), .d(12'd1), .q(vCtr), .tc() );
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always @(posedge clk)
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blank <= #1 hBlank|vBlank;
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always @(posedge clk)
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border <= #1 hBorder|vBorder;
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always @(posedge clk)
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hSync <= #1 hSync1;
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always @(posedge clk)
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vSync <= #1 vSync1;
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endmodule
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