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[/] [rtftextcontroller/] [trunk/] [rtl/] [verilog/] [vid_counter.v] - Blame information for rev 29

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1 29 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@fintron.ca
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//       ||
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//
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//      vid_counter.v
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//              generic counter
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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module vid_counter(rst, clk, ce, ld, d, q, tc);
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parameter WID=12;
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parameter pMaxCnt={WID{1'b1}};
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input rst;
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input clk;
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input ce;
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input ld;
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input [WID:1] d;
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output [WID:1] q;
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reg [WID:1] q;
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output tc;
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assign tc = &q;
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always @(posedge clk)
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if (rst)
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        q <= 1'b0;
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else begin
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        if (ld)
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                q <= d;
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        else if (ce & tc)
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                q <= 1'b0;
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        else if (ce)
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                q <= q + 1'b1;
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end
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endmodule

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