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Subversion Repositories rxaui_interface_and_xaui_to_rxaui_interface_adapter

[/] [rxaui_interface_and_xaui_to_rxaui_interface_adapter/] [BehModules/] [sip_beh_generic_module_lib.v] - Blame information for rev 2

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//-----------------------------------------------------------------------------
// Title         : Cloks and Reset generation
// Project       : SIP
//-----------------------------------------------------------------------------
// File          : sip_generic_module_lib.v
// Author        : Lior Valency
// Created       : 20/02/2008
// Last modified : 20/02/2008
//-----------------------------------------------------------------------------
// Description : This module is library of all cells writen in behaouvral.
//-----------------------------------------------------------------------------
// Copyright (c) 2007  Marvell International Ltd.
//
// THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.
// NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT
// OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE
// DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.
// THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS,
// IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.
//
//------------------------------------------------------------------------------
// Modification history :
// 12/12/2007  : created
//-----------------------------------------------------------------------------
 
// Clock Mux
module sip_clk_mux(/*AUTOARG*/
   // Outputs
   clk_out,
   // Inputs
   clk_in0, clk_in1, selector
   );
 
   ///////////////
   // INTERFACE //
   ///////////////
 
   input  clk_in0;
   input  clk_in1;
   input  selector;
   output clk_out;
 
   ///////////
   // LOGIC //
   ///////////
 
   assign clk_out = (selector == 1'b0) ? clk_in0 : clk_in1;
 
endmodule
 
// Clock divider
module sip_clock_divider(/*AUTOARG*/
   // Outputs
   clk_out,
   // Inputs
   clk_in, dn, dp, reset_n
   );
 
   ///////////////
   // INTERFACE //
   ///////////////
 
   input    clk_in;
   input    dn;
   input    dp;
   input    reset_n;
   output   clk_out;
 
   ////////////////////////////////
   // INTERNAL WIRES & REGISTERS //
   ////////////////////////////////
 
   reg      qn;
   reg      qp;
 
 
   ///////////
   // LOGIC //
   ///////////
 
   assign   clk_out = (clk_in == 1'b0) ? qn : qp;
 
   ////////
   // FF //
   ////////
 
   always @(posedge clk_in or negedge reset_n)
     begin
       if(reset_n == 1'b0)
         begin
           qn <= #1 1'b0;
         end
       else
         begin
           qn <= #1 dn;
         end
     end // always @ (posedge clk_in or negedge reset_n)
 
   always @(negedge clk_in or negedge reset_n)
     begin
       if(reset_n == 1'b0)
         begin
           qp <= #1 1'b0;
         end
       else
         begin
           qp <= #1 dp;
         end
     end // always @ (negedge clk_in or negedge reset_n)
 
 
 
endmodule // sip_clock_divider
 
 
 
 

Line No.	Rev	Author	Line
1	2	tsahidanie	`//-----------------------------------------------------------------------------`
2			`// Title : Cloks and Reset generation`
3			`// Project : SIP`
4			`//-----------------------------------------------------------------------------`
5			`// File : sip_generic_module_lib.v`
6			`// Author : Lior Valency`
7			`// Created : 20/02/2008`
8			`// Last modified : 20/02/2008`
9			`//-----------------------------------------------------------------------------`
10			`// Description : This module is library of all cells writen in behaouvral.`
11			`//-----------------------------------------------------------------------------`
12			`// Copyright (c) 2007 Marvell International Ltd.`
13			`//`
14			`// THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.`
15			`// NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT`
16			`// OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE`
17			`// DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.`
18			`// THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS,`
19			`// IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.`
20			`//`
21			`//------------------------------------------------------------------------------`
22			`// Modification history :`
23			`// 12/12/2007 : created`
24			`//-----------------------------------------------------------------------------`
25
26			`// Clock Mux`
27			`module sip_clk_mux(/AUTOARG/`
28			`// Outputs`
29			`clk_out,`
30			`// Inputs`
31			`clk_in0, clk_in1, selector`
32			`);`
33
34			`///////////////`
35			`// INTERFACE //`
36			`///////////////`
37
38			`input clk_in0;`
39			`input clk_in1;`
40			`input selector;`
41			`output clk_out;`
42
43			`///////////`
44			`// LOGIC //`
45			`///////////`
46
47			`assign clk_out = (selector == 1'b0) ? clk_in0 : clk_in1;`
48
49			`endmodule`
50
51			`// Clock divider`
52			`module sip_clock_divider(/AUTOARG/`
53			`// Outputs`
54			`clk_out,`
55			`// Inputs`
56			`clk_in, dn, dp, reset_n`
57			`);`
58
59			`///////////////`
60			`// INTERFACE //`
61			`///////////////`
62
63			`input clk_in;`
64			`input dn;`
65			`input dp;`
66			`input reset_n;`
67			`output clk_out;`
68
69			`////////////////////////////////`
70			`// INTERNAL WIRES & REGISTERS //`
71			`////////////////////////////////`
72
73			`reg qn;`
74			`reg qp;`
75
76
77			`///////////`
78			`// LOGIC //`
79			`///////////`
80
81			`assign clk_out = (clk_in == 1'b0) ? qn : qp;`
82
83			`////////`
84			`// FF //`
85			`////////`
86
87			`always @(posedge clk_in or negedge reset_n)`
88			`begin`
89			`if(reset_n == 1'b0)`
90			`begin`
91			`qn <= #1 1'b0;`
92			`end`
93			`else`
94			`begin`
95			`qn <= #1 dn;`
96			`end`
97			`end // always @ (posedge clk_in or negedge reset_n)`
98
99			`always @(negedge clk_in or negedge reset_n)`
100			`begin`
101			`if(reset_n == 1'b0)`
102			`begin`
103			`qp <= #1 1'b0;`
104			`end`
105			`else`
106			`begin`
107			`qp <= #1 dp;`
108			`end`
109			`end // always @ (negedge clk_in or negedge reset_n)`
110
111
112
113			`endmodule // sip_clock_divider`
114
115
116
117

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[/] [rxaui_interface_and_xaui_to_rxaui_interface_adapter/] [BehModules/] [sip_beh_generic_module_lib.v] - Blame information for rev 2