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[/] [rxaui_interface_and_xaui_to_rxaui_interface_adapter/] [GenericModules/] [sip_clock_divider_by_2.v] - Blame information for rev 2

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//-----------------------------------------------------------------------------
// Title         :Clock divider by 2
// Project       : SIP
//-----------------------------------------------------------------------------
// File          : sip_clock_divider_by_2.v
// Author        : Lior Valency
// Created       : 21/02/2008 
// Last modified : 21/02/2008 
//-----------------------------------------------------------------------------
// Description :The purpose of this block is to divide the input clock by 2, it
// use <MSIL_0065G_PDCKDIV> cell so the clock will be balanced. // <dp> and <dn>
// are generate from reguler divider (by 2).
//-----------------------------------------------------------------------------
// Copyright (c) 2007  Marvell International Ltd.
//
// THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.
// NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT
// OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE
// DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.
// THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS,
// IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.
//
//------------------------------------------------------------------------------
// Modification history :
// 12/12/2007  : created
//-----------------------------------------------------------------------------
module sip_clock_divider_by_2(/*AUTOARG*/
   // Outputs
   clk_div2,
   // Inputs
   reset_, clk
   );
 
 
   ///////////////
   // INTERFACE //  
   ///////////////
 
   // General
   input          reset_;
   input          clk;
   output         clk_div2;
 
   //////////////////////////////
   // Internal Regsiter & Wire //
   //////////////////////////////
 
   wire           dp_dn;
 
   ///////////
   // Logic //
   ///////////
 
   /* sip_clock_divider_by_2_glue AUTO_TEMPLATE (
    .clk_div2 (dp_dn),
    );*/
   sip_clock_divider_by_2_glue
     sip_clock_divider_by_2_glue(/*AUTOINST*/
                                 // Outputs
                                 .clk_div2              (dp_dn),         // Templated
                                 // Inputs
                                 .reset_                (reset_),
                                 .clk                   (clk));
 
   // Use this cell clock will be balaned.
   sip_clock_divider clock_divider
     (
      // Outputs
      .clk_out  (clk_div2),
      // Inputs
      .clk_in   (clk),
      .dn       (dp_dn),
      .dp       (dp_dn),
      .reset_n  (reset_));
 
endmodule // sip_clock_divider_by_2
 
 

Line No.	Rev	Author	Line
1	2	tsahidanie	`//-----------------------------------------------------------------------------`
2			`// Title :Clock divider by 2`
3			`// Project : SIP`
4			`//-----------------------------------------------------------------------------`
5			`// File : sip_clock_divider_by_2.v`
6			`// Author : Lior Valency`
7			`// Created : 21/02/2008`
8			`// Last modified : 21/02/2008`
9			`//-----------------------------------------------------------------------------`
10			`// Description :The purpose of this block is to divide the input clock by 2, it`
11			`// use <MSIL_0065G_PDCKDIV> cell so the clock will be balanced. // <dp> and <dn>`
12			`// are generate from reguler divider (by 2).`
13			`//-----------------------------------------------------------------------------`
14			`// Copyright (c) 2007 Marvell International Ltd.`
15			`//`
16			`// THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.`
17			`// NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT`
18			`// OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE`
19			`// DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.`
20			`// THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS,`
21			`// IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.`
22			`//`
23			`//------------------------------------------------------------------------------`
24			`// Modification history :`
25			`// 12/12/2007 : created`
26			`//-----------------------------------------------------------------------------`
27			`module sip_clock_divider_by_2(/AUTOARG/`
28			`// Outputs`
29			`clk_div2,`
30			`// Inputs`
31			`reset_, clk`
32			`);`
33
34
35			`///////////////`
36			`// INTERFACE //`
37			`///////////////`
38
39			`// General`
40			`input reset_;`
41			`input clk;`
42			`output clk_div2;`
43
44			`//////////////////////////////`
45			`// Internal Regsiter & Wire //`
46			`//////////////////////////////`
47
48			`wire dp_dn;`
49
50			`///////////`
51			`// Logic //`
52			`///////////`
53
54			`/* sip_clock_divider_by_2_glue AUTO_TEMPLATE (`
55			`.clk_div2 (dp_dn),`
56			`);*/`
57			`sip_clock_divider_by_2_glue`
58			`sip_clock_divider_by_2_glue(/AUTOINST/`
59			`// Outputs`
60			`.clk_div2 (dp_dn), // Templated`
61			`// Inputs`
62			`.reset_ (reset_),`
63			`.clk (clk));`
64
65			`// Use this cell clock will be balaned.`
66			`sip_clock_divider clock_divider`
67			`(`
68			`// Outputs`
69			`.clk_out (clk_div2),`
70			`// Inputs`
71			`.clk_in (clk),`
72			`.dn (dp_dn),`
73			`.dp (dp_dn),`
74			`.reset_n (reset_));`
75
76			`endmodule // sip_clock_divider_by_2`
77
78

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[/] [rxaui_interface_and_xaui_to_rxaui_interface_adapter/] [GenericModules/] [sip_clock_divider_by_2.v] - Blame information for rev 2