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tsahidanie |
//-----------------------------------------------------------------------------
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// Title : Phase sync fifo
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// Project : SIP
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//-----------------------------------------------------------------------------
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// File : sip_phase_sync_fifo_slow_2_fast.v
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// Author : Lior Valency
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// Created : 19/02/2008
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// Last modified : 19/02/2008
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//-----------------------------------------------------------------------------
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// Description : This module is a free-running fifo which syncs the data between
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// 2 clocks domain, the read is double frequency and half-width from the read.
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// in case <fifo_type> is '0' this is regular fifo in which rd and wr clock
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// are the same.
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//-----------------------------------------------------------------------------
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// Copyright (c) 2007 Marvell International Ltd.
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//
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// THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.
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// NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT
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// OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE
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// DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.
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// THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS,
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// IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.
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//
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//------------------------------------------------------------------------------
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// Modification history :
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// 12/12/2007 : created
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//-----------------------------------------------------------------------------
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`timescale 1ns / 10ps
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module sip_phase_sync_fifo_slow_2_fast (/*AUTOARG*/
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// Outputs
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fifo_data_out,
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// Inputs
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fifo_type, wr_clk, rd_clk, wr_reset_, rd_reset_, fifo_data_in
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);
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parameter FAST_DATA_WIDTH = 10;
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parameter SYNC_FIFO_WIDTH = 2*FAST_DATA_WIDTH;
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parameter SYNC_FIFO_DEPTH = 8;
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parameter SYNC_FIFO_ADDR_WIDTH = 3;
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parameter SYNC_FIFO_LAST_ENTRY = 3'd7;
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parameter FIFO_RD_PTR_INIT = 3'd4;
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parameter FIFO_ONE = 3'd1;
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parameter REGULAR = 1'b0;
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input fifo_type;
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input wr_clk;
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input rd_clk;
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input wr_reset_;
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input rd_reset_;
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input [SYNC_FIFO_WIDTH-1:0] fifo_data_in;
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output [SYNC_FIFO_WIDTH-1:0] fifo_data_out;
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//
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reg [SYNC_FIFO_WIDTH-1:0] fifo_entry [SYNC_FIFO_DEPTH-1:0];
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reg [SYNC_FIFO_WIDTH-1:0] fifo_entry_d [SYNC_FIFO_DEPTH-1:0];
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reg [SYNC_FIFO_WIDTH-1:0] fifo_data_out;
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wire [SYNC_FIFO_WIDTH-1:0] fifo_data_out_d;
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reg [SYNC_FIFO_ADDR_WIDTH-1:0] fifo_wr_addr;
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wire [SYNC_FIFO_ADDR_WIDTH-1:0] fifo_wr_addr_d;
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reg [SYNC_FIFO_ADDR_WIDTH-1:0] fifo_rd_addr;
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wire [SYNC_FIFO_ADDR_WIDTH-1:0] fifo_rd_addr_d;
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wire inc_rd_ptr_d_;
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reg inc_rd_ptr_;
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wire [SYNC_FIFO_WIDTH-1:0] full_fifo_data_out;
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integer wr_addr,i;
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//Internal signals
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assign fifo_wr_addr_d = (fifo_wr_addr == SYNC_FIFO_LAST_ENTRY) ? {SYNC_FIFO_ADDR_WIDTH{1'b0}} :
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(fifo_wr_addr + FIFO_ONE);
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assign fifo_rd_addr_d = ((inc_rd_ptr_ == 1'b0) || (fifo_type == REGULAR)) ?
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((fifo_rd_addr == SYNC_FIFO_LAST_ENTRY) ? {SYNC_FIFO_ADDR_WIDTH{1'b0}} :
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(fifo_rd_addr + FIFO_ONE)) :
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fifo_rd_addr;
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// increment read pointer every 2cc
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assign inc_rd_ptr_d_ = ~inc_rd_ptr_;
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//read from fifo
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assign full_fifo_data_out = fifo_entry[fifo_rd_addr];
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assign fifo_data_out_d = (fifo_type == REGULAR) ? full_fifo_data_out :
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(inc_rd_ptr_ == 1'b1) ?
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{{FAST_DATA_WIDTH{1'b0}},full_fifo_data_out[FAST_DATA_WIDTH-1:0]} :
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{{FAST_DATA_WIDTH{1'b0}},full_fifo_data_out[SYNC_FIFO_WIDTH-1:FAST_DATA_WIDTH]};
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//write to fifo
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always @ (fifo_entry[0] or fifo_entry[1] or fifo_entry[2] or fifo_entry[3] or
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fifo_entry[4] or fifo_entry[5] or fifo_entry[6] or fifo_entry[7] or
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/*AUTOSENSE*/fifo_data_in or fifo_wr_addr)
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begin
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for (wr_addr = 0; wr_addr < SYNC_FIFO_DEPTH; wr_addr = wr_addr + 1)
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begin
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fifo_entry_d[wr_addr] = (fifo_wr_addr == wr_addr) ? fifo_data_in : fifo_entry[wr_addr];
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end
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end // always @ (...
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//write clock domain FF
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always @ (negedge wr_clk or negedge wr_reset_)
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begin
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if (!wr_reset_)
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begin
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for (i = 0; i < SYNC_FIFO_DEPTH; i = i + 1)
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begin
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fifo_entry[i] <= #1 {SYNC_FIFO_WIDTH{1'b0}};
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end
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fifo_wr_addr <= #1 {SYNC_FIFO_ADDR_WIDTH{1'b0}};
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end
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else
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begin
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for (i = 0; i < SYNC_FIFO_DEPTH; i = i + 1)
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begin
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fifo_entry[i] <= #1 fifo_entry_d[i];
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end
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fifo_wr_addr <= #1 fifo_wr_addr_d;
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end
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end // always @ (negedge wr_clk or negedge wr_reset_)
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//read clock domain FF
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always @(posedge rd_clk or negedge rd_reset_)
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begin
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if(!rd_reset_)
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begin
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inc_rd_ptr_ <= #1 1'b1;
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fifo_rd_addr <= #1 FIFO_RD_PTR_INIT;
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fifo_data_out <= #1 {SYNC_FIFO_WIDTH{1'b0}};
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end
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else
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begin
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inc_rd_ptr_ <= #1 inc_rd_ptr_d_;
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fifo_rd_addr <= #1 fifo_rd_addr_d;
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fifo_data_out <= #1 fifo_data_out_d;
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end
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end // always @ (posedge rd_clk or negedge rd_reset_)
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endmodule // tc_qsgmii_phase_sync_fifo_slow_2_fast
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