OpenCores
URL https://opencores.org/ocsvn/rxaui_interface_and_xaui_to_rxaui_interface_adapter/rxaui_interface_and_xaui_to_rxaui_interface_adapter/trunk

Subversion Repositories rxaui_interface_and_xaui_to_rxaui_interface_adapter

[/] [rxaui_interface_and_xaui_to_rxaui_interface_adapter/] [TxPath/] [sip_rxaui_tx_top.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 tsahidanie 
//-----------------------------------------------------------------------------
2 
// Title         : Rxaui Tx top
3 
// Project       : SIP
4 
//-----------------------------------------------------------------------------
5 
// File          : sip_rxaui_tx_top.v
6 
// Author        : Lior Valency
7 
// Created       : 17/02/2008
8 
// Last modified : 17/02/2008
9 
//-----------------------------------------------------------------------------
10 
// Description : This is the top of rxaui tranismit block the purpose of this block
11 
// is to receive data from 2 lanes (XPCS) and interleave them on the same lane.
12 
//-----------------------------------------------------------------------------
13 
// Copyright (c) 2007  Marvell International Ltd.
14 
//
15 
// THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.
16 
// NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT
17 
// OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE
18 
// DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.
19 
// THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS,
20 
// IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.
21 
//
22 
//------------------------------------------------------------------------------
23 
// Modification history :
24 
// 12/12/2007  : created
25 
//-----------------------------------------------------------------------------
26 
`timescale 10ps / 10ps
27 
 
28 
 
29 
module sip_rxaui_tx_top(/*AUTOARG*/
30 
   // Outputs
31 
   rxaui_tx_data,
32 
   // Inputs
33 
   serdes_tx_clk, serdes_txclk_in0_reset_, serdes_txclk_in1_reset_,
34 
   serdes_tx_clk_reset_, media_interface_mode, serdes_mode, txclk_in0,
35 
   txdata_serdes0, txclk_in1, txdata_serdes1
36 
   );
37 
 
38 
`include "sip_rxaui_params.inc"
39 
 
40 
   /* AUTO_CONSTANT (1'b0 or 1'b1 or 10'd0)*/
41 
 
42 
   ///////////////
43 
   // INTERFACE //
44 
   ///////////////
45 
 
46 
   // General
47 
   input                               serdes_tx_clk;
48 
   input                               serdes_txclk_in0_reset_;
49 
   input                               serdes_txclk_in1_reset_;
50 
   input                               serdes_tx_clk_reset_;
51 
 
52 
   // Configuration
53 
   input                               media_interface_mode;
54 
   input                               serdes_mode;
55 
 
56 
   // XPCS interface
57 
   input                               txclk_in0;
58 
   input [SERDES_DATA_W-1:0]            txdata_serdes0;
59 
   input                               txclk_in1;
60 
   input [SERDES_DATA_W-1:0]            txdata_serdes1;
61 
 
62 
   // Serdes interface
63 
   output [SERDES_DATA_W-1:0]           rxaui_tx_data;
64 
 
65 
   /*AUTOOUTPUT*/
66 
   // Beginning of automatic outputs (from unused autoinst outputs)
67 
   // End of automatics
68 
   /*AUTOINPUT*/
69 
   // Beginning of automatic inputs (from unused autoinst inputs)
70 
   // End of automatics
71 
   /*AUTOWIRE*/
72 
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
73 
   // End of automatics
74 
 
75 
 
76 
 
77 
   ////////////////////
78 
   // INTERNAL WIRES //
79 
   ////////////////////
80 
   wire [SERDES_DATA_W-1:0]             fifo_rxaui_tx_data0;
81 
   wire [SERDES_DATA_W-1:0]             fifo_rxaui_tx_data1;
82 
   wire                                fifo_type;
83 
 
84 
   /*sip_phase_sync_fifo_slow_2_fast AUTO_TEMPLATE(
85 
    .fifo_data_out      (fifo_rxaui_tx_data0[SERDES_DATA_W-1:0]),
86 
    .wr_clk             (txclk_in0),
87 
    .rd_clk             (serdes_tx_clk),
88 
    .wr_reset_          (serdes_txclk_in0_reset_),
89 
    .rd_reset_          (serdes_tx_clk_reset_),
90 
    .fifo_data_in       (txdata_serdes0[SERDES_DATA_W-1:0]),
91 
    );*/
92 
   sip_phase_sync_fifo_slow_2_fast
93 
     sip_phase_sync_fifo_slow_2_fast_0(/*AUTOINST*/
94 
                                       // Outputs
95 
                                       .fifo_data_out   (fifo_rxaui_tx_data0[SERDES_DATA_W-1:0]), // Templated
96 
                                       // Inputs
97 
                                       .fifo_type       (fifo_type),
98 
                                       .wr_clk          (txclk_in0),     // Templated
99 
                                       .rd_clk          (serdes_tx_clk), // Templated
100 
                                       .wr_reset_       (serdes_txclk_in0_reset_), // Templated
101 
                                       .rd_reset_       (serdes_tx_clk_reset_), // Templated
102 
                                       .fifo_data_in    (txdata_serdes0[SERDES_DATA_W-1:0])); // Templated
103 
 
104 
   /*sip_phase_sync_fifo_slow_2_fast AUTO_TEMPLATE(
105 
    .fifo_data_out      (fifo_rxaui_tx_data1[SERDES_DATA_W-1:0]),
106 
    .wr_clk             (txclk_in1),
107 
    .rd_clk             (serdes_tx_clk),
108 
    .wr_reset_          (serdes_txclk_in1_reset_),
109 
    .rd_reset_          (serdes_tx_clk_reset_),
110 
    .fifo_data_in       (txdata_serdes1[SERDES_DATA_W-1:0]),
111 
    .fifo_type          (media_interface_mode),
112 
    );*/
113 
   sip_phase_sync_fifo_slow_2_fast
114 
     sip_phase_sync_fifo_slow_2_fast_1(/*AUTOINST*/
115 
                                       // Outputs
116 
                                       .fifo_data_out   (fifo_rxaui_tx_data1[SERDES_DATA_W-1:0]), // Templated
117 
                                       // Inputs
118 
                                       .fifo_type       (media_interface_mode), // Templated
119 
                                       .wr_clk          (txclk_in1),     // Templated
120 
                                       .rd_clk          (serdes_tx_clk), // Templated
121 
                                       .wr_reset_       (serdes_txclk_in1_reset_), // Templated
122 
                                       .rd_reset_       (serdes_tx_clk_reset_), // Templated
123 
                                       .fifo_data_in    (txdata_serdes1[SERDES_DATA_W-1:0])); // Templated
124 
 
125 
   sip_rxaui_tx_glue
126 
     sip_rxaui_tx_glue(/*AUTOINST*/
127 
                       // Outputs
128 
                       .fifo_type       (fifo_type),
129 
                       .rxaui_tx_data   (rxaui_tx_data[SERDES_DATA_W-1:0]),
130 
                       // Inputs
131 
                       .media_interface_mode(media_interface_mode),
132 
                       .serdes_mode     (serdes_mode),
133 
                       .fifo_rxaui_tx_data0(fifo_rxaui_tx_data0[SERDES_DATA_W-1:0]),
134 
                       .fifo_rxaui_tx_data1(fifo_rxaui_tx_data1[SERDES_DATA_W-1:0]),
135 
                       .txdata_serdes0  (txdata_serdes0[SERDES_DATA_W-1:0]));
136 
 
137 
 
138 
endmodule // sip_rxaui_tx_top
139 
 
140 
// Local Variables:
141 
// verilog-library-directories:( "." "/proj1/galileo101/tomcat/MODELS/current/Model_link/")
142 
// End:
143 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.