URL
https://opencores.org/ocsvn/s1_core/s1_core/trunk
[/] [s1_core/] [trunk/] [docs/] [UPDATING.txt] - Blame information for rev 114
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
114 |
albert.wat |
S1 Core - OpenSPARC sources updating
|
2 |
|
|
====================================
|
3 |
62 |
fafa1971 |
|
4 |
|
|
To update the source files of the SPARC Core to the latest
|
5 |
|
|
version provided by Sun Microsystems with their OpenSPARC
|
6 |
|
|
T1 project, please perform the following steps:
|
7 |
|
|
|
8 |
|
|
- download the latest chip design from www.opensparc.net
|
9 |
|
|
(requires free registration and takes a while);
|
10 |
|
|
- unpack the tarball, for instance under ~/opensparc-t1 ;
|
11 |
|
|
- make the T1_ROOT enviroment variable contained in your
|
12 |
|
|
top-most $S1_ROOT/sourceme file match the directory
|
13 |
|
|
you used in the previous step;
|
14 |
|
|
- source the sourceme file in a fresh opened shell.
|
15 |
|
|
|
16 |
|
|
Now you are ready to perform the updating; a script named
|
17 |
|
|
"update_sparccore" is provided and it can be called using
|
18 |
|
|
the following syntax:
|
19 |
|
|
|
20 |
|
|
update_sparccore -me
|
21 |
|
|
|
22 |
|
|
or
|
23 |
|
|
|
24 |
|
|
update_sparccore -se
|
25 |
|
|
|
26 |
|
|
or
|
27 |
|
|
|
28 |
|
|
update_sparccore -ee
|
29 |
|
|
|
30 |
|
|
From now on, all the commands you use to simulate or to
|
31 |
|
|
synthesize the design will refer to the SPARC Core version
|
32 |
|
|
you are using.
|
33 |
|
|
|
34 |
|
|
NOTE: in order to call the "update_sparccore" installed you
|
35 |
|
|
*MUST* have Icarus Verilog installed, since it is used to
|
36 |
|
|
preprocess the Verilog files; no matter you want to use
|
37 |
|
|
another simulator for functional verification.
|
38 |
|
|
|
39 |
|
|
The argument to the script works as follows:
|
40 |
|
|
|
41 |
|
|
- S1 Core ME (Memory-less Edition): one thread, no cache;
|
42 |
|
|
- S1 Core SE (Single-thread Edition): one thread, usual 16K+8K L1 caches;
|
43 |
|
|
- S1 Core EE (Elite Edition): four threads, usual 16K+8K L1 caches.
|
44 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.