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[/] [s6soc/] [trunk/] [rtl/] [busmaster.v] - Blame information for rev 46

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1 4 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    busmaster.v
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//
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// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
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//
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// Purpose:     This is the highest level, simulatable, file in the S6SoC
8
//              project--of that portion of the project that includes the
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//      ZipCPU.  This portion therefore contains references to all of the
10
//      masters (ZipCPU) and slaves (flash, block RAM, I/O, Scope) on the
11
//      wishbone bus, and connects them all together.  Hence, this contains
12
//      the wishbone interconnect logic as well.
13 2 dgisselq
//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
18 2 dgisselq
//
19 46 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
30
//
31
// You should have received a copy of the GNU General Public License along
32
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
35
//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
38
//
39
//
40
////////////////////////////////////////////////////////////////////////////////
41
//
42
//
43 2 dgisselq
`include "builddate.v"
44
//
45 16 dgisselq
`define IMPLEMENT_ONCHIP_RAM
46 2 dgisselq
`define FLASH_ACCESS
47 7 dgisselq
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
48 16 dgisselq
// `define      COMPRESSED_SCOPE
49
`define INCLUDE_CPU_RESET_LOGIC
50 2 dgisselq
module  busmaster(i_clk, i_rst,
51 46 dgisselq
                i_uart, o_uart_rts_n, o_uart, i_uart_cts_n,
52 2 dgisselq
                // The SPI Flash lines
53
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
54
                // The board I/O
55
                i_btn, o_led, o_pwm, o_pwm_aux,
56
                // Keypad connections
57
                i_kp_row, o_kp_col,
58
                // GPIO lines
59
                i_gpio, o_gpio);
60 46 dgisselq
        parameter       BUS_ADDRESS_WIDTH=23,
61
                        ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
62
                        CMOD_ZIPCPU_RESET_ADDRESS=32'h1200000,
63
                        UART_SETUP = 31'd25;
64
        localparam      ZA=ZIP_ADDRESS_WIDTH,
65
                        BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
66
        // 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from
67
        // 0 to 11.  As with many other devices, the wb_cyc line is more for
68
        // form than anything else--it is ignored by the memory itself.
69
        localparam      LGMEMSZ=14;     // Takes 8 BLKRAM16 elements for LGMEMSZ=14
70
        // As with the memory size, the flash size is also measured in log_2 of
71
        // the number of bytes.
72
        localparam      LGFLASHSZ = 24;
73 2 dgisselq
        input                   i_clk, i_rst;
74 46 dgisselq
        // UART parameters
75
        input                   i_uart, i_uart_cts_n;
76
        output  wire            o_uart, o_uart_rts_n;
77 2 dgisselq
        // SPI flash control
78
        output  wire            o_qspi_cs_n, o_qspi_sck;
79
        output  wire    [3:0]    o_qspi_dat;
80
        input           [3:0]    i_qspi_dat;
81
        output  wire    [1:0]    o_qspi_mod;
82
        // Board I/O
83
        input           [1:0]    i_btn;
84
        output  wire    [3:0]    o_led;
85
        output  wire            o_pwm;
86
        output  wire    [1:0]    o_pwm_aux;
87
        // Keypad
88
        input           [3:0]    i_kp_row;
89
        output  wire    [3:0]    o_kp_col;
90
        // GPIO liines
91
        input           [15:0]   i_gpio;
92
        output  wire    [15:0]   o_gpio;
93
 
94
 
95
        //
96
        //
97
        // Master wishbone wires
98
        //
99
        //
100
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
101
        wire    [31:0]   wb_data, wb_idata;
102 46 dgisselq
        wire    [3:0]    wb_sel;
103 2 dgisselq
        wire    [(BAW-1):0]      wb_addr;
104
 
105
        // Wires going to devices
106
        // And then headed back home
107
        wire    w_interrupt;
108
        // Oh, and the debug control for the ZIP CPU
109
        wire            zip_dbg_ack, zip_dbg_stall;
110
        wire    [31:0]   zip_dbg_data;
111
 
112
 
113
        //
114
        //
115
        // The BUS master (source): The ZipCPU
116
        //
117
        //
118
        wire            zip_cyc, zip_stb, zip_we, zip_cpu_int;
119
        wire    [(ZA-1):0]       w_zip_addr;
120
        wire    [(BAW-1):0]      zip_addr;
121 16 dgisselq
        wire    [31:0]           zip_data, zip_scope_data;
122 2 dgisselq
        // and then coming from devices
123
        wire            zip_ack, zip_stall, zip_err;
124
        wire    dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
125
        wire    [(BAW-1):0]      dwb_addr;
126
        wire    [31:0]           dwb_odata;
127
 
128 46 dgisselq
        wire    cpu_reset, watchdog_int;
129 2 dgisselq
//
130 16 dgisselq
`ifdef  INCLUDE_CPU_RESET_LOGIC
131
        reg     btn_reset, x_button, r_button;
132
        initial btn_reset = 1'b0;
133
        initial x_button = 1'b0;
134
        initial r_button = 1'b0;
135
        always @(posedge i_clk)
136
        begin
137
                x_button <= i_btn[1];
138
                r_button <= x_button;
139 46 dgisselq
                btn_reset <= ((r_button)&&(zip_cpu_int))||(watchdog_int);
140 16 dgisselq
        end
141
        assign  cpu_reset = btn_reset;
142
`else
143
        assign  cpu_reset = 1'b0;
144
`endif
145
 
146 2 dgisselq
        zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
147 46 dgisselq
                swic(i_clk, btn_reset, // 1'b0,
148 2 dgisselq
                        // Zippys wishbone interface
149 46 dgisselq
                        wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data, wb_sel,
150 2 dgisselq
                                wb_ack, wb_stall, wb_idata, wb_err,
151
                        w_interrupt, zip_cpu_int,
152 16 dgisselq
                        // Debug wishbone interface -- not really used
153 2 dgisselq
                        1'b0, 1'b0,1'b0, 1'b0, 32'h00,
154 16 dgisselq
                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
155
                        zip_scope_data);
156 2 dgisselq
        generate
157
        if (ZA < BAW)
158
                assign  wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
159
        else
160
                assign  wb_addr = w_zip_addr;
161
        endgenerate
162
 
163 46 dgisselq
 
164
        // Signals to build/detect bus errors
165
        wire    none_sel, many_sel;
166
 
167
        wire    io_sel, flash_sel, flctl_sel, scop_sel, mem_sel;
168 25 dgisselq
        wire    flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
169 2 dgisselq
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
170 4 dgisselq
        reg     io_ack;
171 2 dgisselq
 
172
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
173
                        spio_data, gpio_data, uart_data;
174
        reg     [31:0]   io_data;
175
        reg     [(BAW-1):0]      bus_err_addr;
176 46 dgisselq
        //
177
        // wb_ack
178
        //
179
        // The returning wishbone ack is equal to the OR of every component that
180
        // might possibly produce an acknowledgement, gated by the CYC line.  To
181
        // add new components, OR their acknowledgements in here.
182
        //
183
        // Note the reference to none_sel.  If nothing is selected, the result
184
        // is an error.  Here, we do nothing more than insure that the erroneous
185
        // request produces an ACK ... if it was ever made, rather than stalling
186
        // the bus.
187
        //
188 2 dgisselq
 
189 46 dgisselq
 
190
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)
191 2 dgisselq
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
192 46 dgisselq
 
193
        //
194
        // wb_stall
195
        //
196
        // The returning wishbone stall line really depends upon what device
197
        // is requested.  Thus, if a particular device is selected, we return
198
        // the stall line for that device.
199
        //
200
        // To add a new device, simply and that devices select and stall lines
201
        // together, and OR the result with the massive OR logic below.
202
        //
203 2 dgisselq
        assign  wb_stall = ((io_sel)&&(io_stall))
204
                        ||((scop_sel)&&(scop_stall))
205
                        ||((mem_sel)&&(mem_stall))
206
                        ||((flash_sel||flctl_sel)&&(flash_stall));
207
                        // (none_sel)&&(1'b0)
208
 
209 46 dgisselq
        //
210
        // wb_idata
211
        //
212
        // This is the data returned on the bus.  Here, we select between a
213
        // series of bus sources to select what data to return.  The basic
214
        // logic is simply this: the data we return is the data for which the
215
        // ACK line is high.
216
        //
217
        // The last item on the list is chosen by default if no other ACK's are
218
        // true.  Although we might choose to return zeros in that case, by
219
        // returning something we can skimp a touch on the logic.
220
        //
221
        // To add another device, add another ack check, and another closing
222
        // parenthesis.
223
        //
224 2 dgisselq
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
225 46 dgisselq
                        : ((mem_ack)?(mem_data)
226
                        : flash_data);
227 2 dgisselq
 
228 46 dgisselq
        //
229
        // wb_err
230
        //
231
        // This is the bus error signal.  It should never be true, but practice
232
        // teaches us otherwise.  Here, we allow for three basic errors:
233
        //
234
        // 1. STB is true, but no devices are selected
235
        //
236
        //      This is the null pointer reference bug.  If you try to access
237
        //      something on the bus, at an address with no mapping, the bus
238
        //      should produce an error--such as if you try to access something
239
        //      at zero.
240
        //
241
        // 2. STB is true, and more than one device is selected
242
        //
243
        //      (This can be turned off, if you design this file well.  For
244
        //      this line to be true means you have a design flaw.)
245
        //
246
        // 3. If more than one ACK is every true at any given time.
247
        //
248
        //      This is a bug of bus usage, combined with a subtle flaw in the
249
        //      WB pipeline definition.  You can issue bus requests, one per
250
        //      clock, and if you cross device boundaries with your requests,
251
        //      you may have things come back out of order (not detected here)
252
        //      or colliding on return (detected here).  The solution to this
253
        //      problem is to make certain that any burst request does not cross
254
        //      device boundaries.  This is a requirement of whoever (or
255
        //      whatever) drives the bus.
256
        //
257
        assign  wb_err = ((wb_stb)&&(none_sel || many_sel)) || many_ack;
258
 
259 2 dgisselq
        // Addresses ...
260 46 dgisselq
        //
261
        // dev_sel
262
        //
263
        // The device select lines
264
        //
265
        //
266 2 dgisselq
 
267
 
268 46 dgisselq
        //
269
        // The skipaddr bitfield below is our cheaters way of handling
270
        // device selection.  We grab particular wires from the bus to do
271
        // this, and ignore all others.  While this may lead to some
272
        // surprising results for the CPU when it tries to access an
273
        // inappropriate address, it also minimizes our logic while also
274
        // placing every address at the right address.  The only problem is
275
        // ... devices will also be at some unexpected addresses, but ... this
276
        // is still within our spec.
277
        //
278
        wire    [3:0]    skipaddr;
279
        assign  skipaddr = {
280
                        wb_addr[(LGFLASHSZ-2)], // Flash
281
                        wb_addr[(LGMEMSZ-2)],   // RAM
282
                        wb_addr[ 9],            // SCOPE
283
                        wb_addr[ 8] };          // I/O
284
        //
285
        // This might not be the most efficient way in hardware, but it will
286
        // work for our purposes here.  There are two phantom bits for each
287
        // of these ... bits that tell the CPU which byte within the word, and
288
        // another phantom bit because we allocated a minimum of two words to
289
        // every device.
290
        //
291
        wire    idle_n;
292
`ifdef  ZERO_ON_IDLE
293
        assign idle_n = wb_stb;
294
`else
295
        assign idle_n = 1'b1;
296 2 dgisselq
`endif
297 46 dgisselq
 
298
// `define ZERO_ON_IDLE
299
`ifdef  ZERO_ON_IDLE
300
        assign  idle_n = (wb_cyc)&&(wb_stb);
301 25 dgisselq
`else
302 46 dgisselq
        assign  idle_n = 1'b1;
303 25 dgisselq
`endif
304 46 dgisselq
        assign  io_sel   =((idle_n)&&(skipaddr[3:0]==4'h1));
305
        assign  scop_sel =((idle_n)&&(skipaddr[3:1]==3'h1)); // = 4'h2
306
        assign  flctl_sel= 1'b0; // ((wb_cyc)&&(skipaddr[3:0]==4'h3));
307
        assign  mem_sel  =((idle_n)&&(skipaddr[3:2]==2'h1));
308
        assign  flash_sel=((idle_n)&&(skipaddr[3]));
309 2 dgisselq
 
310 46 dgisselq
        //
311
        // none_sel
312
        //
313
        // This wire is true if wb_stb is true and no device is selected.  This
314
        // is an error condition, but here we present the logic to test for it.
315
        //
316
        //
317
        // If you add another device, add another OR into the select lines
318
        // associated with this term.
319
        //
320
        assign  none_sel =((wb_stb)&&(skipaddr==4'h0));
321 2 dgisselq
 
322
        //
323 46 dgisselq
        // many_sel
324 2 dgisselq
        //
325 46 dgisselq
        // This should *never* be true .... unless you mess up your address
326
        // decoding logic.  Since I've done that before, I test/check for it
327
        // here.
328 2 dgisselq
        //
329 46 dgisselq
        // To add a new device here, simply add it to the list.  Make certain
330
        // that the width of the add, however, is greater than the number
331
        // of devices below.  Hence, for 3 devices, you will need an add
332
        // at least 3 bits in width, for 7 devices you will need at least 4
333
        // bits, etc.
334
        //
335
        // Because this add uses the {} operator, the individual components to
336
        // it are by default unsigned ... just as we would like.
337
        //
338
        // There's probably another easier/better/faster/cheaper way to do this,
339
        // but I haven't found any such that are also easier to adjust with
340
        // new devices.  I'm open to options.
341
        //
342
        assign  many_sel = 1'b0;
343
 
344
        //
345
        // many_ack
346
        //
347
        // Normally this would capture the error when multiple things creates acks
348
        // at the same time.  The S6 is small, though, and doesn't have the logic
349
        // we need to do this right.  Hence we just declare (and hope) that this
350
        // will never be true and work with that.
351
        //
352
        assign  many_ack = 1'b0;
353
 
354
 
355
        wire            flash_interrupt, scop_interrupt, timer_int,
356
                        gpio_int, pwm_int, keypad_int,button_int;
357
 
358
 
359
        //
360
        // bus_err_addr
361
        //
362
        // We'd like to know, after the fact, what (if any) address caused a
363
        // bus error.  So ... if we get a bus error, let's record the address
364
        // on the bus for later analysis.
365
        //
366
        initial bus_err_addr = 0;
367
        always @(posedge i_clk)
368
                if (wb_err)
369
                        bus_err_addr <= wb_addr;
370
        //
371
        // Interrupt processing
372
        //
373
        // The interrupt controller will be used to tell us if any interrupts
374
        // take place.  
375
        //
376
        // To add more interrupts, you can just add more wires to this
377
        // int_vector.
378
        // 
379 2 dgisselq
        reg             rx_rdy;
380
        wire    [10:0]   int_vector;
381 46 dgisselq
        assign  int_vector = {
382 25 dgisselq
                                        gpio_int, pwm_int, keypad_int,
383 46 dgisselq
                                (!tx_stb), rx_rdy,
384
                                1'b0, timer_int,
385
                                1'b0, scop_interrupt,
386 2 dgisselq
                                wb_err, button_int };
387
 
388
        wire    [31:0]   pic_data;
389 4 dgisselq
        icontrol #(11)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
390 2 dgisselq
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
391
                        wb_data, pic_data, int_vector, w_interrupt);
392
 
393 46 dgisselq
        wire    [31:0]   timer_data, watchdog_data;
394 2 dgisselq
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
395 25 dgisselq
        ziptimer        #(32,31,1)
396 46 dgisselq
                thetimer(i_clk, 1'b0, 1'b1, wb_cyc,
397 2 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
398 46 dgisselq
                                wb_we, wb_data, zta_ack, zta_stall, timer_data,
399
                                timer_int);
400 25 dgisselq
        ziptimer        #(32,31,0)
401 46 dgisselq
                watchdog(i_clk, cpu_reset, 1'b1, wb_cyc,
402 2 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
403 46 dgisselq
                                wb_we, wb_data, ztb_ack, ztb_stall, watchdog_data,
404
                                watchdog_int);
405 2 dgisselq
 
406
        always @(posedge i_clk)
407
                case(wb_addr[3:0])
408
                        4'h0: io_data <= pic_data;
409 46 dgisselq
                        4'h1: io_data <= { {(30-BAW){1'b0}}, bus_err_addr, 2'b00 };
410
                        4'h2: io_data <= timer_data;
411
                        4'h3: io_data <= watchdog_data;
412 2 dgisselq
                        4'h4: io_data <= pwm_data;
413
                        4'h5: io_data <= spio_data;
414
                        4'h6: io_data <= gpio_data;
415
                        4'h7: io_data <= uart_data;
416
                        default: io_data <= `DATESTAMP;
417
                        // 4'h8: io_data <= `DATESTAMP;
418
                endcase
419
        always @(posedge i_clk)
420 46 dgisselq
                io_ack <= (wb_stb)&&(io_sel);
421 2 dgisselq
        assign  io_stall = 1'b0;
422
 
423
        wire    pwm_ack, pwm_stall;
424 12 dgisselq
        wbpwmaudio      #(14'd10000,2,0,14)
425
                theaudio(i_clk, wb_cyc,
426
                                ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
427
                                        wb_we, 1'b0, wb_data,
428
                                pwm_ack, pwm_stall, pwm_data, o_pwm,
429
                                        o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
430
                                        pwm_int);
431 2 dgisselq
 
432
        //
433
        // Special Purpose I/O: Keypad, button, LED status and control
434
        //
435 16 dgisselq
        wire    [3:0]    w_led;
436 46 dgisselq
        spio    thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),
437
                                wb_we, wb_data, spio_data,
438
                        o_kp_col, i_kp_row, i_btn, w_led,
439 2 dgisselq
                        keypad_int, button_int);
440 16 dgisselq
        assign  o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,w_led[1:0] };
441 2 dgisselq
 
442
        //
443
        // General purpose (sort of) I/O:  (Bottom two bits robbed in each
444
        // direction for an I2C link at the toplevel.v design)
445
        //
446
        wbgpio  #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
447
                        (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
448
                        wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
449
 
450
        //
451
        //
452 46 dgisselq
        //      UART device: our console
453
        //
454
        //
455
        wire    [30:0]   uart_setup;
456
        //
457
        wire    rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, rx_stb;
458
        wire    [7:0]    rx_data;
459
        //
460
        assign  uart_setup = UART_SETUP;
461
        //
462
        rxuart  #(UART_SETUP)
463
                rcvuart(i_clk, 1'b0, uart_setup, i_uart, rx_stb, rx_data,
464
                        rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
465
        //
466
        wire    tx_break, tx_busy;
467
        reg             tx_stb;
468
        reg     [7:0]    tx_data;
469
        assign  tx_break = 1'b0;
470
        txuart  #(UART_SETUP)
471
                tcvuart(i_clk, 1'b0, uart_setup, tx_break, tx_stb, tx_data,
472
                        i_uart_cts_n, o_uart, tx_busy);
473
 
474
        //
475 2 dgisselq
        //      Rudimentary serial port control
476
        //
477
        reg     [7:0]    r_rx_data;
478
        // Baud rate is set by clock rate / baud rate.
479
 
480 46 dgisselq
        initial tx_stb = 1'b0;
481
        initial tx_data = 8'h00;
482 2 dgisselq
        always @(posedge i_clk)
483 4 dgisselq
                if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
484 2 dgisselq
                begin
485 46 dgisselq
                        tx_data <= wb_data[7:0];
486
                        tx_stb <= 1'b1;
487 2 dgisselq
                end
488 46 dgisselq
                else if ((tx_stb)&&(!tx_busy))
489
                        tx_stb <= 1'b0;
490 2 dgisselq
        initial rx_rdy = 1'b0;
491
        always @(posedge i_clk)
492 46 dgisselq
                if (rx_stb)
493
                        r_rx_data <= rx_data;
494 2 dgisselq
        always @(posedge i_clk)
495
        begin
496 46 dgisselq
                if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(!wb_we))
497
                        rx_rdy <= rx_stb;
498
                else if (rx_stb)
499
                        rx_rdy <= (rx_rdy | rx_stb);
500 2 dgisselq
        end
501 46 dgisselq
        assign  o_uart_rts_n = (rx_rdy);
502
        assign  uart_data = { 23'h0, !rx_rdy, r_rx_data };
503 4 dgisselq
        //
504
        // uart_ack gets returned as part of io_ack, since that happens when
505
        // io_sel and wb_stb are defined
506
        //
507
        // always @(posedge i_clk)
508
                // uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
509 2 dgisselq
 
510
 
511
 
512
        //
513
        //      FLASH MEMORY CONFIGURATION ACCESS
514
        //
515 46 dgisselq
`ifdef  FLASH_ACCESS
516
        wbqspiflash #(LGFLASHSZ)        flashmem(i_clk,
517 11 dgisselq
                wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
518 46 dgisselq
                        wb_addr[(LGFLASHSZ-3):0], wb_data,
519 2 dgisselq
                flash_ack, flash_stall, flash_data,
520
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
521
                flash_interrupt);
522
`else
523 46 dgisselq
        reg     r_flash_ack;
524
        initial r_flash_ack = 1'b0;
525 2 dgisselq
        always @(posedge i_clk)
526 46 dgisselq
                r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
527
 
528
        assign  flash_ack = r_flash_ack;
529
        assign  flash_stall = 1'b0;
530
        assign  flash_data = 32'h0000;
531
        assign  flash_interrupt = 1'b0;
532
 
533
        assign  o_qspi_sck   = 1'b1;
534
        assign  o_qspi_cs_n  = 1'b1;
535
        assign  o_qspi_mod   = 2'b01;
536
        assign  o_qspi_dat   = 4'b1111;
537 2 dgisselq
`endif
538
 
539
        //
540
        //      ON-CHIP RAM MEMORY ACCESS
541
        //
542 4 dgisselq
`ifdef  IMPLEMENT_ONCHIP_RAM
543 46 dgisselq
        memdev  #(.LGMEMSZ(LGMEMSZ))
544
                ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
545
                        wb_addr[(LGMEMSZ-3):0], wb_data, wb_sel,
546
                        mem_ack, mem_stall, mem_data);
547 4 dgisselq
`else
548
        assign  mem_data = 32'h00;
549
        assign  mem_stall = 1'b0;
550
        reg     r_mem_ack;
551
        always @(posedge i_clk)
552 46 dgisselq
                r_mem_ack <= (wb_stb)&&(mem_sel);
553 4 dgisselq
        assign  mem_ack = r_mem_ack;
554
`endif
555 2 dgisselq
 
556
        //
557
        //
558
        //      WISHBONE SCOPE
559
        //
560
        //
561
        //
562
        //
563 46 dgisselq
        wire    [31:0]   scop_cpu_data;
564
        wire            scop_cpu_ack, scop_cpu_stall, scop_cpu_interrupt;
565 7 dgisselq
`ifdef  DBG_SCOPE
566 16 dgisselq
        wire    scop_trigger = (zip_cpu_int) || (cpu_reset);
567
`ifdef  COMPRESSED_SCOPE
568
        wbscopc #(5'ha)
569
`else
570 46 dgisselq
        wbscope #(.LGMEM(5'h6), .HOLDOFFBITS(9))
571 16 dgisselq
`endif
572 46 dgisselq
        cpuscope(i_clk, 1'b1, scop_trigger,
573 28 dgisselq
`ifdef  COMPRESSED_SCOPE
574
                // cfg_scope[30:0],
575 16 dgisselq
                zip_scope_data[30:0],
576 28 dgisselq
`else
577
                // cfg_scope[31:0],
578
                zip_scope_data[31:0],
579
`endif
580 2 dgisselq
                // Wishbone interface
581 4 dgisselq
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
582 2 dgisselq
                                wb_we, wb_addr[0], wb_data,
583 46 dgisselq
                        scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
584
                scop_cpu_interrupt);
585 4 dgisselq
`else
586 46 dgisselq
        reg     r_scop_cpu_ack;
587 4 dgisselq
        always @(posedge i_clk)
588 46 dgisselq
                r_scop_cpu_ack <= (wb_stb)&&(scop_sel);
589
        assign  scop_cpu_ack = r_scop_cpu_ack;
590
        assign  scop_cpu_data = 32'h000;
591
        assign  scop_cpu_stall= 1'b0;
592 2 dgisselq
`endif
593
 
594 46 dgisselq
        assign  scop_interrupt = scop_cpu_interrupt;
595
        assign  scop_ack   = scop_cpu_ack;
596
        assign  scop_stall = scop_cpu_stall;
597
        assign  scop_data  = scop_cpu_data;
598 2 dgisselq
 
599
endmodule
600
 

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