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lukasz.dzi |
--
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-- Copyright 2012 iQUBE research
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--
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-- This file is part of Salsa20IpCore.
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--
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-- Salsa20IpCore is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Salsa20IpCore is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Salsa20IpCore. If not, see <http://www.gnu.org/licenses/>.
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--
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-- contact: Rúa Fonte das Abelleiras s/n, Campus Universitario de Vigo, 36310, Vigo (Spain)
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-- e-mail: lukasz.dzianach@iqube.es, info@iqube.es
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.NUMERIC_STD.all;
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entity salsaa_dm is
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port (
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clk : in std_logic;
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reset : in std_logic;
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-- iface for user
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data : out std_logic_vector(31 downto 0);
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data_req : in std_logic;
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data_valid : out std_logic;
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-- iface to salsaa_mc
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mc_data : in std_logic_vector(511 downto 0);
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mc_restart : out std_logic;
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mc_busy : in std_logic
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);
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end entity salsaa_dm;
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architecture rtl of salsaa_dm is
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type reg_type is array(0 to 15) of std_logic_vector(31 downto 0);
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signal state : std_logic_vector (3 downto 0);
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signal reg : reg_type;
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signal reg_idx : std_logic_vector (3 downto 0);
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constant dm_rst : std_logic_vector := x"0";
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constant dm_wmc_dr : std_logic_vector := x"1";
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constant dm_wmc_ndr : std_logic_vector := x"2";
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constant dm_idl : std_logic_vector := x"3";
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constant dm_lmd : std_logic_vector := x"4";
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constant dm_lmdps : std_logic_vector := x"5";
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constant dm_ps : std_logic_vector := x"6";
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constant max_reg_idx : std_logic_vector := x"f";
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begin
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main: process(clk) is
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begin
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if (clk'event and clk='1') then
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if (reset='1') then
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state <= dm_rst;
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for Z in 0 to 15
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loop
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--reg(Z) <= mc_data(32 * Z + 31 downto 32 * Z + 0);
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reg(Z) <= x"00000000";
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end loop;
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data_valid <= '0';
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data <= x"00000000";
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reg_idx <= x"0";
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else
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case state is
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when dm_rst =>
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reg_idx <= x"0";
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data_valid <= '0';
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mc_restart <= '0';
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if mc_busy = '0' and data_req = '1' then
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state <= dm_lmdps;
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elsif data_req = '1' then
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state <= dm_wmc_dr;
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elsif mc_busy = '0' then
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state <= dm_lmd;
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end if;
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when dm_lmdps =>
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-- state to reg
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reg(00) <= mc_data(32 * 00 + 31 downto 32 * 00 + 0);
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reg(01) <= mc_data(32 * 01 + 31 downto 32 * 01 + 0);
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reg(02) <= mc_data(32 * 02 + 31 downto 32 * 02 + 0);
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reg(03) <= mc_data(32 * 03 + 31 downto 32 * 03 + 0);
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reg(04) <= mc_data(32 * 04 + 31 downto 32 * 04 + 0);
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reg(05) <= mc_data(32 * 05 + 31 downto 32 * 05 + 0);
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reg(06) <= mc_data(32 * 06 + 31 downto 32 * 06 + 0);
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reg(07) <= mc_data(32 * 07 + 31 downto 32 * 07 + 0);
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reg(08) <= mc_data(32 * 08 + 31 downto 32 * 08 + 0);
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reg(09) <= mc_data(32 * 09 + 31 downto 32 * 09 + 0);
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reg(10) <= mc_data(32 * 10 + 31 downto 32 * 10 + 0);
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reg(11) <= mc_data(32 * 11 + 31 downto 32 * 11 + 0);
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reg(12) <= mc_data(32 * 12 + 31 downto 32 * 12 + 0);
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reg(13) <= mc_data(32 * 13 + 31 downto 32 * 13 + 0);
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reg(14) <= mc_data(32 * 14 + 31 downto 32 * 14 + 0);
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reg(15) <= mc_data(32 * 15 + 31 downto 32 * 15 + 0);
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reg_idx <= reg_idx + x"1";
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data_valid <= '1';
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mc_restart <= '1';
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data <= mc_data(32 * 00 + 31 downto 32 * 00 + 0);
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if data_req = '1' then
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state <= dm_ps;
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else
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state <= dm_idl;
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end if;
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when dm_lmd =>
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-- state to reg
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reg(00) <= mc_data(32 * 00 + 31 downto 32 * 00 + 0);
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reg(01) <= mc_data(32 * 01 + 31 downto 32 * 01 + 0);
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reg(02) <= mc_data(32 * 02 + 31 downto 32 * 02 + 0);
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reg(03) <= mc_data(32 * 03 + 31 downto 32 * 03 + 0);
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reg(04) <= mc_data(32 * 04 + 31 downto 32 * 04 + 0);
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reg(05) <= mc_data(32 * 05 + 31 downto 32 * 05 + 0);
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reg(06) <= mc_data(32 * 06 + 31 downto 32 * 06 + 0);
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reg(07) <= mc_data(32 * 07 + 31 downto 32 * 07 + 0);
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reg(08) <= mc_data(32 * 08 + 31 downto 32 * 08 + 0);
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reg(09) <= mc_data(32 * 09 + 31 downto 32 * 09 + 0);
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reg(10) <= mc_data(32 * 10 + 31 downto 32 * 10 + 0);
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reg(11) <= mc_data(32 * 11 + 31 downto 32 * 11 + 0);
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reg(12) <= mc_data(32 * 12 + 31 downto 32 * 12 + 0);
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reg(13) <= mc_data(32 * 13 + 31 downto 32 * 13 + 0);
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reg(14) <= mc_data(32 * 14 + 31 downto 32 * 14 + 0);
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reg(15) <= mc_data(32 * 15 + 31 downto 32 * 15 + 0);
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reg_idx <= x"0";
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data_valid <= '0';
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mc_restart <= '1';
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if data_req = '1' then
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state <= dm_ps;
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else
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state <= dm_idl;
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end if;
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when dm_ps =>
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-- loading data to output
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data <= reg(to_integer(unsigned(reg_idx)));
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data_valid <= '1';
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-- mc should not restart in this state
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mc_restart <= '0';
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-- moving reg_idx
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if reg_idx = max_reg_idx then
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reg_idx <= x"0";
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else
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reg_idx <= reg_idx + x"1";
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end if;
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-- selecting next state
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if reg_idx = max_reg_idx then
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-- considering the situation when the last reg_idx
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if data_req = '0' and mc_busy = '0' then
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state <= dm_lmd;
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elsif data_req = '0' and mc_busy = '1' then
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state <= dm_wmc_ndr;
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elsif data_req = '1' and mc_busy = '0' then
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state <= dm_lmdps;
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elsif data_req = '1' and mc_busy = '1' then
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state <= dm_wmc_dr;
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end if;
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else
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-- considering typical situation
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if data_req = '1' then
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state <= dm_ps;
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elsif data_req = '0' then
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state <= dm_idl;
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end if;
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end if;
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when dm_idl =>
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-- no valid data
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data_valid <= '0';
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-- mc should not restart in this state
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mc_restart <= '0';
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-- selecting next state CHECK THIS CODE
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if data_req = '1' then
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state <= dm_ps;
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elsif data_req = '0' then
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state <= dm_idl;
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end if;
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when dm_wmc_dr =>
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-- no valid data
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data_valid <= '0';
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-- mc should not restart in this state
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mc_restart <= '0';
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-- sett to the beginning of data register
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reg_idx <= x"0";
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-- selecting next state
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if mc_busy = '0' then
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state <= dm_lmdps;
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end if;
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when dm_wmc_ndr =>
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-- no valid data
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data_valid <= '0';
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-- mc should not restart in this state
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mc_restart <= '0';
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-- set to the beginning of data register
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reg_idx <= x"0";
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-- selecting next state
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if mc_busy = '0' and data_req = '0' then
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state <= dm_lmd;
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elsif mc_busy = '0' and data_req = '1' then
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state <= dm_lmdps;
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elsif mc_busy = '1' and data_req = '0' then
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state <= dm_wmc_ndr;
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elsif mc_busy = '1' and data_req = '1' then
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state <= dm_wmc_dr;
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end if;
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when others =>
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null;
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end case;
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end if;
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end if;
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end process;
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end architecture rtl;
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