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lukasz.dzi |
--
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-- Copyright 2012 iQUBE research
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--
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-- This file is part of Salsa20IpCore.
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--
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-- Salsa20IpCore is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Salsa20IpCore is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Salsa20IpCore. If not, see <http://www.gnu.org/licenses/>.
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--
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-- contact: Rúa Fonte das Abelleiras s/n, Campus Universitario de Vigo, 36310, Vigo (Spain)
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-- e-mail: lukasz.dzianach@iqube.es, info@iqube.es
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.NUMERIC_STD.all;
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use IEEE.std_logic_unsigned.all;
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entity salsaa_mc is
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port (
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clk : in std_logic;
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reset : in std_logic;
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-- iface for user
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key : in std_logic_vector(255 downto 0);
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nonce : in std_logic_vector(63 downto 0);
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start : in std_logic;
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-- iface to salsaa_dm
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mc_data : out std_logic_vector(511 downto 0);
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mc_restart : in std_logic := '0';
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mc_busy : out std_logic
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);
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end entity salsaa_mc;
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architecture rtl of salsaa_mc is
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type x_type is array(0 to 15) of std_logic_vector(31 downto 0);
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constant salsa_const_0 : std_logic_vector := x"61707865";
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constant salsa_const_1 : std_logic_vector := x"3320646e";
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constant salsa_const_2 : std_logic_vector := x"79622d32";
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constant salsa_const_3 : std_logic_vector := x"6b206574";
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constant st_rst : std_logic_vector := x"0";
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constant st_read_in : std_logic_vector := x"1";
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constant st_save_init : std_logic_vector := x"2";
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constant st_perf_rnds : std_logic_vector := x"3";
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constant st_sum_res : std_logic_vector := x"4";
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constant st_calc_done : std_logic_vector := x"5";
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constant max_calc_state : std_logic_vector (7 downto 0) := x"07";
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constant max_rnds_state : std_logic_vector (7 downto 0) := x"09";
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signal x : x_type;
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signal idx : std_logic_vector (63 downto 0);
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signal state : std_logic_vector (3 downto 0);
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signal calc_state : std_logic_vector (7 downto 0);
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signal rnds_state : std_logic_vector (7 downto 0);
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signal mc_data_buf : std_logic_vector(511 downto 0);
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begin
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mc_data <= mc_data_buf;
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main: process(clk) is
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begin
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if (clk'event and clk='1') then
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if (reset='1') then
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state <= st_rst;
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mc_busy <= '1';
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else
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case state is
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when st_rst =>
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if start = '1' then
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state <= st_read_in;
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end if;
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-- reseting the index (as new nonce can is being read)
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idx <= x"0000000000000000";
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mc_busy <= '1';
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when st_read_in =>
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state <= st_save_init;
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mc_busy <= '1';
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x(0) <= salsa_const_0;
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x(1) <= key(32 * 0 + 31 downto 32 * 0 + 0);
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x(2) <= key(32 * 1 + 31 downto 32 * 1 + 0);
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x(3) <= key(32 * 2 + 31 downto 32 * 2 + 0);
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x(4) <= key(32 * 3 + 31 downto 32 * 3 + 0);
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x(5) <= salsa_const_1;
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x(6) <= nonce(32 * 0 + 31 downto 32 * 0 + 0);
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x(7) <= nonce(32 * 1 + 31 downto 32 * 1 + 0);
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x(8) <= idx(32 * 0 + 31 downto 32 * 0 + 0);
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x(9) <= idx(32 * 1 + 31 downto 32 * 1 + 0);
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x(10) <= salsa_const_2;
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x(11) <= key(32 * 4 + 31 downto 32 * 4 + 0);
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x(12) <= key(32 * 5 + 31 downto 32 * 5 + 0);
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x(13) <= key(32 * 6 + 31 downto 32 * 6 + 0);
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x(14) <= key(32 * 7 + 31 downto 32 * 7 + 0);
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x(15) <= salsa_const_3;
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when st_save_init =>
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-- prepare seq of runds
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state <= st_perf_rnds;
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calc_state <= x"00";
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rnds_state <= x"00";
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-- storing initial state of x
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mc_data_buf(32 * 00 + 31 downto 32 * 00 + 0) <= x(00);
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mc_data_buf(32 * 01 + 31 downto 32 * 01 + 0) <= x(01);
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mc_data_buf(32 * 02 + 31 downto 32 * 02 + 0) <= x(02);
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mc_data_buf(32 * 03 + 31 downto 32 * 03 + 0) <= x(03);
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mc_data_buf(32 * 04 + 31 downto 32 * 04 + 0) <= x(04);
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mc_data_buf(32 * 05 + 31 downto 32 * 05 + 0) <= x(05);
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mc_data_buf(32 * 06 + 31 downto 32 * 06 + 0) <= x(06);
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mc_data_buf(32 * 07 + 31 downto 32 * 07 + 0) <= x(07);
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mc_data_buf(32 * 08 + 31 downto 32 * 08 + 0) <= x(08);
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mc_data_buf(32 * 09 + 31 downto 32 * 09 + 0) <= x(09);
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mc_data_buf(32 * 10 + 31 downto 32 * 10 + 0) <= x(10);
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mc_data_buf(32 * 11 + 31 downto 32 * 11 + 0) <= x(11);
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mc_data_buf(32 * 12 + 31 downto 32 * 12 + 0) <= x(12);
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mc_data_buf(32 * 13 + 31 downto 32 * 13 + 0) <= x(13);
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mc_data_buf(32 * 14 + 31 downto 32 * 14 + 0) <= x(14);
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mc_data_buf(32 * 15 + 31 downto 32 * 15 + 0) <= x(15);
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when st_perf_rnds =>
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calc_state <= calc_state + x"01";
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if calc_state = max_calc_state then
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if rnds_state = max_rnds_state then
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state <= st_sum_res;
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else
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calc_state <= x"00";
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rnds_state <= rnds_state + x"01";
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end if;
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end if;
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-- processing goes here
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case calc_state is
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when x"00" =>
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x(04) <= x(04) xor std_logic_vector( rotate_left(unsigned(x(12)+x(00)),7));
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x(09) <= x(09) xor std_logic_vector( rotate_left(unsigned(x(01)+x(05)),7));
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x(14) <= x(14) xor std_logic_vector( rotate_left(unsigned(x(06)+x(10)),7));
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x(03) <= x(03) xor std_logic_vector( rotate_left(unsigned(x(11)+x(15)),7));
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when x"01" =>
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x(08) <= x(08) xor std_logic_vector( rotate_left(unsigned(x(00)+x(04)),9));
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x(13) <= x(13) xor std_logic_vector( rotate_left(unsigned(x(05)+x(09)),9));
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x(02) <= x(02) xor std_logic_vector( rotate_left(unsigned(x(10)+x(14)),9));
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x(07) <= x(07) xor std_logic_vector( rotate_left(unsigned(x(15)+x(03)),9));
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when x"02" =>
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x(12) <= x(12) xor std_logic_vector( rotate_left(unsigned(x(04)+x(08)),13));
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x(01) <= x(01) xor std_logic_vector( rotate_left(unsigned(x(09)+x(13)),13));
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x(06) <= x(06) xor std_logic_vector( rotate_left(unsigned(x(14)+x(02)),13));
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x(11) <= x(11) xor std_logic_vector( rotate_left(unsigned(x(03)+x(07)),13));
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when x"03" =>
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x(00) <= x(00) xor std_logic_vector( rotate_left(unsigned(x(08)+x(12)),18));
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x(05) <= x(05) xor std_logic_vector( rotate_left(unsigned(x(13)+x(01)),18));
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x(10) <= x(10) xor std_logic_vector( rotate_left(unsigned(x(02)+x(06)),18));
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x(15) <= x(15) xor std_logic_vector( rotate_left(unsigned(x(07)+x(11)),18));
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when x"04" =>
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x(01) <= x(01) xor std_logic_vector( rotate_left(unsigned(x(03)+x(00)),07));
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x(06) <= x(06) xor std_logic_vector( rotate_left(unsigned(x(04)+x(05)),07));
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x(11) <= x(11) xor std_logic_vector( rotate_left(unsigned(x(09)+x(10)),07));
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x(12) <= x(12) xor std_logic_vector( rotate_left(unsigned(x(14)+x(15)),07));
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when x"05" =>
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x(02) <= x(02) xor std_logic_vector( rotate_left(unsigned(x(00)+x(01)),09));
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x(07) <= x(07) xor std_logic_vector( rotate_left(unsigned(x(05)+x(06)),09));
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x(08) <= x(08) xor std_logic_vector( rotate_left(unsigned(x(10)+x(11)),09));
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x(13) <= x(13) xor std_logic_vector( rotate_left(unsigned(x(15)+x(12)),09));
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when x"06" =>
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x(03) <= x(03) xor std_logic_vector( rotate_left(unsigned(x(01)+x(02)),13));
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x(04) <= x(04) xor std_logic_vector( rotate_left(unsigned(x(06)+x(07)),13));
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x(09) <= x(09) xor std_logic_vector( rotate_left(unsigned(x(11)+x(08)),13));
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x(14) <= x(14) xor std_logic_vector( rotate_left(unsigned(x(12)+x(13)),13));
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when x"07" =>
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x(00) <= x(00) xor std_logic_vector( rotate_left(unsigned(x(02)+x(03)),18));
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x(05) <= x(05) xor std_logic_vector( rotate_left(unsigned(x(07)+x(04)),18));
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x(10) <= x(10) xor std_logic_vector( rotate_left(unsigned(x(08)+x(09)),18));
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x(15) <= x(15) xor std_logic_vector( rotate_left(unsigned(x(13)+x(14)),18));
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when others =>
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null;
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end case;
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when st_sum_res =>
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-- preparing index for the next random block reneration
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idx <= idx + x"0000000000000001";
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mc_data_buf(32 * 00 + 31 downto 32 * 00 + 0) <= mc_data_buf(32 * 00 + 31 downto 32 * 00 + 0) + x(00);
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mc_data_buf(32 * 01 + 31 downto 32 * 01 + 0) <= mc_data_buf(32 * 01 + 31 downto 32 * 01 + 0) + x(01);
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mc_data_buf(32 * 02 + 31 downto 32 * 02 + 0) <= mc_data_buf(32 * 02 + 31 downto 32 * 02 + 0) + x(02);
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mc_data_buf(32 * 03 + 31 downto 32 * 03 + 0) <= mc_data_buf(32 * 03 + 31 downto 32 * 03 + 0) + x(03);
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mc_data_buf(32 * 04 + 31 downto 32 * 04 + 0) <= mc_data_buf(32 * 04 + 31 downto 32 * 04 + 0) + x(04);
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mc_data_buf(32 * 05 + 31 downto 32 * 05 + 0) <= mc_data_buf(32 * 05 + 31 downto 32 * 05 + 0) + x(05);
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mc_data_buf(32 * 06 + 31 downto 32 * 06 + 0) <= mc_data_buf(32 * 06 + 31 downto 32 * 06 + 0) + x(06);
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mc_data_buf(32 * 07 + 31 downto 32 * 07 + 0) <= mc_data_buf(32 * 07 + 31 downto 32 * 07 + 0) + x(07);
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mc_data_buf(32 * 08 + 31 downto 32 * 08 + 0) <= mc_data_buf(32 * 08 + 31 downto 32 * 08 + 0) + x(08);
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mc_data_buf(32 * 09 + 31 downto 32 * 09 + 0) <= mc_data_buf(32 * 09 + 31 downto 32 * 09 + 0) + x(09);
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mc_data_buf(32 * 10 + 31 downto 32 * 10 + 0) <= mc_data_buf(32 * 10 + 31 downto 32 * 10 + 0) + x(10);
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mc_data_buf(32 * 11 + 31 downto 32 * 11 + 0) <= mc_data_buf(32 * 11 + 31 downto 32 * 11 + 0) + x(11);
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mc_data_buf(32 * 12 + 31 downto 32 * 12 + 0) <= mc_data_buf(32 * 12 + 31 downto 32 * 12 + 0) + x(12);
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mc_data_buf(32 * 13 + 31 downto 32 * 13 + 0) <= mc_data_buf(32 * 13 + 31 downto 32 * 13 + 0) + x(13);
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mc_data_buf(32 * 14 + 31 downto 32 * 14 + 0) <= mc_data_buf(32 * 14 + 31 downto 32 * 14 + 0) + x(14);
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mc_data_buf(32 * 15 + 31 downto 32 * 15 + 0) <= mc_data_buf(32 * 15 + 31 downto 32 * 15 + 0) + x(15);
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mc_busy <= '0';
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state <= st_calc_done;
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when st_calc_done =>
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if mc_restart = '1' then
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-- new block requested with new input
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state <= st_read_in;
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end if;
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when others =>
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null;
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end case;
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end if;
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end if;
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end process;
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end architecture rtl;
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