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[/] [sata_phy/] [trunk/] [hdl/] [sata_phy_dev_ctrl_x6series.v] - Blame information for rev 11

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////////////////////////////////////////////////////////////
//
// This confidential and proprietary software may be used
// only as authorized by a licensing agreement from
// Bean Digital Ltd
// In the event of publication, the following notice is
// applicable:
//
// (C)COPYRIGHT 2012 BEAN DIGITAL LTD.
// ALL RIGHTS RESERVED
//
// The entire notice above must be reproduced on all
// authorized copies.
//
// File        : sata_phy_dev_ctrl_x6series.v
// Author      : J.Bean
// Date        : Mar 2012
// Description : SATA PHY Layer Device Control Xilinx 6 Series
////////////////////////////////////////////////////////////
 
`resetall
`timescale 1ns/10ps
 
`include "sata_constants.v"
 
module sata_phy_dev_ctrl_x6series
  #(parameter SATA_REV = 1)(              // SATA Revision (1, 2, 3)
  input  wire         clk_phy,             // Clock PHY
  input  wire         rst_n,                 // Reset
  output reg          link_up_o,          // Link Up     
  // Transceiver  
  input  wire         gt_rst_done_i,      // GT Reset Done
  output reg  [31:0]  gt_tx_data_o,            // GT Transmit Data
  output reg  [3:0]   gt_tx_charisk_o,      // GT Transmit K/D
  output reg          gt_tx_com_strt_o,   // GT Transmit        COM Start
  output reg          gt_tx_com_type_o,   // GT Transmit COM Type
  output reg          gt_tx_elec_idle_o,  // GT Transmit Electrical Idle                           
  input  wire [31:0]  gt_rx_data_i,       // GT Receive Data                
  input  wire [2:0]   gt_rx_status_i      // GT Receive Status
);
 
////////////////////////////////////////////////////////////
// Parameters
//////////////////////////////////////////////////////////// 
 
// Time delays
parameter SATA1_10MS            = 750000;   // 75MHz * 750000
parameter SATA2_10MS            = 1500000;  // 150MHz * 1500000
parameter SATA3_10MS            = 3000000;  // 300MHz * 3000000
parameter SATA1_55US            = 4095;     // 75MHz * 4095
parameter SATA2_55US            = 8190;     // 150MHz * 8190
parameter SATA3_55US            = 16380;    // 300MHz * 16380
 
// State machine states
parameter DP1_RESET             = 0;
parameter DP2_COMINIT           = 1;
parameter DP3_AWAIT_COMWAKE     = 2;
parameter DP3B_AWAIT_NO_COMWAKE = 3;
parameter DP4_CALIBRATE         = 4;
parameter DP5_COMWAKE           = 5;
parameter DP6_SEND_ALIGN        = 6;
parameter DP7_READY             = 7;
parameter DP11_ERROR            = 8;
 
////////////////////////////////////////////////////////////
// Signals
//////////////////////////////////////////////////////////// 
 
reg  [3:0]   state_cs;          // Current state
reg  [3:0]   state_ns;          // Next state  
reg  [199:0] state_ascii;       // ASCII state
reg      [31:0]   align_timeout_cnt; // ALIGN Timeout Count
reg  [31:0]  retry_cnt;         // Retry Count 
wire         comreset_detect;   // COMRESET Detect
wire         comwake_detect;    // COMWAKE Detect
wire         align_detect;      // ALIGN Detected
reg          tx_com_strt;       // Transmit COM Start
wire         tx_com_strt_pedge; // Transmit COM Start Positive Edge
reg          tx_com_done;       // Transmit COM Done
 
////////////////////////////////////////////////////////////
// Instance    : Transmit Com Start Pos Edge
// Description : Detect positive edge on COM start signal.
////////////////////////////////////////////////////////////
 
det_pos_edge U_tx_com_strt_pedge(
  .clk   (clk_phy),
  .rst_n (rst_n),
  .d     (tx_com_strt),
  .q     (tx_com_strt_pedge));
 
////////////////////////////////////////////////////////////
// Comb Assign : ALIGN primitive detect
// Description : 
////////////////////////////////////////////////////////////
 
assign align_detect = (gt_rx_data_i == 32'h7B4A4ABC);
 
////////////////////////////////////////////////////////////
// Comb Assign : COMWAKE Detect
// Description : 
////////////////////////////////////////////////////////////
 
assign comwake_detect = gt_rx_status_i[1];
 
////////////////////////////////////////////////////////////
// Comb Assign : COMRESET Detect
// Description : 
////////////////////////////////////////////////////////////
 
assign comreset_detect = gt_rx_status_i[2];
 
////////////////////////////////////////////////////////////
// Seq Block   : State machine seq logic
// Description : Sets the current state to the next state.
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    state_cs <= DP1_RESET;
  end else begin
    if (comreset_detect == 1) begin
      state_cs <= DP1_RESET;
    end else begin
      state_cs <= state_ns;
    end
  end
end
 
////////////////////////////////////////////////////////////
// Comb Block  : State machine ascii 
// Description : Converts the state to ascii for debug.
////////////////////////////////////////////////////////////
 
always @(*)
begin
  case (state_cs)
    DP1_RESET:             state_ascii = "DP1_RESET";
    DP2_COMINIT:           state_ascii = "DP2_COMINIT";
    DP3_AWAIT_COMWAKE:     state_ascii = "DP3_AWAIT_COMWAKE";
    DP3B_AWAIT_NO_COMWAKE: state_ascii = "DP3B_AWAIT_NO_COMWAKE";
    DP4_CALIBRATE:         state_ascii = "DP4_CALIBRATE";
    DP5_COMWAKE:           state_ascii = "DP5_COMWAKE";
    DP6_SEND_ALIGN:        state_ascii = "DP6_SEND_ALIGN";
    DP7_READY:             state_ascii = "DP7_READY";
    DP11_ERROR:            state_ascii = "DP11_ERROR";
  endcase
end
 
////////////////////////////////////////////////////////////
// Comb Block  : State machine comb logic
// Description : Assigns the next state.
////////////////////////////////////////////////////////////
 
always @(*)
begin
  state_ns = state_cs;
 
  case (state_cs)
    // DP1_RESET - Interface quiescent
    DP1_RESET: begin
      if ((gt_rst_done_i == 1) && (comreset_detect == 0)) begin
        state_ns = DP2_COMINIT;
      end
    end
 
    // DP2_COMINIT - Send COMINIT
    DP2_COMINIT: begin
      if (tx_com_done == 1) begin
        state_ns = DP3_AWAIT_COMWAKE;
      end
    end
 
    // DP3_AWAIT_COMWAKE - Wait for COMWAKE to be detected
    DP3_AWAIT_COMWAKE: begin
      if (comwake_detect == 1) begin
        state_ns = DP3B_AWAIT_NO_COMWAKE;
      end else begin
        if (retry_cnt == 0) begin
          state_ns = DP1_RESET;
        end
      end
    end
 
    // DP3B_AWAIT_NO_COMWAKE - Wait for COMWAKE to finish
    DP3B_AWAIT_NO_COMWAKE: begin
      if (comwake_detect == 0) begin
        state_ns = DP4_CALIBRATE;
      end
    end
 
    // DP4_CALIBRATE 
    DP4_CALIBRATE: begin
      state_ns = DP5_COMWAKE;
    end
 
    // DP5_COMWAKE - Send COMWAKE
    DP5_COMWAKE: begin
      if (tx_com_done == 1) begin
        state_ns = DP6_SEND_ALIGN;
      end
    end
 
    // DP6_SEND_ALIGN - Send ALIGN
    DP6_SEND_ALIGN: begin
      if (align_detect == 1) begin
        state_ns = DP7_READY;
      end else begin
        if (align_timeout_cnt == 0) begin
          state_ns = DP11_ERROR;
        end
      end
    end
 
    // DP7_READY - Link ready
    DP7_READY: begin
      state_ns = DP7_READY;
    end
 
    // DP11_ERROR
    DP11_ERROR: begin
      state_ns = DP1_RESET;
    end
 
    default: begin
      state_ns = 'bx;
    end
  endcase
end
 
////////////////////////////////////////////////////////////
// Seq Block   : Link Up
// Description : Set when communication has been established
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    link_up_o <= 0;
  end   else begin
    case (state_cs)
      // DP7_READY - Link ready
      DP7_READY: begin
        link_up_o <= 1;
      end
 
      default: begin
        link_up_o <= 0;
      end
    endcase
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : GT Transmit COM Start
// Description : 
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    gt_tx_com_strt_o <= 0;
  end   else begin
    gt_tx_com_strt_o <= tx_com_strt_pedge;
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : Transmit COM Type
// Description : 
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    gt_tx_com_type_o <= 0;
  end   else begin
    case (state_cs)
      // DP2_COMINIT - Send COMINIT
      DP2_COMINIT: begin
        gt_tx_com_type_o <= 0;
      end
 
      // DP5_COMWAKE - Send COMWAKE
      DP5_COMWAKE: begin
        gt_tx_com_type_o <= 1;
      end
    endcase
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : GT Transmit Electrical Idle
// Description : 
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    gt_tx_elec_idle_o <= 0;
  end   else begin
    case (state_cs)
      // DP5_COMWAKE - Send COMWAKE
      DP5_COMWAKE: begin
        if (tx_com_done == 1) begin
          gt_tx_elec_idle_o <= 0;
        end
      end
 
      // DP6_SEND_ALIGN - Send ALIGN
      DP6_SEND_ALIGN: begin
        gt_tx_elec_idle_o <= 0;
      end
 
      // DP7_READY - Link ready
      DP7_READY: begin
        gt_tx_elec_idle_o <= 0;
      end
 
      default: begin
        gt_tx_elec_idle_o <= 1;
      end
    endcase
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : GT Transmit Data
// Description : 
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    gt_tx_data_o <= 0;
  end   else begin
    case (state_cs)
      // DP6_SEND_ALIGN - Send ALIGN
      DP6_SEND_ALIGN: begin
        gt_tx_data_o <= `ALIGN_VAL; // ALIGN;        
      end
 
      // DP7_READY - Link ready
      DP7_READY: begin
        gt_tx_data_o <= `SYNC_VAL;  // SYNC;     
      end
 
      default: begin
        gt_tx_data_o <= 0;
      end
    endcase
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : GT Transmit K/D
// Description : 
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    gt_tx_charisk_o <= 0;
  end   else begin
    case (state_cs)
      // DP6_SEND_ALIGN - Send ALIGN
      DP6_SEND_ALIGN: begin
        gt_tx_charisk_o <= 4'b0001; // ALIGN;        
      end
 
      // DP7_READY - Link ready
      DP7_READY: begin
        gt_tx_charisk_o <= 4'b0001; // SYNC;     
      end
 
      default: begin
        gt_tx_charisk_o <= 0;
      end
    endcase
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : Transmit COM Start
// Description : Starts transmission of a COM sequence.
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    tx_com_strt <= 0;
  end   else begin
    case (state_cs)
      // DP2_COMINIT - Send COMINIT
      DP2_COMINIT: begin
        tx_com_strt <= 1;
      end
 
      // DP5_COMWAKE - Send COMWAKE
      DP5_COMWAKE: begin
        tx_com_strt <= 1;
      end
 
      default: begin
        tx_com_strt <= 0;
      end
    endcase
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : Transmit COM Done
// Description : 
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    tx_com_done <= 0;
  end   else begin
    case (state_cs)
      // DP1_RESET - Interface quiescent
      DP1_RESET: begin
        tx_com_done <= 0;
      end
 
      // DP2_COMINIT - Send COMINIT
      DP2_COMINIT: begin
        if (gt_rx_status_i[0] == 1) begin
          tx_com_done <= 1;
        end
      end
 
      // DP5_COMWAKE - Send COMWAKE
      DP5_COMWAKE: begin
        if (gt_rx_status_i[0] == 1) begin
          tx_com_done <= 1;
        end
      end
 
      default: begin
        tx_com_done <= 0;
      end
    endcase
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : ALIGN Timeout Count
// Description : Error if ALIGN not detected within 54.6us.
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
                align_timeout_cnt <= 0;
        end     else begin
    case (state_cs)
      // DP1_RESET - Interface quiescent
      DP1_RESET: begin
        case (SATA_REV)
          1:       align_timeout_cnt <= SATA1_55US;
          2:       align_timeout_cnt <= SATA2_55US;
          3:       align_timeout_cnt <= SATA3_55US;
          default: align_timeout_cnt <= SATA1_55US;
        endcase
      end
 
      // DP6_SEND_ALIGN - Send ALIGN
      DP6_SEND_ALIGN: begin
        align_timeout_cnt <= align_timeout_cnt - 1;
      end
          endcase
        end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : Retry Count
// Description : Used to for async signal recovery (10 ms)
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
                retry_cnt <= 0;
        end     else begin
          case (state_cs)
      // DP1_RESET - Interface quiescent
      DP1_RESET: begin
        case (SATA_REV)
          1:       retry_cnt <= SATA1_10MS;
          2:       retry_cnt <= SATA2_10MS;
          3:       retry_cnt <= SATA3_10MS;
          default: retry_cnt <= SATA1_10MS;
        endcase
      end
 
      // DP3_AWAIT_COMWAKE - Wait for COMWAKE to be detected
      DP3_AWAIT_COMWAKE: begin
        retry_cnt <= retry_cnt - 1;
      end
    endcase
        end
end
 
endmodule

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[/] [sata_phy/] [trunk/] [hdl/] [sata_phy_dev_ctrl_x6series.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	beandigita	`////////////////////////////////////////////////////////////`
2			`//`
3			`// This confidential and proprietary software may be used`
4			`// only as authorized by a licensing agreement from`
5			`// Bean Digital Ltd`
6			`// In the event of publication, the following notice is`
7			`// applicable:`
8			`//`
9			`// (C)COPYRIGHT 2012 BEAN DIGITAL LTD.`
10			`// ALL RIGHTS RESERVED`
11			`//`
12			`// The entire notice above must be reproduced on all`
13			`// authorized copies.`
14			`//`
15			`// File : sata_phy_dev_ctrl_x6series.v`
16			`// Author : J.Bean`
17			`// Date : Mar 2012`
18			`// Description : SATA PHY Layer Device Control Xilinx 6 Series`
19			`////////////////////////////////////////////////////////////`
20
21			`resetall
22			`timescale 1ns/10ps
23
24			`include "sata_constants.v"
25
26			`module sata_phy_dev_ctrl_x6series`
27			`#(parameter SATA_REV = 1)( // SATA Revision (1, 2, 3)`
28			`input wire clk_phy, // Clock PHY`
29			`input wire rst_n, // Reset`
30			`output reg link_up_o, // Link Up`
31			`// Transceiver`
32			`input wire gt_rst_done_i, // GT Reset Done`
33			`output reg [31:0] gt_tx_data_o, // GT Transmit Data`
34			`output reg [3:0] gt_tx_charisk_o, // GT Transmit K/D`
35			`output reg gt_tx_com_strt_o, // GT Transmit COM Start`
36			`output reg gt_tx_com_type_o, // GT Transmit COM Type`
37			`output reg gt_tx_elec_idle_o, // GT Transmit Electrical Idle`
38			`input wire [31:0] gt_rx_data_i, // GT Receive Data`
39			`input wire [2:0] gt_rx_status_i // GT Receive Status`
40			`);`
41
42			`////////////////////////////////////////////////////////////`
43			`// Parameters`
44			`////////////////////////////////////////////////////////////`
45
46			`// Time delays`
47			`parameter SATA1_10MS = 750000; // 75MHz * 750000`
48			`parameter SATA2_10MS = 1500000; // 150MHz * 1500000`
49			`parameter SATA3_10MS = 3000000; // 300MHz * 3000000`
50			`parameter SATA1_55US = 4095; // 75MHz * 4095`
51			`parameter SATA2_55US = 8190; // 150MHz * 8190`
52			`parameter SATA3_55US = 16380; // 300MHz * 16380`
53
54			`// State machine states`
55			`parameter DP1_RESET = 0;`
56			`parameter DP2_COMINIT = 1;`
57			`parameter DP3_AWAIT_COMWAKE = 2;`
58			`parameter DP3B_AWAIT_NO_COMWAKE = 3;`
59			`parameter DP4_CALIBRATE = 4;`
60			`parameter DP5_COMWAKE = 5;`
61			`parameter DP6_SEND_ALIGN = 6;`
62			`parameter DP7_READY = 7;`
63			`parameter DP11_ERROR = 8;`
64
65			`////////////////////////////////////////////////////////////`
66			`// Signals`
67			`////////////////////////////////////////////////////////////`
68
69			`reg [3:0] state_cs; // Current state`
70			`reg [3:0] state_ns; // Next state`
71			`reg [199:0] state_ascii; // ASCII state`
72			`reg [31:0] align_timeout_cnt; // ALIGN Timeout Count`
73			`reg [31:0] retry_cnt; // Retry Count`
74			`wire comreset_detect; // COMRESET Detect`
75			`wire comwake_detect; // COMWAKE Detect`
76			`wire align_detect; // ALIGN Detected`
77			`reg tx_com_strt; // Transmit COM Start`
78			`wire tx_com_strt_pedge; // Transmit COM Start Positive Edge`
79			`reg tx_com_done; // Transmit COM Done`
80
81			`////////////////////////////////////////////////////////////`
82			`// Instance : Transmit Com Start Pos Edge`
83			`// Description : Detect positive edge on COM start signal.`
84			`////////////////////////////////////////////////////////////`
85
86			`det_pos_edge U_tx_com_strt_pedge(`
87			`.clk (clk_phy),`
88			`.rst_n (rst_n),`
89			`.d (tx_com_strt),`
90			`.q (tx_com_strt_pedge));`
91
92			`////////////////////////////////////////////////////////////`
93			`// Comb Assign : ALIGN primitive detect`
94			`// Description :`
95			`////////////////////////////////////////////////////////////`
96
97			`assign align_detect = (gt_rx_data_i == 32'h7B4A4ABC);`
98
99			`////////////////////////////////////////////////////////////`
100			`// Comb Assign : COMWAKE Detect`
101			`// Description :`
102			`////////////////////////////////////////////////////////////`
103
104			`assign comwake_detect = gt_rx_status_i[1];`
105
106			`////////////////////////////////////////////////////////////`
107			`// Comb Assign : COMRESET Detect`
108			`// Description :`
109			`////////////////////////////////////////////////////////////`
110
111			`assign comreset_detect = gt_rx_status_i[2];`
112
113			`////////////////////////////////////////////////////////////`
114			`// Seq Block : State machine seq logic`
115			`// Description : Sets the current state to the next state.`
116			`////////////////////////////////////////////////////////////`
117
118			`always @(negedge rst_n or posedge clk_phy)`
119			`begin`
120			`if (rst_n == 0) begin`
121			`state_cs <= DP1_RESET;`
122			`end else begin`
123			`if (comreset_detect == 1) begin`
124			`state_cs <= DP1_RESET;`
125			`end else begin`
126			`state_cs <= state_ns;`
127			`end`
128			`end`
129			`end`
130
131			`////////////////////////////////////////////////////////////`
132			`// Comb Block : State machine ascii`
133			`// Description : Converts the state to ascii for debug.`
134			`////////////////////////////////////////////////////////////`
135
136			`always @(*)`
137			`begin`
138			`case (state_cs)`
139			`DP1_RESET: state_ascii = "DP1_RESET";`
140			`DP2_COMINIT: state_ascii = "DP2_COMINIT";`
141			`DP3_AWAIT_COMWAKE: state_ascii = "DP3_AWAIT_COMWAKE";`
142			`DP3B_AWAIT_NO_COMWAKE: state_ascii = "DP3B_AWAIT_NO_COMWAKE";`
143			`DP4_CALIBRATE: state_ascii = "DP4_CALIBRATE";`
144			`DP5_COMWAKE: state_ascii = "DP5_COMWAKE";`
145			`DP6_SEND_ALIGN: state_ascii = "DP6_SEND_ALIGN";`
146			`DP7_READY: state_ascii = "DP7_READY";`
147			`DP11_ERROR: state_ascii = "DP11_ERROR";`
148			`endcase`
149			`end`
150
151			`////////////////////////////////////////////////////////////`
152			`// Comb Block : State machine comb logic`
153			`// Description : Assigns the next state.`
154			`////////////////////////////////////////////////////////////`
155
156			`always @(*)`
157			`begin`
158			`state_ns = state_cs;`
159
160			`case (state_cs)`
161			`// DP1_RESET - Interface quiescent`
162			`DP1_RESET: begin`
163			`if ((gt_rst_done_i == 1) && (comreset_detect == 0)) begin`
164			`state_ns = DP2_COMINIT;`
165			`end`
166			`end`
167
168			`// DP2_COMINIT - Send COMINIT`
169			`DP2_COMINIT: begin`
170			`if (tx_com_done == 1) begin`
171			`state_ns = DP3_AWAIT_COMWAKE;`
172			`end`
173			`end`
174
175			`// DP3_AWAIT_COMWAKE - Wait for COMWAKE to be detected`
176			`DP3_AWAIT_COMWAKE: begin`
177			`if (comwake_detect == 1) begin`
178			`state_ns = DP3B_AWAIT_NO_COMWAKE;`
179			`end else begin`
180			`if (retry_cnt == 0) begin`
181			`state_ns = DP1_RESET;`
182			`end`
183			`end`
184			`end`
185
186			`// DP3B_AWAIT_NO_COMWAKE - Wait for COMWAKE to finish`
187			`DP3B_AWAIT_NO_COMWAKE: begin`
188			`if (comwake_detect == 0) begin`
189			`state_ns = DP4_CALIBRATE;`
190			`end`
191			`end`
192
193			`// DP4_CALIBRATE`
194			`DP4_CALIBRATE: begin`
195			`state_ns = DP5_COMWAKE;`
196			`end`
197
198			`// DP5_COMWAKE - Send COMWAKE`
199			`DP5_COMWAKE: begin`
200			`if (tx_com_done == 1) begin`
201			`state_ns = DP6_SEND_ALIGN;`
202			`end`
203			`end`
204
205			`// DP6_SEND_ALIGN - Send ALIGN`
206			`DP6_SEND_ALIGN: begin`
207			`if (align_detect == 1) begin`
208			`state_ns = DP7_READY;`
209			`end else begin`
210			`if (align_timeout_cnt == 0) begin`
211			`state_ns = DP11_ERROR;`
212			`end`
213			`end`
214			`end`
215
216			`// DP7_READY - Link ready`
217			`DP7_READY: begin`
218			`state_ns = DP7_READY;`
219			`end`
220
221			`// DP11_ERROR`
222			`DP11_ERROR: begin`
223			`state_ns = DP1_RESET;`
224			`end`
225
226			`default: begin`
227			`state_ns = 'bx;`
228			`end`
229			`endcase`
230			`end`
231
232			`////////////////////////////////////////////////////////////`
233			`// Seq Block : Link Up`
234			`// Description : Set when communication has been established`
235			`////////////////////////////////////////////////////////////`
236
237			`always @(negedge rst_n or posedge clk_phy)`
238			`begin`
239			`if (rst_n == 0) begin`
240			`link_up_o <= 0;`
241			`end else begin`
242			`case (state_cs)`
243			`// DP7_READY - Link ready`
244			`DP7_READY: begin`
245			`link_up_o <= 1;`
246			`end`
247
248			`default: begin`
249			`link_up_o <= 0;`
250			`end`
251			`endcase`
252			`end`
253			`end`
254
255			`////////////////////////////////////////////////////////////`
256			`// Seq Block : GT Transmit COM Start`
257			`// Description :`
258			`////////////////////////////////////////////////////////////`
259
260			`always @(negedge rst_n or posedge clk_phy)`
261			`begin`
262			`if (rst_n == 0) begin`
263			`gt_tx_com_strt_o <= 0;`
264			`end else begin`
265			`gt_tx_com_strt_o <= tx_com_strt_pedge;`
266			`end`
267			`end`
268
269			`////////////////////////////////////////////////////////////`
270			`// Seq Block : Transmit COM Type`
271			`// Description :`
272			`////////////////////////////////////////////////////////////`
273
274			`always @(negedge rst_n or posedge clk_phy)`
275			`begin`
276			`if (rst_n == 0) begin`
277			`gt_tx_com_type_o <= 0;`
278			`end else begin`
279			`case (state_cs)`
280			`// DP2_COMINIT - Send COMINIT`
281			`DP2_COMINIT: begin`
282			`gt_tx_com_type_o <= 0;`
283			`end`
284
285			`// DP5_COMWAKE - Send COMWAKE`
286			`DP5_COMWAKE: begin`
287			`gt_tx_com_type_o <= 1;`
288			`end`
289			`endcase`
290			`end`
291			`end`
292
293			`////////////////////////////////////////////////////////////`
294			`// Seq Block : GT Transmit Electrical Idle`
295			`// Description :`
296			`////////////////////////////////////////////////////////////`
297
298			`always @(negedge rst_n or posedge clk_phy)`
299			`begin`
300			`if (rst_n == 0) begin`
301			`gt_tx_elec_idle_o <= 0;`
302			`end else begin`
303			`case (state_cs)`
304			`// DP5_COMWAKE - Send COMWAKE`
305			`DP5_COMWAKE: begin`
306			`if (tx_com_done == 1) begin`
307			`gt_tx_elec_idle_o <= 0;`
308			`end`
309			`end`
310
311			`// DP6_SEND_ALIGN - Send ALIGN`
312			`DP6_SEND_ALIGN: begin`
313			`gt_tx_elec_idle_o <= 0;`
314			`end`
315
316			`// DP7_READY - Link ready`
317			`DP7_READY: begin`
318			`gt_tx_elec_idle_o <= 0;`
319			`end`
320
321			`default: begin`
322			`gt_tx_elec_idle_o <= 1;`
323			`end`
324			`endcase`
325			`end`
326			`end`
327
328			`////////////////////////////////////////////////////////////`
329			`// Seq Block : GT Transmit Data`
330			`// Description :`
331			`////////////////////////////////////////////////////////////`
332
333			`always @(negedge rst_n or posedge clk_phy)`
334			`begin`
335			`if (rst_n == 0) begin`
336			`gt_tx_data_o <= 0;`
337			`end else begin`
338			`case (state_cs)`
339			`// DP6_SEND_ALIGN - Send ALIGN`
340			`DP6_SEND_ALIGN: begin`
341			gt_tx_data_o <= `ALIGN_VAL; // ALIGN;
342			`end`
343
344			`// DP7_READY - Link ready`
345			`DP7_READY: begin`
346			gt_tx_data_o <= `SYNC_VAL; // SYNC;
347			`end`
348
349			`default: begin`
350			`gt_tx_data_o <= 0;`
351			`end`
352			`endcase`
353			`end`
354			`end`
355
356			`////////////////////////////////////////////////////////////`
357			`// Seq Block : GT Transmit K/D`
358			`// Description :`
359			`////////////////////////////////////////////////////////////`
360
361			`always @(negedge rst_n or posedge clk_phy)`
362			`begin`
363			`if (rst_n == 0) begin`
364			`gt_tx_charisk_o <= 0;`
365			`end else begin`
366			`case (state_cs)`
367			`// DP6_SEND_ALIGN - Send ALIGN`
368			`DP6_SEND_ALIGN: begin`
369			`gt_tx_charisk_o <= 4'b0001; // ALIGN;`
370			`end`
371
372			`// DP7_READY - Link ready`
373			`DP7_READY: begin`
374			`gt_tx_charisk_o <= 4'b0001; // SYNC;`
375			`end`
376
377			`default: begin`
378			`gt_tx_charisk_o <= 0;`
379			`end`
380			`endcase`
381			`end`
382			`end`
383
384			`////////////////////////////////////////////////////////////`
385			`// Seq Block : Transmit COM Start`
386			`// Description : Starts transmission of a COM sequence.`
387			`////////////////////////////////////////////////////////////`
388
389			`always @(negedge rst_n or posedge clk_phy)`
390			`begin`
391			`if (rst_n == 0) begin`
392			`tx_com_strt <= 0;`
393			`end else begin`
394			`case (state_cs)`
395			`// DP2_COMINIT - Send COMINIT`
396			`DP2_COMINIT: begin`
397			`tx_com_strt <= 1;`
398			`end`
399
400			`// DP5_COMWAKE - Send COMWAKE`
401			`DP5_COMWAKE: begin`
402			`tx_com_strt <= 1;`
403			`end`
404
405			`default: begin`
406			`tx_com_strt <= 0;`
407			`end`
408			`endcase`
409			`end`
410			`end`
411
412			`////////////////////////////////////////////////////////////`
413			`// Seq Block : Transmit COM Done`
414			`// Description :`
415			`////////////////////////////////////////////////////////////`
416
417			`always @(negedge rst_n or posedge clk_phy)`
418			`begin`
419			`if (rst_n == 0) begin`
420			`tx_com_done <= 0;`
421			`end else begin`
422			`case (state_cs)`
423			`// DP1_RESET - Interface quiescent`
424			`DP1_RESET: begin`
425			`tx_com_done <= 0;`
426			`end`
427
428			`// DP2_COMINIT - Send COMINIT`
429			`DP2_COMINIT: begin`
430			`if (gt_rx_status_i[0] == 1) begin`
431			`tx_com_done <= 1;`
432			`end`
433			`end`
434
435			`// DP5_COMWAKE - Send COMWAKE`
436			`DP5_COMWAKE: begin`
437			`if (gt_rx_status_i[0] == 1) begin`
438			`tx_com_done <= 1;`
439			`end`
440			`end`
441
442			`default: begin`
443			`tx_com_done <= 0;`
444			`end`
445			`endcase`
446			`end`
447			`end`
448
449			`////////////////////////////////////////////////////////////`
450			`// Seq Block : ALIGN Timeout Count`
451			`// Description : Error if ALIGN not detected within 54.6us.`
452			`////////////////////////////////////////////////////////////`
453
454			`always @(negedge rst_n or posedge clk_phy)`
455			`begin`
456			`if (rst_n == 0) begin`
457			`align_timeout_cnt <= 0;`
458			`end else begin`
459			`case (state_cs)`
460			`// DP1_RESET - Interface quiescent`
461			`DP1_RESET: begin`
462			`case (SATA_REV)`
463			`1: align_timeout_cnt <= SATA1_55US;`
464			`2: align_timeout_cnt <= SATA2_55US;`
465			`3: align_timeout_cnt <= SATA3_55US;`
466			`default: align_timeout_cnt <= SATA1_55US;`
467			`endcase`
468			`end`
469
470			`// DP6_SEND_ALIGN - Send ALIGN`
471			`DP6_SEND_ALIGN: begin`
472			`align_timeout_cnt <= align_timeout_cnt - 1;`
473			`end`
474			`endcase`
475			`end`
476			`end`
477
478			`////////////////////////////////////////////////////////////`
479			`// Seq Block : Retry Count`
480			`// Description : Used to for async signal recovery (10 ms)`
481			`////////////////////////////////////////////////////////////`
482
483			`always @(negedge rst_n or posedge clk_phy)`
484			`begin`
485			`if (rst_n == 0) begin`
486			`retry_cnt <= 0;`
487			`end else begin`
488			`case (state_cs)`
489			`// DP1_RESET - Interface quiescent`
490			`DP1_RESET: begin`
491			`case (SATA_REV)`
492			`1: retry_cnt <= SATA1_10MS;`
493			`2: retry_cnt <= SATA2_10MS;`
494			`3: retry_cnt <= SATA3_10MS;`
495			`default: retry_cnt <= SATA1_10MS;`
496			`endcase`
497			`end`
498
499			`// DP3_AWAIT_COMWAKE - Wait for COMWAKE to be detected`
500			`DP3_AWAIT_COMWAKE: begin`
501			`retry_cnt <= retry_cnt - 1;`
502			`end`
503			`endcase`
504			`end`
505			`end`
506
507			`endmodule`