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[/] [scalable_arbiter/] [trunk/] [rtl/] [verilog/] [pulser.v] - Blame information for rev 12

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/*
 * Copyright (c) 2008, Kendall Correll
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
`timescale 1ns / 1ps
 
module pulser #(
        parameter count = 1,
        parameter toggle = 0
)(
        input enable,
        output reg out,
 
        input clock,
        input reset
);
 
`include "functions.v"
 
// counter width is the size of the loaded value
parameter counter_width = flog2(count - 1) + 1;
 
reg [counter_width:0] counter;
wire [counter_width-1:0] counter_load;
wire counter_overflow;
 
assign counter_overflow = counter[counter_width];
assign counter_load = -count;
 
always @(posedge clock, posedge reset)
begin
        if(reset)
                out <= 1'b0;
        else
        begin
                if(toggle)
                        out <= out ^ counter_overflow;
                else
                        out <= counter_overflow;
        end
end
 
always @(posedge clock, posedge reset)
begin
        if(reset)
                counter <= {counter_width{1'b1}};
        else
        begin
                if(counter_overflow)
                        counter <= { 1'b0, counter_load };
                else if(enable)
                        counter <= counter + 1;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	12	kendallc	`/*`
2			`* Copyright (c) 2008, Kendall Correll`
3			`*`
4			`* Permission to use, copy, modify, and distribute this software for any`
5			`* purpose with or without fee is hereby granted, provided that the above`
6			`* copyright notice and this permission notice appear in all copies.`
7			`*`
8			`* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES`
9			`* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF`
10			`* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR`
11			`* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES`
12			`* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN`
13			`* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF`
14			`* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.`
15			`*/`
16
17			`timescale 1ns / 1ps
18
19			`module pulser #(`
20			`parameter count = 1,`
21			`parameter toggle = 0`
22			`)(`
23			`input enable,`
24			`output reg out,`
25
26			`input clock,`
27			`input reset`
28			`);`
29
30			`include "functions.v"
31
32			`// counter width is the size of the loaded value`
33			`parameter counter_width = flog2(count - 1) + 1;`
34
35			`reg [counter_width:0] counter;`
36			`wire [counter_width-1:0] counter_load;`
37			`wire counter_overflow;`
38
39			`assign counter_overflow = counter[counter_width];`
40			`assign counter_load = -count;`
41
42			`always @(posedge clock, posedge reset)`
43			`begin`
44			`if(reset)`
45			`out <= 1'b0;`
46			`else`
47			`begin`
48			`if(toggle)`
49			`out <= out ^ counter_overflow;`
50			`else`
51			`out <= counter_overflow;`
52			`end`
53			`end`
54
55			`always @(posedge clock, posedge reset)`
56			`begin`
57			`if(reset)`
58			`counter <= {counter_width{1'b1}};`
59			`else`
60			`begin`
61			`if(counter_overflow)`
62			`counter <= { 1'b0, counter_load };`
63			`else if(enable)`
64			`counter <= counter + 1;`
65			`end`
66			`end`
67
68			`endmodule`

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[/] [scalable_arbiter/] [trunk/] [rtl/] [verilog/] [pulser.v] - Blame information for rev 12