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jlechner |
/* thumbemu.c -- Thumb instruction emulation.
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Copyright (C) 1996, Cygnus Software Technologies Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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/* We can provide simple Thumb simulation by decoding the Thumb
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instruction into its corresponding ARM instruction, and using the
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existing ARM simulator. */
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#ifndef MODET /* required for the Thumb instruction support */
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#if 1
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#error "MODET needs to be defined for the Thumb world to work"
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#else
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#define MODET (1)
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#endif
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#endif
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#include "armdefs.h"
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#include "armemu.h"
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#include "armos.h"
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/* Attempt to emulate an ARMv6 instruction.
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Stores t_branch into PVALUE upon success or t_undefined otherwise. */
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static void
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handle_v6_thumb_insn (ARMul_State * state,
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ARMword tinstr,
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tdstate * pvalid)
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{
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ARMword Rd;
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ARMword Rm;
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if (! state->is_v6)
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{
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* pvalid = t_undefined;
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return;
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}
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switch (tinstr & 0xFFC0)
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{
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case 0xb660: /* cpsie */
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case 0xb670: /* cpsid */
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case 0x4600: /* cpy */
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case 0xba00: /* rev */
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case 0xba40: /* rev16 */
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case 0xbac0: /* revsh */
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case 0xb650: /* setend */
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default:
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printf ("Unhandled v6 thumb insn: %04x\n", tinstr);
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* pvalid = t_undefined;
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return;
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case 0xb200: /* sxth */
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Rm = state->Reg [(tinstr & 0x38) >> 3];
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if (Rm & 0x8000)
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state->Reg [(tinstr & 0x7)] = (Rm & 0xffff) | 0xffff0000;
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else
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state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
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break;
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case 0xb240: /* sxtb */
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Rm = state->Reg [(tinstr & 0x38) >> 3];
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if (Rm & 0x80)
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state->Reg [(tinstr & 0x7)] = (Rm & 0xff) | 0xffffff00;
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else
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state->Reg [(tinstr & 0x7)] = Rm & 0xff;
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break;
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case 0xb280: /* uxth */
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Rm = state->Reg [(tinstr & 0x38) >> 3];
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state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
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break;
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case 0xb2c0: /* uxtb */
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Rm = state->Reg [(tinstr & 0x38) >> 3];
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state->Reg [(tinstr & 0x7)] = Rm & 0xff;
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break;
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}
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/* Indicate that the instruction has been processed. */
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* pvalid = t_branch;
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}
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/* Decode a 16bit Thumb instruction. The instruction is in the low
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16-bits of the tinstr field, with the following Thumb instruction
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held in the high 16-bits. Passing in two Thumb instructions allows
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easier simulation of the special dual BL instruction. */
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tdstate
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ARMul_ThumbDecode (ARMul_State * state,
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ARMword pc,
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ARMword tinstr,
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ARMword * ainstr)
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{
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tdstate valid = t_decoded; /* default assumes a valid instruction */
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ARMword next_instr;
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if (state->bigendSig)
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{
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next_instr = tinstr & 0xFFFF;
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tinstr >>= 16;
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}
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else
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{
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next_instr = tinstr >> 16;
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tinstr &= 0xFFFF;
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}
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#if 1 /* debugging to catch non updates */
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*ainstr = 0xDEADC0DE;
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#endif
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switch ((tinstr & 0xF800) >> 11)
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{
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case 0: /* LSL */
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case 1: /* LSR */
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case 2: /* ASR */
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/* Format 1 */
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*ainstr = 0xE1B00000 /* base opcode */
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| ((tinstr & 0x1800) >> (11 - 5)) /* shift type */
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| ((tinstr & 0x07C0) << (7 - 6)) /* imm5 */
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| ((tinstr & 0x0038) >> 3) /* Rs */
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| ((tinstr & 0x0007) << 12); /* Rd */
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break;
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case 3: /* ADD/SUB */
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/* Format 2 */
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{
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ARMword subset[4] = {
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0xE0900000, /* ADDS Rd,Rs,Rn */
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0xE0500000, /* SUBS Rd,Rs,Rn */
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0xE2900000, /* ADDS Rd,Rs,#imm3 */
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0xE2500000 /* SUBS Rd,Rs,#imm3 */
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};
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/* It is quicker indexing into a table, than performing switch
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or conditionals: */
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*ainstr = subset[(tinstr & 0x0600) >> 9] /* base opcode */
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| ((tinstr & 0x01C0) >> 6) /* Rn or imm3 */
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| ((tinstr & 0x0038) << (16 - 3)) /* Rs */
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| ((tinstr & 0x0007) << (12 - 0)); /* Rd */
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}
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break;
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case 4: /* MOV */
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case 5: /* CMP */
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case 6: /* ADD */
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case 7: /* SUB */
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/* Format 3 */
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{
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ARMword subset[4] = {
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0xE3B00000, /* MOVS Rd,#imm8 */
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0xE3500000, /* CMP Rd,#imm8 */
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0xE2900000, /* ADDS Rd,Rd,#imm8 */
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0xE2500000, /* SUBS Rd,Rd,#imm8 */
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};
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*ainstr = subset[(tinstr & 0x1800) >> 11] /* base opcode */
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| ((tinstr & 0x00FF) >> 0) /* imm8 */
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| ((tinstr & 0x0700) << (16 - 8)) /* Rn */
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| ((tinstr & 0x0700) << (12 - 8)); /* Rd */
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}
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break;
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case 8: /* Arithmetic and high register transfers */
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/* TODO: Since the subsets for both Format 4 and Format 5
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instructions are made up of different ARM encodings, we could
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save the following conditional, and just have one large
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subset. */
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if ((tinstr & (1 << 10)) == 0)
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{
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/* Format 4 */
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struct
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{
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ARMword opcode;
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enum
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{ t_norm, t_shift, t_neg, t_mul }
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otype;
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}
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subset[16] =
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{
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{ 0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */
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{ 0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */
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{ 0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */
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{ 0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */
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{ 0xE1B00050, t_shift}, /* MOVS Rd,Rd,ASR Rs */
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{ 0xE0B00000, t_norm}, /* ADCS Rd,Rd,Rs */
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{ 0xE0D00000, t_norm}, /* SBCS Rd,Rd,Rs */
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{ 0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */
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{ 0xE1100000, t_norm}, /* TST Rd,Rs */
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{ 0xE2700000, t_neg}, /* RSBS Rd,Rs,#0 */
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{ 0xE1500000, t_norm}, /* CMP Rd,Rs */
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{ 0xE1700000, t_norm}, /* CMN Rd,Rs */
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{ 0xE1900000, t_norm}, /* ORRS Rd,Rd,Rs */
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{ 0xE0100090, t_mul} , /* MULS Rd,Rd,Rs */
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{ 0xE1D00000, t_norm}, /* BICS Rd,Rd,Rs */
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{ 0xE1F00000, t_norm} /* MVNS Rd,Rs */
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};
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*ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */
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switch (subset[(tinstr & 0x03C0) >> 6].otype)
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{
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case t_norm:
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*ainstr |= ((tinstr & 0x0007) << 16) /* Rn */
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| ((tinstr & 0x0007) << 12) /* Rd */
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| ((tinstr & 0x0038) >> 3); /* Rs */
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break;
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case t_shift:
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*ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
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| ((tinstr & 0x0007) >> 0) /* Rm */
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| ((tinstr & 0x0038) << (8 - 3)); /* Rs */
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break;
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case t_neg:
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*ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
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| ((tinstr & 0x0038) << (16 - 3)); /* Rn */
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break;
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case t_mul:
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*ainstr |= ((tinstr & 0x0007) << 16) /* Rd */
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| ((tinstr & 0x0007) << 8) /* Rs */
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| ((tinstr & 0x0038) >> 3); /* Rm */
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break;
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}
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}
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else
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{
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/* Format 5 */
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ARMword Rd = ((tinstr & 0x0007) >> 0);
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ARMword Rs = ((tinstr & 0x0038) >> 3);
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if (tinstr & (1 << 7))
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Rd += 8;
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if (tinstr & (1 << 6))
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Rs += 8;
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switch ((tinstr & 0x03C0) >> 6)
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{
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case 0x1: /* ADD Rd,Rd,Hs */
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case 0x2: /* ADD Hd,Hd,Rs */
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case 0x3: /* ADD Hd,Hd,Hs */
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*ainstr = 0xE0800000 /* base */
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| (Rd << 16) /* Rn */
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| (Rd << 12) /* Rd */
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| (Rs << 0); /* Rm */
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break;
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case 0x5: /* CMP Rd,Hs */
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case 0x6: /* CMP Hd,Rs */
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case 0x7: /* CMP Hd,Hs */
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*ainstr = 0xE1500000 /* base */
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| (Rd << 16) /* Rn */
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| (Rd << 12) /* Rd */
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| (Rs << 0); /* Rm */
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break;
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| 253 |
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case 0x9: /* MOV Rd,Hs */
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case 0xA: /* MOV Hd,Rs */
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case 0xB: /* MOV Hd,Hs */
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*ainstr = 0xE1A00000 /* base */
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| 257 |
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| (Rd << 16) /* Rn */
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| 258 |
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| (Rd << 12) /* Rd */
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| (Rs << 0); /* Rm */
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break;
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| 261 |
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case 0xC: /* BX Rs */
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| 262 |
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case 0xD: /* BX Hs */
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*ainstr = 0xE12FFF10 /* base */
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| 264 |
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| ((tinstr & 0x0078) >> 3); /* Rd */
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| 265 |
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break;
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| 266 |
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case 0xE: /* UNDEFINED */
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| 267 |
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case 0xF: /* UNDEFINED */
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| 268 |
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if (state->is_v5)
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| 269 |
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{
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| 270 |
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/* BLX Rs; BLX Hs */
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| 271 |
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*ainstr = 0xE12FFF30 /* base */
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| 272 |
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| ((tinstr & 0x0078) >> 3); /* Rd */
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| 273 |
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break;
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| 274 |
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}
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| 275 |
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/* Drop through. */
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| 276 |
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case 0x0: /* UNDEFINED */
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| 277 |
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case 0x4: /* UNDEFINED */
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| 278 |
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case 0x8: /* UNDEFINED */
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| 279 |
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handle_v6_thumb_insn (state, tinstr, & valid);
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| 280 |
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break;
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| 281 |
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}
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| 282 |
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}
|
| 283 |
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break;
|
| 284 |
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case 9: /* LDR Rd,[PC,#imm8] */
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| 285 |
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/* Format 6 */
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| 286 |
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*ainstr = 0xE59F0000 /* base */
|
| 287 |
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| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
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| 288 |
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| ((tinstr & 0x00FF) << (2 - 0)); /* off8 */
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| 289 |
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break;
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| 290 |
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case 10:
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| 291 |
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case 11:
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| 292 |
|
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/* TODO: Format 7 and Format 8 perform the same ARM encoding, so
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| 293 |
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the following could be merged into a single subset, saving on
|
| 294 |
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the following boolean: */
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| 295 |
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if ((tinstr & (1 << 9)) == 0)
|
| 296 |
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{
|
| 297 |
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/* Format 7 */
|
| 298 |
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ARMword subset[4] = {
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| 299 |
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0xE7800000, /* STR Rd,[Rb,Ro] */
|
| 300 |
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0xE7C00000, /* STRB Rd,[Rb,Ro] */
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| 301 |
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0xE7900000, /* LDR Rd,[Rb,Ro] */
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| 302 |
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0xE7D00000 /* LDRB Rd,[Rb,Ro] */
|
| 303 |
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};
|
| 304 |
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*ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
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| 305 |
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| ((tinstr & 0x0007) << (12 - 0)) /* Rd */
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| 306 |
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| ((tinstr & 0x0038) << (16 - 3)) /* Rb */
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| 307 |
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| ((tinstr & 0x01C0) >> 6); /* Ro */
|
| 308 |
|
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}
|
| 309 |
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else
|
| 310 |
|
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{
|
| 311 |
|
|
/* Format 8 */
|
| 312 |
|
|
ARMword subset[4] = {
|
| 313 |
|
|
0xE18000B0, /* STRH Rd,[Rb,Ro] */
|
| 314 |
|
|
0xE19000D0, /* LDRSB Rd,[Rb,Ro] */
|
| 315 |
|
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0xE19000B0, /* LDRH Rd,[Rb,Ro] */
|
| 316 |
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0xE19000F0 /* LDRSH Rd,[Rb,Ro] */
|
| 317 |
|
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};
|
| 318 |
|
|
*ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
|
| 319 |
|
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| ((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
| 320 |
|
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| ((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
| 321 |
|
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| ((tinstr & 0x01C0) >> 6); /* Ro */
|
| 322 |
|
|
}
|
| 323 |
|
|
break;
|
| 324 |
|
|
case 12: /* STR Rd,[Rb,#imm5] */
|
| 325 |
|
|
case 13: /* LDR Rd,[Rb,#imm5] */
|
| 326 |
|
|
case 14: /* STRB Rd,[Rb,#imm5] */
|
| 327 |
|
|
case 15: /* LDRB Rd,[Rb,#imm5] */
|
| 328 |
|
|
/* Format 9 */
|
| 329 |
|
|
{
|
| 330 |
|
|
ARMword subset[4] = {
|
| 331 |
|
|
0xE5800000, /* STR Rd,[Rb,#imm5] */
|
| 332 |
|
|
0xE5900000, /* LDR Rd,[Rb,#imm5] */
|
| 333 |
|
|
0xE5C00000, /* STRB Rd,[Rb,#imm5] */
|
| 334 |
|
|
0xE5D00000 /* LDRB Rd,[Rb,#imm5] */
|
| 335 |
|
|
};
|
| 336 |
|
|
/* The offset range defends on whether we are transferring a
|
| 337 |
|
|
byte or word value: */
|
| 338 |
|
|
*ainstr = subset[(tinstr & 0x1800) >> 11] /* base */
|
| 339 |
|
|
| ((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
| 340 |
|
|
| ((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
| 341 |
|
|
| ((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); /* off5 */
|
| 342 |
|
|
}
|
| 343 |
|
|
break;
|
| 344 |
|
|
case 16: /* STRH Rd,[Rb,#imm5] */
|
| 345 |
|
|
case 17: /* LDRH Rd,[Rb,#imm5] */
|
| 346 |
|
|
/* Format 10 */
|
| 347 |
|
|
*ainstr = ((tinstr & (1 << 11)) /* base */
|
| 348 |
|
|
? 0xE1D000B0 /* LDRH */
|
| 349 |
|
|
: 0xE1C000B0) /* STRH */
|
| 350 |
|
|
| ((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
| 351 |
|
|
| ((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
| 352 |
|
|
| ((tinstr & 0x01C0) >> (6 - 1)) /* off5, low nibble */
|
| 353 |
|
|
| ((tinstr & 0x0600) >> (9 - 8)); /* off5, high nibble */
|
| 354 |
|
|
break;
|
| 355 |
|
|
case 18: /* STR Rd,[SP,#imm8] */
|
| 356 |
|
|
case 19: /* LDR Rd,[SP,#imm8] */
|
| 357 |
|
|
/* Format 11 */
|
| 358 |
|
|
*ainstr = ((tinstr & (1 << 11)) /* base */
|
| 359 |
|
|
? 0xE59D0000 /* LDR */
|
| 360 |
|
|
: 0xE58D0000) /* STR */
|
| 361 |
|
|
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
| 362 |
|
|
| ((tinstr & 0x00FF) << 2); /* off8 */
|
| 363 |
|
|
break;
|
| 364 |
|
|
case 20: /* ADD Rd,PC,#imm8 */
|
| 365 |
|
|
case 21: /* ADD Rd,SP,#imm8 */
|
| 366 |
|
|
/* Format 12 */
|
| 367 |
|
|
if ((tinstr & (1 << 11)) == 0)
|
| 368 |
|
|
{
|
| 369 |
|
|
/* NOTE: The PC value used here should by word aligned */
|
| 370 |
|
|
/* We encode shift-left-by-2 in the rotate immediate field,
|
| 371 |
|
|
so no shift of off8 is needed. */
|
| 372 |
|
|
*ainstr = 0xE28F0F00 /* base */
|
| 373 |
|
|
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
| 374 |
|
|
| (tinstr & 0x00FF); /* off8 */
|
| 375 |
|
|
}
|
| 376 |
|
|
else
|
| 377 |
|
|
{
|
| 378 |
|
|
/* We encode shift-left-by-2 in the rotate immediate field,
|
| 379 |
|
|
so no shift of off8 is needed. */
|
| 380 |
|
|
*ainstr = 0xE28D0F00 /* base */
|
| 381 |
|
|
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
| 382 |
|
|
| (tinstr & 0x00FF); /* off8 */
|
| 383 |
|
|
}
|
| 384 |
|
|
break;
|
| 385 |
|
|
case 22:
|
| 386 |
|
|
case 23:
|
| 387 |
|
|
switch (tinstr & 0x0F00)
|
| 388 |
|
|
{
|
| 389 |
|
|
case 0x0000:
|
| 390 |
|
|
/* Format 13 */
|
| 391 |
|
|
/* NOTE: The instruction contains a shift left of 2
|
| 392 |
|
|
equivalent (implemented as ROR #30): */
|
| 393 |
|
|
*ainstr = ((tinstr & (1 << 7)) /* base */
|
| 394 |
|
|
? 0xE24DDF00 /* SUB */
|
| 395 |
|
|
: 0xE28DDF00) /* ADD */
|
| 396 |
|
|
| (tinstr & 0x007F); /* off7 */
|
| 397 |
|
|
break;
|
| 398 |
|
|
case 0x0400:
|
| 399 |
|
|
/* Format 14 - Push */
|
| 400 |
|
|
* ainstr = 0xE92D0000 | (tinstr & 0x00FF);
|
| 401 |
|
|
break;
|
| 402 |
|
|
case 0x0500:
|
| 403 |
|
|
/* Format 14 - Push + LR */
|
| 404 |
|
|
* ainstr = 0xE92D4000 | (tinstr & 0x00FF);
|
| 405 |
|
|
break;
|
| 406 |
|
|
case 0x0c00:
|
| 407 |
|
|
/* Format 14 - Pop */
|
| 408 |
|
|
* ainstr = 0xE8BD0000 | (tinstr & 0x00FF);
|
| 409 |
|
|
break;
|
| 410 |
|
|
case 0x0d00:
|
| 411 |
|
|
/* Format 14 - Pop + PC */
|
| 412 |
|
|
* ainstr = 0xE8BD8000 | (tinstr & 0x00FF);
|
| 413 |
|
|
break;
|
| 414 |
|
|
case 0x0e00:
|
| 415 |
|
|
if (state->is_v5)
|
| 416 |
|
|
{
|
| 417 |
|
|
/* This is normally an undefined instruction. The v5t architecture
|
| 418 |
|
|
defines this particular pattern as a BKPT instruction, for
|
| 419 |
|
|
hardware assisted debugging. We map onto the arm BKPT
|
| 420 |
|
|
instruction. */
|
| 421 |
|
|
* ainstr = 0xE1200070 | ((tinstr & 0xf0) << 4) | (tinstr & 0xf);
|
| 422 |
|
|
break;
|
| 423 |
|
|
}
|
| 424 |
|
|
/* Drop through. */
|
| 425 |
|
|
default:
|
| 426 |
|
|
/* Everything else is an undefined instruction. */
|
| 427 |
|
|
handle_v6_thumb_insn (state, tinstr, & valid);
|
| 428 |
|
|
break;
|
| 429 |
|
|
}
|
| 430 |
|
|
break;
|
| 431 |
|
|
case 24: /* STMIA */
|
| 432 |
|
|
case 25: /* LDMIA */
|
| 433 |
|
|
/* Format 15 */
|
| 434 |
|
|
*ainstr = ((tinstr & (1 << 11)) /* base */
|
| 435 |
|
|
? 0xE8B00000 /* LDMIA */
|
| 436 |
|
|
: 0xE8A00000) /* STMIA */
|
| 437 |
|
|
| ((tinstr & 0x0700) << (16 - 8)) /* Rb */
|
| 438 |
|
|
| (tinstr & 0x00FF); /* mask8 */
|
| 439 |
|
|
break;
|
| 440 |
|
|
case 26: /* Bcc */
|
| 441 |
|
|
case 27: /* Bcc/SWI */
|
| 442 |
|
|
if ((tinstr & 0x0F00) == 0x0F00)
|
| 443 |
|
|
{
|
| 444 |
|
|
/* Format 17 : SWI */
|
| 445 |
|
|
*ainstr = 0xEF000000;
|
| 446 |
|
|
/* Breakpoint must be handled specially. */
|
| 447 |
|
|
if ((tinstr & 0x00FF) == 0x18)
|
| 448 |
|
|
*ainstr |= ((tinstr & 0x00FF) << 16);
|
| 449 |
|
|
/* New breakpoint value. See gdb/arm-tdep.c */
|
| 450 |
|
|
else if ((tinstr & 0x00FF) == 0xFE)
|
| 451 |
|
|
*ainstr |= SWI_Breakpoint;
|
| 452 |
|
|
else
|
| 453 |
|
|
*ainstr |= (tinstr & 0x00FF);
|
| 454 |
|
|
}
|
| 455 |
|
|
else if ((tinstr & 0x0F00) != 0x0E00)
|
| 456 |
|
|
{
|
| 457 |
|
|
/* Format 16 */
|
| 458 |
|
|
int doit = FALSE;
|
| 459 |
|
|
/* TODO: Since we are doing a switch here, we could just add
|
| 460 |
|
|
the SWI and undefined instruction checks into this
|
| 461 |
|
|
switch to same on a couple of conditionals: */
|
| 462 |
|
|
switch ((tinstr & 0x0F00) >> 8)
|
| 463 |
|
|
{
|
| 464 |
|
|
case EQ:
|
| 465 |
|
|
doit = ZFLAG;
|
| 466 |
|
|
break;
|
| 467 |
|
|
case NE:
|
| 468 |
|
|
doit = !ZFLAG;
|
| 469 |
|
|
break;
|
| 470 |
|
|
case VS:
|
| 471 |
|
|
doit = VFLAG;
|
| 472 |
|
|
break;
|
| 473 |
|
|
case VC:
|
| 474 |
|
|
doit = !VFLAG;
|
| 475 |
|
|
break;
|
| 476 |
|
|
case MI:
|
| 477 |
|
|
doit = NFLAG;
|
| 478 |
|
|
break;
|
| 479 |
|
|
case PL:
|
| 480 |
|
|
doit = !NFLAG;
|
| 481 |
|
|
break;
|
| 482 |
|
|
case CS:
|
| 483 |
|
|
doit = CFLAG;
|
| 484 |
|
|
break;
|
| 485 |
|
|
case CC:
|
| 486 |
|
|
doit = !CFLAG;
|
| 487 |
|
|
break;
|
| 488 |
|
|
case HI:
|
| 489 |
|
|
doit = (CFLAG && !ZFLAG);
|
| 490 |
|
|
break;
|
| 491 |
|
|
case LS:
|
| 492 |
|
|
doit = (!CFLAG || ZFLAG);
|
| 493 |
|
|
break;
|
| 494 |
|
|
case GE:
|
| 495 |
|
|
doit = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
|
| 496 |
|
|
break;
|
| 497 |
|
|
case LT:
|
| 498 |
|
|
doit = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
|
| 499 |
|
|
break;
|
| 500 |
|
|
case GT:
|
| 501 |
|
|
doit = ((!NFLAG && !VFLAG && !ZFLAG)
|
| 502 |
|
|
|| (NFLAG && VFLAG && !ZFLAG));
|
| 503 |
|
|
break;
|
| 504 |
|
|
case LE:
|
| 505 |
|
|
doit = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
|
| 506 |
|
|
break;
|
| 507 |
|
|
}
|
| 508 |
|
|
if (doit)
|
| 509 |
|
|
{
|
| 510 |
|
|
state->Reg[15] = (pc + 4
|
| 511 |
|
|
+ (((tinstr & 0x7F) << 1)
|
| 512 |
|
|
| ((tinstr & (1 << 7)) ? 0xFFFFFF00 : 0)));
|
| 513 |
|
|
FLUSHPIPE;
|
| 514 |
|
|
}
|
| 515 |
|
|
valid = t_branch;
|
| 516 |
|
|
}
|
| 517 |
|
|
else
|
| 518 |
|
|
/* UNDEFINED : cc=1110(AL) uses different format. */
|
| 519 |
|
|
handle_v6_thumb_insn (state, tinstr, & valid);
|
| 520 |
|
|
break;
|
| 521 |
|
|
case 28: /* B */
|
| 522 |
|
|
/* Format 18 */
|
| 523 |
|
|
state->Reg[15] = (pc + 4
|
| 524 |
|
|
+ (((tinstr & 0x3FF) << 1)
|
| 525 |
|
|
| ((tinstr & (1 << 10)) ? 0xFFFFF800 : 0)));
|
| 526 |
|
|
FLUSHPIPE;
|
| 527 |
|
|
valid = t_branch;
|
| 528 |
|
|
break;
|
| 529 |
|
|
case 29: /* UNDEFINED */
|
| 530 |
|
|
if (state->is_v5)
|
| 531 |
|
|
{
|
| 532 |
|
|
if (tinstr & 1)
|
| 533 |
|
|
{
|
| 534 |
|
|
handle_v6_thumb_insn (state, tinstr, & valid);
|
| 535 |
|
|
break;
|
| 536 |
|
|
}
|
| 537 |
|
|
/* Drop through. */
|
| 538 |
|
|
|
| 539 |
|
|
/* Format 19 */
|
| 540 |
|
|
/* There is no single ARM instruction equivalent for this
|
| 541 |
|
|
instruction. Also, it should only ever be matched with the
|
| 542 |
|
|
fmt19 "BL/BLX instruction 1" instruction. However, we do
|
| 543 |
|
|
allow the simulation of it on its own, with undefined results
|
| 544 |
|
|
if r14 is not suitably initialised. */
|
| 545 |
|
|
{
|
| 546 |
|
|
ARMword tmp = (pc + 2);
|
| 547 |
|
|
|
| 548 |
|
|
state->Reg[15] = ((state->Reg[14] + ((tinstr & 0x07FF) << 1))
|
| 549 |
|
|
& 0xFFFFFFFC);
|
| 550 |
|
|
CLEART;
|
| 551 |
|
|
state->Reg[14] = (tmp | 1);
|
| 552 |
|
|
valid = t_branch;
|
| 553 |
|
|
FLUSHPIPE;
|
| 554 |
|
|
break;
|
| 555 |
|
|
}
|
| 556 |
|
|
}
|
| 557 |
|
|
|
| 558 |
|
|
handle_v6_thumb_insn (state, tinstr, & valid);
|
| 559 |
|
|
break;
|
| 560 |
|
|
|
| 561 |
|
|
case 30: /* BL instruction 1 */
|
| 562 |
|
|
/* Format 19 */
|
| 563 |
|
|
/* There is no single ARM instruction equivalent for this Thumb
|
| 564 |
|
|
instruction. To keep the simulation simple (from the user
|
| 565 |
|
|
perspective) we check if the following instruction is the
|
| 566 |
|
|
second half of this BL, and if it is we simulate it
|
| 567 |
|
|
immediately. */
|
| 568 |
|
|
state->Reg[14] = state->Reg[15] \
|
| 569 |
|
|
+ (((tinstr & 0x07FF) << 12) \
|
| 570 |
|
|
| ((tinstr & (1 << 10)) ? 0xFF800000 : 0));
|
| 571 |
|
|
|
| 572 |
|
|
valid = t_branch; /* in-case we don't have the 2nd half */
|
| 573 |
|
|
tinstr = next_instr; /* move the instruction down */
|
| 574 |
|
|
pc += 2; /* point the pc at the 2nd half */
|
| 575 |
|
|
if (((tinstr & 0xF800) >> 11) != 31)
|
| 576 |
|
|
{
|
| 577 |
|
|
if (((tinstr & 0xF800) >> 11) == 29)
|
| 578 |
|
|
{
|
| 579 |
|
|
ARMword tmp = (pc + 2);
|
| 580 |
|
|
|
| 581 |
|
|
state->Reg[15] = ((state->Reg[14]
|
| 582 |
|
|
+ ((tinstr & 0x07FE) << 1))
|
| 583 |
|
|
& 0xFFFFFFFC);
|
| 584 |
|
|
CLEART;
|
| 585 |
|
|
state->Reg[14] = (tmp | 1);
|
| 586 |
|
|
valid = t_branch;
|
| 587 |
|
|
FLUSHPIPE;
|
| 588 |
|
|
}
|
| 589 |
|
|
else
|
| 590 |
|
|
/* Exit, since not correct instruction. */
|
| 591 |
|
|
pc -= 2;
|
| 592 |
|
|
break;
|
| 593 |
|
|
}
|
| 594 |
|
|
/* else we fall through to process the second half of the BL */
|
| 595 |
|
|
pc += 2; /* point the pc at the 2nd half */
|
| 596 |
|
|
case 31: /* BL instruction 2 */
|
| 597 |
|
|
/* Format 19 */
|
| 598 |
|
|
/* There is no single ARM instruction equivalent for this
|
| 599 |
|
|
instruction. Also, it should only ever be matched with the
|
| 600 |
|
|
fmt19 "BL instruction 1" instruction. However, we do allow
|
| 601 |
|
|
the simulation of it on its own, with undefined results if
|
| 602 |
|
|
r14 is not suitably initialised. */
|
| 603 |
|
|
{
|
| 604 |
|
|
ARMword tmp = pc;
|
| 605 |
|
|
|
| 606 |
|
|
state->Reg[15] = (state->Reg[14] + ((tinstr & 0x07FF) << 1));
|
| 607 |
|
|
state->Reg[14] = (tmp | 1);
|
| 608 |
|
|
valid = t_branch;
|
| 609 |
|
|
FLUSHPIPE;
|
| 610 |
|
|
}
|
| 611 |
|
|
break;
|
| 612 |
|
|
}
|
| 613 |
|
|
|
| 614 |
|
|
return valid;
|
| 615 |
|
|
}
|
