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jlechner |
/* The common simulator framework for GDB, the GNU Debugger.
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Copyright 2002, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Andrew Cagney and Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef N
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#error "N must be #defined"
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#endif
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#ifndef M
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#define M N
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#endif
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/* N: The number of bytes of data to transfer.
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M: The number of bytes in the type used to transfer the data */
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#if (N > M)
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#error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
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#endif
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#include "symcat.h"
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/* NOTE: see end of file for #undef of these macros */
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#define unsigned_M XCONCAT2(unsigned_,M)
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#define T2H_M XCONCAT2(T2H_,M)
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#define H2T_M XCONCAT2(H2T_,M)
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#define SWAP_M XCONCAT2(SWAP_,M)
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#define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
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#define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
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#define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N)
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#define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
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#define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
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#define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
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#define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
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#define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)
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#if (M == N && N > 1)
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/* dummy variable used as a return value when nothing else is
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available and the compiler is complaining */
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static unsigned_M sim_core_dummy_M;
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#endif
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/* TAGS: sim_core_trace_1 sim_core_trace_2 */
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/* TAGS: sim_core_trace_4 sim_core_trace_8 */
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/* TAGS: sim_core_trace_16 */
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#if (M == N)
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STATIC_SIM_CORE(void)
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sim_core_trace_M (sim_cpu *cpu,
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sim_cia cia,
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int line_nr,
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transfer_type type,
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unsigned map,
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address_word addr,
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unsigned_M val,
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int nr_bytes)
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{
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const char *transfer = (type == read_transfer ? "read" : "write");
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const char *direction = (type == read_transfer ? "->" : "<-");
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if (TRACE_DEBUG_P (cpu))
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trace_printf (CPU_STATE (cpu), cpu, "sim-n-core.h:%d: ", line_nr);
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#if (M == 16)
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trace_printf (CPU_STATE (cpu), cpu,
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"%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n",
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transfer, nr_bytes,
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map_to_str (map),
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(unsigned long) addr,
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direction,
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(unsigned long) V4_16 (val, 0),
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(unsigned long) V4_16 (val, 1),
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(unsigned long) V4_16 (val, 2),
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(unsigned long) V4_16 (val, 3));
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#endif
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#if (M == 8)
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trace_printf (CPU_STATE (cpu), cpu,
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"%s-%d %s:0x%08lx %s 0x%08lx%08lx\n",
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transfer, nr_bytes,
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map_to_str (map),
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(unsigned long) addr,
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direction,
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(unsigned long) V4_8 (val, 0),
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(unsigned long) V4_8 (val, 1));
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#endif
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#if (M == 4)
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trace_printf (CPU_STATE (cpu), cpu,
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"%s-%d %s:0x%08lx %s 0x%08lx\n",
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transfer,
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nr_bytes,
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map_to_str (map),
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(unsigned long) addr,
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direction,
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(unsigned long) val);
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#endif
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#if (M == 2)
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trace_printf (CPU_STATE (cpu), cpu,
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"%s-%d %s:0x%08lx %s 0x%04lx\n",
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transfer,
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nr_bytes,
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map_to_str (map),
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(unsigned long) addr,
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direction,
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(unsigned long) val);
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#endif
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#if (M == 1)
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trace_printf (CPU_STATE (cpu), cpu,
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"%s-%d %s:0x%08lx %s 0x%02lx\n",
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transfer,
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nr_bytes,
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map_to_str (map),
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(unsigned long) addr,
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direction,
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(unsigned long) val);
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#endif
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}
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#endif
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/* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
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/* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
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/* TAGS: sim_core_read_aligned_16 */
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#if (M == N)
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INLINE_SIM_CORE(unsigned_M)
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sim_core_read_aligned_N(sim_cpu *cpu,
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sim_cia cia,
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unsigned map,
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address_word xaddr)
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{
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sim_cpu_core *cpu_core = CPU_CORE (cpu);
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sim_core_common *core = &cpu_core->common;
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unsigned_M val;
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sim_core_mapping *mapping;
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address_word addr;
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#if WITH_XOR_ENDIAN != 0
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if (WITH_XOR_ENDIAN)
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addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
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else
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#endif
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addr = xaddr;
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mapping = sim_core_find_mapping (core, map, addr, N, read_transfer, 1 /*abort*/, cpu, cia);
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do
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{
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#if (WITH_DEVICES)
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if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
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{
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unsigned_M data;
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if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
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device_error (mapping->device, "internal error - %s - io_read_buffer should not fail",
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XSTRING (sim_core_read_aligned_N));
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val = T2H_M (data);
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break;
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}
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#endif
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#if (WITH_HW)
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if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
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{
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unsigned_M data;
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sim_cpu_hw_io_read_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
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val = T2H_M (data);
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break;
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}
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#endif
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val = T2H_M (*(unsigned_M*) sim_core_translate (mapping, addr));
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}
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while (0);
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PROFILE_COUNT_CORE (cpu, addr, N, map);
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if (TRACE_P (cpu, TRACE_CORE_IDX))
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sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
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return val;
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}
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#endif
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/* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
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/* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
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/* TAGS: sim_core_read_unaligned_16 */
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#if (M == N && N > 1)
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INLINE_SIM_CORE(unsigned_M)
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sim_core_read_unaligned_N(sim_cpu *cpu,
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sim_cia cia,
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unsigned map,
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address_word addr)
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{
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int alignment = N - 1;
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/* if hardwired to forced alignment just do it */
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if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
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return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
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else if ((addr & alignment) == 0)
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return sim_core_read_aligned_N (cpu, cia, map, addr);
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else
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switch (CURRENT_ALIGNMENT)
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{
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case STRICT_ALIGNMENT:
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SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
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read_transfer, sim_core_unaligned_signal);
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case NONSTRICT_ALIGNMENT:
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{
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unsigned_M val;
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if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
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SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
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read_transfer, sim_core_unaligned_signal);
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val = T2H_M(val);
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PROFILE_COUNT_CORE (cpu, addr, N, map);
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if (TRACE_P (cpu, TRACE_CORE_IDX))
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sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
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return val;
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}
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case FORCED_ALIGNMENT:
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return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
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case MIXED_ALIGNMENT:
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sim_engine_abort (CPU_STATE (cpu), cpu, cia,
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"internal error - %s - mixed alignment",
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XSTRING (sim_core_read_unaligned_N));
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default:
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sim_engine_abort (CPU_STATE (cpu), cpu, cia,
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"internal error - %s - bad switch",
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XSTRING (sim_core_read_unaligned_N));
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/* to keep some compilers happy, we return a dummy */
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return sim_core_dummy_M;
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}
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}
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#endif
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| 247 |
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| 248 |
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/* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */
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| 249 |
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/* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */
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| 250 |
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| 251 |
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#if (M != N)
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| 252 |
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INLINE_SIM_CORE(unsigned_M)
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| 253 |
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sim_core_read_misaligned_N(sim_cpu *cpu,
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| 254 |
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sim_cia cia,
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| 255 |
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unsigned map,
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| 256 |
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address_word addr)
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| 257 |
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{
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| 258 |
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unsigned_M val = 0;
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| 259 |
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if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
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| 260 |
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SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
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| 261 |
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read_transfer, sim_core_unaligned_signal);
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| 262 |
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if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
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| 263 |
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val = SWAP_M (val);
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| 264 |
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if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
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| 265 |
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val >>= (M - N) * 8;
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| 266 |
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PROFILE_COUNT_CORE (cpu, addr, N, map);
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| 267 |
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if (TRACE_P (cpu, TRACE_CORE_IDX))
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| 268 |
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sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
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| 269 |
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return val;
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| 270 |
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}
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| 271 |
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#endif
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| 272 |
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| 273 |
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/* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
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| 274 |
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/* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
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| 275 |
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/* TAGS: sim_core_write_aligned_16 */
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| 276 |
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| 277 |
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#if (M == N)
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| 278 |
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INLINE_SIM_CORE(void)
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| 279 |
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sim_core_write_aligned_N(sim_cpu *cpu,
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| 280 |
|
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sim_cia cia,
|
| 281 |
|
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unsigned map,
|
| 282 |
|
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address_word xaddr,
|
| 283 |
|
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unsigned_M val)
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| 284 |
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{
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| 285 |
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sim_cpu_core *cpu_core = CPU_CORE (cpu);
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| 286 |
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sim_core_common *core = &cpu_core->common;
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| 287 |
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sim_core_mapping *mapping;
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| 288 |
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address_word addr;
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| 289 |
|
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#if WITH_XOR_ENDIAN != 0
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| 290 |
|
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if (WITH_XOR_ENDIAN)
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| 291 |
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addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
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| 292 |
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else
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| 293 |
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#endif
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| 294 |
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addr = xaddr;
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| 295 |
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mapping = sim_core_find_mapping (core, map, addr, N, write_transfer, 1 /*abort*/, cpu, cia);
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| 296 |
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do
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| 297 |
|
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{
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| 298 |
|
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#if (WITH_DEVICES)
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| 299 |
|
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if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
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| 300 |
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{
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| 301 |
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unsigned_M data = H2T_M (val);
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| 302 |
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if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
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| 303 |
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device_error (mapping->device, "internal error - %s - io_write_buffer should not fail",
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| 304 |
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XSTRING (sim_core_write_aligned_N));
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| 305 |
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break;
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| 306 |
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}
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| 307 |
|
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#endif
|
| 308 |
|
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#if (WITH_HW)
|
| 309 |
|
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if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
|
| 310 |
|
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{
|
| 311 |
|
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unsigned_M data = H2T_M (val);
|
| 312 |
|
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sim_cpu_hw_io_write_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
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| 313 |
|
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break;
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| 314 |
|
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}
|
| 315 |
|
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#endif
|
| 316 |
|
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*(unsigned_M*) sim_core_translate (mapping, addr) = H2T_M (val);
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| 317 |
|
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}
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| 318 |
|
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while (0);
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| 319 |
|
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PROFILE_COUNT_CORE (cpu, addr, N, map);
|
| 320 |
|
|
if (TRACE_P (cpu, TRACE_CORE_IDX))
|
| 321 |
|
|
sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
|
| 322 |
|
|
}
|
| 323 |
|
|
#endif
|
| 324 |
|
|
|
| 325 |
|
|
/* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
|
| 326 |
|
|
/* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
|
| 327 |
|
|
/* TAGS: sim_core_write_unaligned_16 */
|
| 328 |
|
|
|
| 329 |
|
|
#if (M == N && N > 1)
|
| 330 |
|
|
INLINE_SIM_CORE(void)
|
| 331 |
|
|
sim_core_write_unaligned_N(sim_cpu *cpu,
|
| 332 |
|
|
sim_cia cia,
|
| 333 |
|
|
unsigned map,
|
| 334 |
|
|
address_word addr,
|
| 335 |
|
|
unsigned_M val)
|
| 336 |
|
|
{
|
| 337 |
|
|
int alignment = N - 1;
|
| 338 |
|
|
/* if hardwired to forced alignment just do it */
|
| 339 |
|
|
if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
|
| 340 |
|
|
sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
|
| 341 |
|
|
else if ((addr & alignment) == 0)
|
| 342 |
|
|
sim_core_write_aligned_N (cpu, cia, map, addr, val);
|
| 343 |
|
|
else
|
| 344 |
|
|
switch (CURRENT_ALIGNMENT)
|
| 345 |
|
|
{
|
| 346 |
|
|
case STRICT_ALIGNMENT:
|
| 347 |
|
|
SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
|
| 348 |
|
|
write_transfer, sim_core_unaligned_signal);
|
| 349 |
|
|
break;
|
| 350 |
|
|
case NONSTRICT_ALIGNMENT:
|
| 351 |
|
|
{
|
| 352 |
|
|
unsigned_M data = H2T_M (val);
|
| 353 |
|
|
if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
|
| 354 |
|
|
SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
|
| 355 |
|
|
write_transfer, sim_core_unaligned_signal);
|
| 356 |
|
|
PROFILE_COUNT_CORE (cpu, addr, N, map);
|
| 357 |
|
|
if (TRACE_P (cpu, TRACE_CORE_IDX))
|
| 358 |
|
|
sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
|
| 359 |
|
|
break;
|
| 360 |
|
|
}
|
| 361 |
|
|
case FORCED_ALIGNMENT:
|
| 362 |
|
|
sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
|
| 363 |
|
|
break;
|
| 364 |
|
|
case MIXED_ALIGNMENT:
|
| 365 |
|
|
sim_engine_abort (CPU_STATE (cpu), cpu, cia,
|
| 366 |
|
|
"internal error - %s - mixed alignment",
|
| 367 |
|
|
XSTRING (sim_core_write_unaligned_N));
|
| 368 |
|
|
break;
|
| 369 |
|
|
default:
|
| 370 |
|
|
sim_engine_abort (CPU_STATE (cpu), cpu, cia,
|
| 371 |
|
|
"internal error - %s - bad switch",
|
| 372 |
|
|
XSTRING (sim_core_write_unaligned_N));
|
| 373 |
|
|
break;
|
| 374 |
|
|
}
|
| 375 |
|
|
}
|
| 376 |
|
|
#endif
|
| 377 |
|
|
|
| 378 |
|
|
/* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */
|
| 379 |
|
|
/* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */
|
| 380 |
|
|
|
| 381 |
|
|
#if (M != N)
|
| 382 |
|
|
INLINE_SIM_CORE(void)
|
| 383 |
|
|
sim_core_write_misaligned_N(sim_cpu *cpu,
|
| 384 |
|
|
sim_cia cia,
|
| 385 |
|
|
unsigned map,
|
| 386 |
|
|
address_word addr,
|
| 387 |
|
|
unsigned_M val)
|
| 388 |
|
|
{
|
| 389 |
|
|
unsigned_M data = val;
|
| 390 |
|
|
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
|
| 391 |
|
|
data <<= (M - N) * 8;
|
| 392 |
|
|
if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
|
| 393 |
|
|
data = SWAP_M (data);
|
| 394 |
|
|
if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
|
| 395 |
|
|
SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
|
| 396 |
|
|
write_transfer, sim_core_unaligned_signal);
|
| 397 |
|
|
PROFILE_COUNT_CORE (cpu, addr, N, map);
|
| 398 |
|
|
if (TRACE_P (cpu, TRACE_CORE_IDX))
|
| 399 |
|
|
sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
|
| 400 |
|
|
}
|
| 401 |
|
|
#endif
|
| 402 |
|
|
|
| 403 |
|
|
|
| 404 |
|
|
/* NOTE: see start of file for #define of these macros */
|
| 405 |
|
|
#undef unsigned_M
|
| 406 |
|
|
#undef T2H_M
|
| 407 |
|
|
#undef H2T_M
|
| 408 |
|
|
#undef SWAP_M
|
| 409 |
|
|
#undef sim_core_read_aligned_N
|
| 410 |
|
|
#undef sim_core_read_unaligned_N
|
| 411 |
|
|
#undef sim_core_read_misaligned_N
|
| 412 |
|
|
#undef sim_core_write_aligned_N
|
| 413 |
|
|
#undef sim_core_write_unaligned_N
|
| 414 |
|
|
#undef sim_core_write_misaligned_N
|
| 415 |
|
|
#undef sim_core_trace_M
|
| 416 |
|
|
#undef sim_core_dummy_M
|
| 417 |
|
|
#undef M
|
| 418 |
|
|
#undef N
|
