OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [ppc/] [altivec_expression.h] - Blame information for rev 26

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 jlechner
/* Altivec expression macros, for PSIM, the PowerPC simulator.
2
 
3
   Copyright 2003, 2007, 2008 Free Software Foundation, Inc.
4
 
5
   Contributed by Red Hat Inc; developed under contract from Motorola.
6
   Written by matthew green <mrg@redhat.com>.
7
 
8
   This file is part of GDB.
9
 
10
   This program is free software; you can redistribute it and/or modify
11
   it under the terms of the GNU General Public License as published by
12
   the Free Software Foundation; either version 3 of the License, or
13
   (at your option) any later version.
14
 
15
   This program is distributed in the hope that it will be useful,
16
   but WITHOUT ANY WARRANTY; without even the implied warranty of
17
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
   GNU General Public License for more details.
19
 
20
   You should have received a copy of the GNU General Public License
21
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
/* AltiVec macro helpers.  */
24
 
25
#define ALTIVEC_SET_CR6(vS, checkone) \
26
do { \
27
  if (checkone && ((*vS).w[0] == 0xffffffff && \
28
                   (*vS).w[1] == 0xffffffff && \
29
                   (*vS).w[2] == 0xffffffff && \
30
                   (*vS).w[3] == 0xffffffff)) \
31
    CR_SET(6, 1 << 3); \
32
  else if ((*vS).w[0] == 0 && \
33
           (*vS).w[1] == 0 && \
34
           (*vS).w[2] == 0 && \
35
           (*vS).w[3] == 0) \
36
    CR_SET(6, 1 << 1); \
37
  else \
38
    CR_SET(6, 0); \
39
} while (0)
40
 
41
#define VSCR_SAT        0x00000001
42
#define VSCR_NJ         0x00010000
43
 
44
#define ALTIVEC_SET_SAT(sat) \
45
do { \
46
  if (sat) \
47
    VSCR |= VSCR_SAT; \
48
} while (0)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.