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# Intel(r) Wireless MMX(tm) technology testcase for TEXTRM
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global textrm
textrm:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        # Test Unsigned Byte Wide Extraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff
 
        tmcrr      wr0, r0, r1
 
        textrmub   r2, wr0, #3
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x00000012
 
        # Test Signed Byte Wide Extraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff
 
        tmcrr      wr0, r0, r1
 
        textrmsb   r2, wr0, #4
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0xfffffff0
 
        # Test Unsigned Half Word Wide Extraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff
 
        tmcrr      wr0, r0, r1
 
        textrmuh   r2, wr0, #3
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x00009abc
 
        # Test Signed Half Word Wide Extraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff
 
        tmcrr      wr0, r0, r1
 
        textrmsh   r2, wr0, #1
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x00001234
 
        # Test Unsigned Word Wide Extraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff
 
        tmcrr      wr0, r0, r1
 
        textrmuw   r2, wr0, #0
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x12345678
 
        # Test Signed Word Wide Extraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff
 
        tmcrr      wr0, r0, r1
 
        textrmsw   r2, wr0, #1
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x9abcdef0
 
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# Intel(r) Wireless MMX(tm) technology testcase for TEXTRM`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global textrm`
10			`textrm:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`# Test Unsigned Byte Wide Extraction`
18
19			`mvi_h_gr r0, 0x12345678`
20			`mvi_h_gr r1, 0x9abcdef0`
21			`mvi_h_gr r2, 0x111111ff`
22
23			`tmcrr wr0, r0, r1`
24
25			`textrmub r2, wr0, #3`
26
27			`tmrrc r0, r1, wr0`
28
29			`test_h_gr r0, 0x12345678`
30			`test_h_gr r1, 0x9abcdef0`
31			`test_h_gr r2, 0x00000012`
32
33			`# Test Signed Byte Wide Extraction`
34
35			`mvi_h_gr r0, 0x12345678`
36			`mvi_h_gr r1, 0x9abcdef0`
37			`mvi_h_gr r2, 0x111111ff`
38
39			`tmcrr wr0, r0, r1`
40
41			`textrmsb r2, wr0, #4`
42
43			`tmrrc r0, r1, wr0`
44
45			`test_h_gr r0, 0x12345678`
46			`test_h_gr r1, 0x9abcdef0`
47			`test_h_gr r2, 0xfffffff0`
48
49			`# Test Unsigned Half Word Wide Extraction`
50
51			`mvi_h_gr r0, 0x12345678`
52			`mvi_h_gr r1, 0x9abcdef0`
53			`mvi_h_gr r2, 0x111111ff`
54
55			`tmcrr wr0, r0, r1`
56
57			`textrmuh r2, wr0, #3`
58
59			`tmrrc r0, r1, wr0`
60
61			`test_h_gr r0, 0x12345678`
62			`test_h_gr r1, 0x9abcdef0`
63			`test_h_gr r2, 0x00009abc`
64
65			`# Test Signed Half Word Wide Extraction`
66
67			`mvi_h_gr r0, 0x12345678`
68			`mvi_h_gr r1, 0x9abcdef0`
69			`mvi_h_gr r2, 0x111111ff`
70
71			`tmcrr wr0, r0, r1`
72
73			`textrmsh r2, wr0, #1`
74
75			`tmrrc r0, r1, wr0`
76
77			`test_h_gr r0, 0x12345678`
78			`test_h_gr r1, 0x9abcdef0`
79			`test_h_gr r2, 0x00001234`
80
81			`# Test Unsigned Word Wide Extraction`
82
83			`mvi_h_gr r0, 0x12345678`
84			`mvi_h_gr r1, 0x9abcdef0`
85			`mvi_h_gr r2, 0x111111ff`
86
87			`tmcrr wr0, r0, r1`
88
89			`textrmuw r2, wr0, #0`
90
91			`tmrrc r0, r1, wr0`
92
93			`test_h_gr r0, 0x12345678`
94			`test_h_gr r1, 0x9abcdef0`
95			`test_h_gr r2, 0x12345678`
96
97			`# Test Signed Word Wide Extraction`
98
99			`mvi_h_gr r0, 0x12345678`
100			`mvi_h_gr r1, 0x9abcdef0`
101			`mvi_h_gr r2, 0x111111ff`
102
103			`tmcrr wr0, r0, r1`
104
105			`textrmsw r2, wr0, #1`
106
107			`tmrrc r0, r1, wr0`
108
109			`test_h_gr r0, 0x12345678`
110			`test_h_gr r1, 0x9abcdef0`
111			`test_h_gr r2, 0x9abcdef0`
112
113			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [textrm.cgs] - Blame information for rev 26