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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmin.cgs] - Blame information for rev 26

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# Intel(r) Wireless MMX(tm) technology testcase for WMIN
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global wmin
wmin:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        # Test Unsigned Byte Minimum
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wminub     wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x11111111
        test_h_gr  r5, 0x11111100
 
        # Test Signed Byte Minimum
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wminsb     wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x11111111
        test_h_gr  r5, 0x9abcde00
 
        # Test Unsigned Halfword Minimum
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wminuh     wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x11111111
        test_h_gr  r5, 0x11111111
 
        # Test Signed Halfword Minimum
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wminsh     wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x11111111
        test_h_gr  r5, 0x9abcde00
 
        # Test Unsigned Word Minimum
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wminuw     wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x11111111
        test_h_gr  r5, 0x11111111
 
        # Test Signed Word Minimum
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wminsw     wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x11111111
        test_h_gr  r5, 0x9abcde00
 
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# Intel(r) Wireless MMX(tm) technology testcase for WMIN`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global wmin`
10			`wmin:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`# Test Unsigned Byte Minimum`
18
19			`mvi_h_gr r0, 0x12345678`
20			`mvi_h_gr r1, 0x9abcde00`
21			`mvi_h_gr r2, 0x11111111`
22			`mvi_h_gr r3, 0x11111111`
23			`mvi_h_gr r4, 0`
24			`mvi_h_gr r5, 0`
25
26			`tmcrr wr0, r0, r1`
27			`tmcrr wr1, r2, r3`
28			`tmcrr wr2, r4, r5`
29
30			`wminub wr2, wr0, wr1`
31
32			`tmrrc r0, r1, wr0`
33			`tmrrc r2, r3, wr1`
34			`tmrrc r4, r5, wr2`
35
36			`test_h_gr r0, 0x12345678`
37			`test_h_gr r1, 0x9abcde00`
38			`test_h_gr r2, 0x11111111`
39			`test_h_gr r3, 0x11111111`
40			`test_h_gr r4, 0x11111111`
41			`test_h_gr r5, 0x11111100`
42
43			`# Test Signed Byte Minimum`
44
45			`mvi_h_gr r0, 0x12345678`
46			`mvi_h_gr r1, 0x9abcde00`
47			`mvi_h_gr r2, 0x11111111`
48			`mvi_h_gr r3, 0x11111111`
49			`mvi_h_gr r4, 0`
50			`mvi_h_gr r5, 0`
51
52			`tmcrr wr0, r0, r1`
53			`tmcrr wr1, r2, r3`
54			`tmcrr wr2, r4, r5`
55
56			`wminsb wr2, wr0, wr1`
57
58			`tmrrc r0, r1, wr0`
59			`tmrrc r2, r3, wr1`
60			`tmrrc r4, r5, wr2`
61
62			`test_h_gr r0, 0x12345678`
63			`test_h_gr r1, 0x9abcde00`
64			`test_h_gr r2, 0x11111111`
65			`test_h_gr r3, 0x11111111`
66			`test_h_gr r4, 0x11111111`
67			`test_h_gr r5, 0x9abcde00`
68
69			`# Test Unsigned Halfword Minimum`
70
71			`mvi_h_gr r0, 0x12345678`
72			`mvi_h_gr r1, 0x9abcde00`
73			`mvi_h_gr r2, 0x11111111`
74			`mvi_h_gr r3, 0x11111111`
75			`mvi_h_gr r4, 0`
76			`mvi_h_gr r5, 0`
77
78			`tmcrr wr0, r0, r1`
79			`tmcrr wr1, r2, r3`
80			`tmcrr wr2, r4, r5`
81
82			`wminuh wr2, wr0, wr1`
83
84			`tmrrc r0, r1, wr0`
85			`tmrrc r2, r3, wr1`
86			`tmrrc r4, r5, wr2`
87
88			`test_h_gr r0, 0x12345678`
89			`test_h_gr r1, 0x9abcde00`
90			`test_h_gr r2, 0x11111111`
91			`test_h_gr r3, 0x11111111`
92			`test_h_gr r4, 0x11111111`
93			`test_h_gr r5, 0x11111111`
94
95			`# Test Signed Halfword Minimum`
96
97			`mvi_h_gr r0, 0x12345678`
98			`mvi_h_gr r1, 0x9abcde00`
99			`mvi_h_gr r2, 0x11111111`
100			`mvi_h_gr r3, 0x11111111`
101			`mvi_h_gr r4, 0`
102			`mvi_h_gr r5, 0`
103
104			`tmcrr wr0, r0, r1`
105			`tmcrr wr1, r2, r3`
106			`tmcrr wr2, r4, r5`
107
108			`wminsh wr2, wr0, wr1`
109
110			`tmrrc r0, r1, wr0`
111			`tmrrc r2, r3, wr1`
112			`tmrrc r4, r5, wr2`
113
114			`test_h_gr r0, 0x12345678`
115			`test_h_gr r1, 0x9abcde00`
116			`test_h_gr r2, 0x11111111`
117			`test_h_gr r3, 0x11111111`
118			`test_h_gr r4, 0x11111111`
119			`test_h_gr r5, 0x9abcde00`
120
121			`# Test Unsigned Word Minimum`
122
123			`mvi_h_gr r0, 0x12345678`
124			`mvi_h_gr r1, 0x9abcde00`
125			`mvi_h_gr r2, 0x11111111`
126			`mvi_h_gr r3, 0x11111111`
127			`mvi_h_gr r4, 0`
128			`mvi_h_gr r5, 0`
129
130			`tmcrr wr0, r0, r1`
131			`tmcrr wr1, r2, r3`
132			`tmcrr wr2, r4, r5`
133
134			`wminuw wr2, wr0, wr1`
135
136			`tmrrc r0, r1, wr0`
137			`tmrrc r2, r3, wr1`
138			`tmrrc r4, r5, wr2`
139
140			`test_h_gr r0, 0x12345678`
141			`test_h_gr r1, 0x9abcde00`
142			`test_h_gr r2, 0x11111111`
143			`test_h_gr r3, 0x11111111`
144			`test_h_gr r4, 0x11111111`
145			`test_h_gr r5, 0x11111111`
146
147			`# Test Signed Word Minimum`
148
149			`mvi_h_gr r0, 0x12345678`
150			`mvi_h_gr r1, 0x9abcde00`
151			`mvi_h_gr r2, 0x11111111`
152			`mvi_h_gr r3, 0x11111111`
153			`mvi_h_gr r4, 0`
154			`mvi_h_gr r5, 0`
155
156			`tmcrr wr0, r0, r1`
157			`tmcrr wr1, r2, r3`
158			`tmcrr wr2, r4, r5`
159
160			`wminsw wr2, wr0, wr1`
161
162			`tmrrc r0, r1, wr0`
163			`tmrrc r2, r3, wr1`
164			`tmrrc r4, r5, wr2`
165
166			`test_h_gr r0, 0x12345678`
167			`test_h_gr r1, 0x9abcde00`
168			`test_h_gr r2, 0x11111111`
169			`test_h_gr r3, 0x11111111`
170			`test_h_gr r4, 0x11111111`
171			`test_h_gr r5, 0x9abcde00`
172
173			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmin.cgs] - Blame information for rev 26