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# Intel(r) Wireless MMX(tm) technology testcase for WOR
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global wor
wor:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x00000000
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wor        wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x00000000
        test_h_gr  r4, 0x13355779
        test_h_gr  r5, 0x9abcdef0
 
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# Intel(r) Wireless MMX(tm) technology testcase for WOR`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global wor`
10			`wor:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`mvi_h_gr r0, 0x12345678`
18			`mvi_h_gr r1, 0x9abcdef0`
19			`mvi_h_gr r2, 0x11111111`
20			`mvi_h_gr r3, 0x00000000`
21			`mvi_h_gr r4, 0`
22			`mvi_h_gr r5, 0`
23
24			`tmcrr wr0, r0, r1`
25			`tmcrr wr1, r2, r3`
26			`tmcrr wr2, r4, r5`
27
28			`wor wr2, wr0, wr1`
29
30			`tmrrc r0, r1, wr0`
31			`tmrrc r2, r3, wr1`
32			`tmrrc r4, r5, wr2`
33
34			`test_h_gr r0, 0x12345678`
35			`test_h_gr r1, 0x9abcdef0`
36			`test_h_gr r2, 0x11111111`
37			`test_h_gr r3, 0x00000000`
38			`test_h_gr r4, 0x13355779`
39			`test_h_gr r5, 0x9abcdef0`
40
41			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wor.cgs] - Blame information for rev 26