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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [hw/] [rv-n-cris/] [trivial5.ms] - Blame information for rev 26

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#mach: crisv10 crisv32
#sim(crisv10): --hw-device "/rv/trace? true"
#sim(crisv32): --hw-device "/rv/trace? true"
#output: /rv: WD\n
#output: /rv: REG R 0xd0000032\n
#output: /rv: := 0xabcdef01\n
#output: /rv: REG W 0xd0000036 := 0xaabbccdd\n
#output: /rv: REG R 0xd0000036\n
#output: /rv: := 0x76543210\n
#output: pass\n
 
# Test trace output for read and write.
 
#r @,@srcdir@/trivial4.r
 
 .include "trivial4.ms"

Line No.	Rev	Author	Line
1	26	jlechner	`#mach: crisv10 crisv32`
2			`#sim(crisv10): --hw-device "/rv/trace? true"`
3			`#sim(crisv32): --hw-device "/rv/trace? true"`
4			`#output: /rv: WD\n`
5			`#output: /rv: REG R 0xd0000032\n`
6			`#output: /rv: := 0xabcdef01\n`
7			`#output: /rv: REG W 0xd0000036 := 0xaabbccdd\n`
8			`#output: /rv: REG R 0xd0000036\n`
9			`#output: /rv: := 0x76543210\n`
10			`#output: pass\n`
11
12			`# Test trace output for read and write.`
13
14			`#r @,@srcdir@/trivial4.r`
15
16			`.include "trivial4.ms"`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [hw/] [rv-n-cris/] [trivial5.ms] - Blame information for rev 26