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# frv testcase for bclelr $ICCi,$ccond,$hint
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global bclelr
bclelr:
        ; ccond is true
        set_spr_immed   128,lcr
        set_spr_addr    bad,lr
        set_icc         0x0 0
        bclelr          icc0,0,0
 
        set_spr_addr    bad,lr
        set_icc         0x1 1
        bclelr          icc1,0,1
 
        set_spr_addr    ok3,lr
        set_icc         0x2 2
        bclelr          icc2,0,2
        fail
ok3:
        set_spr_addr    ok4,lr
        set_icc         0x3 3
        bclelr          icc3,0,3
        fail
ok4:
        set_spr_addr    ok5,lr
        set_icc         0x4 0
        bclelr          icc0,0,0
        fail
ok5:
        set_spr_addr    ok6,lr
        set_icc         0x5 1
        bclelr          icc1,0,1
        fail
ok6:
        set_spr_addr    ok7,lr
        set_icc         0x6 2
        bclelr          icc2,0,2
        fail
ok7:
        set_spr_addr    ok8,lr
        set_icc         0x7 3
        bclelr          icc3,0,3
        fail
ok8:
        set_spr_addr    ok9,lr
        set_icc         0x8 0
        bclelr          icc0,0,0
        fail
ok9:
        set_spr_addr    oka,lr
        set_icc         0x9 1
        bclelr          icc1,0,1
        fail
oka:
        set_spr_addr    bad,lr
        set_icc         0xa 2
        bclelr          icc2,0,2
 
        set_spr_addr    bad,lr
        set_icc         0xb 3
        bclelr          icc3,0,3
 
        set_spr_addr    okd,lr
        set_icc         0xc 0
        bclelr          icc0,0,0
        fail
okd:
        set_spr_addr    oke,lr
        set_icc         0xd 1
        bclelr          icc1,0,1
        fail
oke:
        set_spr_addr    okf,lr
        set_icc         0xe 2
        bclelr          icc2,0,2
        fail
okf:
        set_spr_addr    okg,lr
        set_icc         0xf 3
        bclelr          icc3,0,3
        fail
okg:
 
        ; ccond is true
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0x0 0
        bclelr          icc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0x1 1
        bclelr          icc1,1,1
 
        set_spr_immed   1,lcr
        set_spr_addr    okj,lr
        set_icc         0x2 2
        bclelr          icc2,1,2
        fail
okj:
        set_spr_immed   1,lcr
        set_spr_addr    okk,lr
        set_icc         0x3 3
        bclelr          icc3,1,3
        fail
okk:
        set_spr_immed   1,lcr
        set_spr_addr    okl,lr
        set_icc         0x4 0
        bclelr          icc0,1,0
        fail
okl:
        set_spr_immed   1,lcr
        set_spr_addr    okm,lr
        set_icc         0x5 1
        bclelr          icc1,1,1
        fail
okm:
        set_spr_immed   1,lcr
        set_spr_addr    okn,lr
        set_icc         0x6 2
        bclelr          icc2,1,2
        fail
okn:
        set_spr_immed   1,lcr
        set_spr_addr    oko,lr
        set_icc         0x7 3
        bclelr          icc3,1,3
        fail
oko:
        set_spr_immed   1,lcr
        set_spr_addr    okp,lr
        set_icc         0x8 0
        bclelr          icc0,1,0
        fail
okp:
        set_spr_immed   1,lcr
        set_spr_addr    okq,lr
        set_icc         0x9 1
        bclelr          icc1,1,1
        fail
okq:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0xa 2
        bclelr          icc2,1,2
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0xb 3
        bclelr          icc3,1,3
 
        set_spr_immed   1,lcr
        set_spr_addr    okt,lr
        set_icc         0xc 0
        bclelr          icc0,1,0
        fail
okt:
        set_spr_immed   1,lcr
        set_spr_addr    oku,lr
        set_icc         0xd 1
        bclelr          icc1,1,1
        fail
oku:
        set_spr_immed   1,lcr
        set_spr_addr    okv,lr
        set_icc         0xe 2
        bclelr          icc2,1,2
        fail
okv:
        set_spr_immed   1,lcr
        set_spr_addr    okw,lr
        set_icc         0xf 3
        bclelr          icc3,1,3
        fail
okw:
        ; ccond is false
        set_spr_immed   128,lcr
        set_spr_addr    bad,lr
        set_icc         0x0 0
        bclelr          icc0,1,0
 
        set_icc         0x1 1
        bclelr          icc1,1,1
 
        set_icc         0x2 2
        bclelr          icc2,1,2
 
        set_icc         0x3 3
        bclelr          icc3,1,3
 
        set_icc         0x4 0
        bclelr          icc0,1,0
 
        set_icc         0x5 1
        bclelr          icc1,1,1
 
        set_icc         0x6 2
        bclelr          icc2,1,2
 
        set_icc         0x7 3
        bclelr          icc3,1,3
 
        set_icc         0x8 0
        bclelr          icc0,1,0
 
        set_icc         0x9 1
        bclelr          icc1,1,1
 
        set_icc         0xa 2
        bclelr          icc2,1,2
 
        set_icc         0xb 3
        bclelr          icc3,1,3
 
        set_icc         0xc 0
        bclelr          icc0,1,0
 
        set_icc         0xd 1
        bclelr          icc1,1,1
 
        set_icc         0xe 2
        bclelr          icc2,1,2
 
        set_icc         0xf 3
        bclelr          icc3,1,3
 
        ; ccond is false
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0x0 0
        bclelr          icc0,0,0
 
        set_spr_immed   1,lcr
        set_icc         0x1 1
        bclelr          icc1,0,1
 
        set_spr_immed   1,lcr
        set_icc         0x2 2
        bclelr          icc2,0,2
 
        set_spr_immed   1,lcr
        set_icc         0x3 3
        bclelr          icc3,0,3
 
        set_spr_immed   1,lcr
        set_icc         0x4 0
        bclelr          icc0,0,0
 
        set_spr_immed   1,lcr
        set_icc         0x5 1
        bclelr          icc1,0,1
 
        set_spr_immed   1,lcr
        set_icc         0x6 2
        bclelr          icc2,0,2
 
        set_spr_immed   1,lcr
        set_icc         0x7 3
        bclelr          icc3,0,3
 
        set_spr_immed   1,lcr
        set_icc         0x8 0
        bclelr          icc0,0,0
 
        set_spr_immed   1,lcr
        set_icc         0x9 1
        bclelr          icc1,0,1
 
        set_spr_immed   1,lcr
        set_icc         0xa 2
        bclelr          icc2,0,2
 
        set_spr_immed   1,lcr
        set_icc         0xb 3
        bclelr          icc3,0,3
 
        set_spr_immed   1,lcr
        set_icc         0xc 0
        bclelr          icc0,0,0
 
        set_spr_immed   1,lcr
        set_icc         0xd 1
        bclelr          icc1,0,1
 
        set_spr_immed   1,lcr
        set_icc         0xe 2
        bclelr          icc2,0,2
 
        set_spr_immed   1,lcr
        set_icc         0xf 3
        bclelr          icc3,0,3
 
        pass
bad:
        fail

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [bclelr.cgs] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jlechner	`# frv testcase for bclelr $ICCi,$ccond,$hint`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global bclelr`
9			`bclelr:`
10			`; ccond is true`
11			`set_spr_immed 128,lcr`
12			`set_spr_addr bad,lr`
13			`set_icc 0x0 0`
14			`bclelr icc0,0,0`
15
16			`set_spr_addr bad,lr`
17			`set_icc 0x1 1`
18			`bclelr icc1,0,1`
19
20			`set_spr_addr ok3,lr`
21			`set_icc 0x2 2`
22			`bclelr icc2,0,2`
23			`fail`
24			`ok3:`
25			`set_spr_addr ok4,lr`
26			`set_icc 0x3 3`
27			`bclelr icc3,0,3`
28			`fail`
29			`ok4:`
30			`set_spr_addr ok5,lr`
31			`set_icc 0x4 0`
32			`bclelr icc0,0,0`
33			`fail`
34			`ok5:`
35			`set_spr_addr ok6,lr`
36			`set_icc 0x5 1`
37			`bclelr icc1,0,1`
38			`fail`
39			`ok6:`
40			`set_spr_addr ok7,lr`
41			`set_icc 0x6 2`
42			`bclelr icc2,0,2`
43			`fail`
44			`ok7:`
45			`set_spr_addr ok8,lr`
46			`set_icc 0x7 3`
47			`bclelr icc3,0,3`
48			`fail`
49			`ok8:`
50			`set_spr_addr ok9,lr`
51			`set_icc 0x8 0`
52			`bclelr icc0,0,0`
53			`fail`
54			`ok9:`
55			`set_spr_addr oka,lr`
56			`set_icc 0x9 1`
57			`bclelr icc1,0,1`
58			`fail`
59			`oka:`
60			`set_spr_addr bad,lr`
61			`set_icc 0xa 2`
62			`bclelr icc2,0,2`
63
64			`set_spr_addr bad,lr`
65			`set_icc 0xb 3`
66			`bclelr icc3,0,3`
67
68			`set_spr_addr okd,lr`
69			`set_icc 0xc 0`
70			`bclelr icc0,0,0`
71			`fail`
72			`okd:`
73			`set_spr_addr oke,lr`
74			`set_icc 0xd 1`
75			`bclelr icc1,0,1`
76			`fail`
77			`oke:`
78			`set_spr_addr okf,lr`
79			`set_icc 0xe 2`
80			`bclelr icc2,0,2`
81			`fail`
82			`okf:`
83			`set_spr_addr okg,lr`
84			`set_icc 0xf 3`
85			`bclelr icc3,0,3`
86			`fail`
87			`okg:`
88
89			`; ccond is true`
90			`set_spr_immed 1,lcr`
91			`set_spr_addr bad,lr`
92			`set_icc 0x0 0`
93			`bclelr icc0,1,0`
94
95			`set_spr_immed 1,lcr`
96			`set_spr_addr bad,lr`
97			`set_icc 0x1 1`
98			`bclelr icc1,1,1`
99
100			`set_spr_immed 1,lcr`
101			`set_spr_addr okj,lr`
102			`set_icc 0x2 2`
103			`bclelr icc2,1,2`
104			`fail`
105			`okj:`
106			`set_spr_immed 1,lcr`
107			`set_spr_addr okk,lr`
108			`set_icc 0x3 3`
109			`bclelr icc3,1,3`
110			`fail`
111			`okk:`
112			`set_spr_immed 1,lcr`
113			`set_spr_addr okl,lr`
114			`set_icc 0x4 0`
115			`bclelr icc0,1,0`
116			`fail`
117			`okl:`
118			`set_spr_immed 1,lcr`
119			`set_spr_addr okm,lr`
120			`set_icc 0x5 1`
121			`bclelr icc1,1,1`
122			`fail`
123			`okm:`
124			`set_spr_immed 1,lcr`
125			`set_spr_addr okn,lr`
126			`set_icc 0x6 2`
127			`bclelr icc2,1,2`
128			`fail`
129			`okn:`
130			`set_spr_immed 1,lcr`
131			`set_spr_addr oko,lr`
132			`set_icc 0x7 3`
133			`bclelr icc3,1,3`
134			`fail`
135			`oko:`
136			`set_spr_immed 1,lcr`
137			`set_spr_addr okp,lr`
138			`set_icc 0x8 0`
139			`bclelr icc0,1,0`
140			`fail`
141			`okp:`
142			`set_spr_immed 1,lcr`
143			`set_spr_addr okq,lr`
144			`set_icc 0x9 1`
145			`bclelr icc1,1,1`
146			`fail`
147			`okq:`
148			`set_spr_immed 1,lcr`
149			`set_spr_addr bad,lr`
150			`set_icc 0xa 2`
151			`bclelr icc2,1,2`
152
153			`set_spr_immed 1,lcr`
154			`set_spr_addr bad,lr`
155			`set_icc 0xb 3`
156			`bclelr icc3,1,3`
157
158			`set_spr_immed 1,lcr`
159			`set_spr_addr okt,lr`
160			`set_icc 0xc 0`
161			`bclelr icc0,1,0`
162			`fail`
163			`okt:`
164			`set_spr_immed 1,lcr`
165			`set_spr_addr oku,lr`
166			`set_icc 0xd 1`
167			`bclelr icc1,1,1`
168			`fail`
169			`oku:`
170			`set_spr_immed 1,lcr`
171			`set_spr_addr okv,lr`
172			`set_icc 0xe 2`
173			`bclelr icc2,1,2`
174			`fail`
175			`okv:`
176			`set_spr_immed 1,lcr`
177			`set_spr_addr okw,lr`
178			`set_icc 0xf 3`
179			`bclelr icc3,1,3`
180			`fail`
181			`okw:`
182			`; ccond is false`
183			`set_spr_immed 128,lcr`
184			`set_spr_addr bad,lr`
185			`set_icc 0x0 0`
186			`bclelr icc0,1,0`
187
188			`set_icc 0x1 1`
189			`bclelr icc1,1,1`
190
191			`set_icc 0x2 2`
192			`bclelr icc2,1,2`
193
194			`set_icc 0x3 3`
195			`bclelr icc3,1,3`
196
197			`set_icc 0x4 0`
198			`bclelr icc0,1,0`
199
200			`set_icc 0x5 1`
201			`bclelr icc1,1,1`
202
203			`set_icc 0x6 2`
204			`bclelr icc2,1,2`
205
206			`set_icc 0x7 3`
207			`bclelr icc3,1,3`
208
209			`set_icc 0x8 0`
210			`bclelr icc0,1,0`
211
212			`set_icc 0x9 1`
213			`bclelr icc1,1,1`
214
215			`set_icc 0xa 2`
216			`bclelr icc2,1,2`
217
218			`set_icc 0xb 3`
219			`bclelr icc3,1,3`
220
221			`set_icc 0xc 0`
222			`bclelr icc0,1,0`
223
224			`set_icc 0xd 1`
225			`bclelr icc1,1,1`
226
227			`set_icc 0xe 2`
228			`bclelr icc2,1,2`
229
230			`set_icc 0xf 3`
231			`bclelr icc3,1,3`
232
233			`; ccond is false`
234			`set_spr_immed 1,lcr`
235			`set_spr_addr bad,lr`
236			`set_icc 0x0 0`
237			`bclelr icc0,0,0`
238
239			`set_spr_immed 1,lcr`
240			`set_icc 0x1 1`
241			`bclelr icc1,0,1`
242
243			`set_spr_immed 1,lcr`
244			`set_icc 0x2 2`
245			`bclelr icc2,0,2`
246
247			`set_spr_immed 1,lcr`
248			`set_icc 0x3 3`
249			`bclelr icc3,0,3`
250
251			`set_spr_immed 1,lcr`
252			`set_icc 0x4 0`
253			`bclelr icc0,0,0`
254
255			`set_spr_immed 1,lcr`
256			`set_icc 0x5 1`
257			`bclelr icc1,0,1`
258
259			`set_spr_immed 1,lcr`
260			`set_icc 0x6 2`
261			`bclelr icc2,0,2`
262
263			`set_spr_immed 1,lcr`
264			`set_icc 0x7 3`
265			`bclelr icc3,0,3`
266
267			`set_spr_immed 1,lcr`
268			`set_icc 0x8 0`
269			`bclelr icc0,0,0`
270
271			`set_spr_immed 1,lcr`
272			`set_icc 0x9 1`
273			`bclelr icc1,0,1`
274
275			`set_spr_immed 1,lcr`
276			`set_icc 0xa 2`
277			`bclelr icc2,0,2`
278
279			`set_spr_immed 1,lcr`
280			`set_icc 0xb 3`
281			`bclelr icc3,0,3`
282
283			`set_spr_immed 1,lcr`
284			`set_icc 0xc 0`
285			`bclelr icc0,0,0`
286
287			`set_spr_immed 1,lcr`
288			`set_icc 0xd 1`
289			`bclelr icc1,0,1`
290
291			`set_spr_immed 1,lcr`
292			`set_icc 0xe 2`
293			`bclelr icc2,0,2`
294
295			`set_spr_immed 1,lcr`
296			`set_icc 0xf 3`
297			`bclelr icc3,0,3`
298
299			`pass`
300			`bad:`
301			`fail`